CN110149249A - A kind of vector network analyzer test function extension system and method - Google Patents
A kind of vector network analyzer test function extension system and method Download PDFInfo
- Publication number
- CN110149249A CN110149249A CN201910568613.8A CN201910568613A CN110149249A CN 110149249 A CN110149249 A CN 110149249A CN 201910568613 A CN201910568613 A CN 201910568613A CN 110149249 A CN110149249 A CN 110149249A
- Authority
- CN
- China
- Prior art keywords
- test
- network analyzer
- vector network
- data
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 240
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000012545 processing Methods 0.000 claims abstract description 30
- 230000006870 function Effects 0.000 claims description 33
- 238000012544 monitoring process Methods 0.000 claims description 15
- 238000010408 sweeping Methods 0.000 claims description 11
- 238000012937 correction Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 125000004122 cyclic group Chemical group 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 238000005259 measurement Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 238000004590 computer program Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/04—Processing captured monitoring data, e.g. for logfile generation
- H04L43/045—Processing captured monitoring data, e.g. for logfile generation for graphical visualisation of monitoring data
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/14—Arrangements for monitoring or testing data switching networks using software, i.e. software packages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Mining & Analysis (AREA)
- Computer Security & Cryptography (AREA)
- Environmental & Geological Engineering (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The present invention provides a kind of vector network analyzer test function extension system and method, specifically includes that control module, data acquisition module, data processing module and aobvious control interface module；Data acquisition module is used to read calibration data and test data from vector network analyzer；Data processing module is for being fitted processing to test data；The setting that aobvious control interface module is used to be inputted according to user instructs, the running parameter and operating mode of vector network analyzer are set, realize the control and reading data to vector network analyzer, and control instruction is sent to control module, test data is distributed on the display for dividing aobvious computer accordingly by control module and is shown.The present invention is by designing corresponding control circuit and data processing algorithm, based on single vector Network Analyzer, carries out batch expansion to its test function and significantly reduces production cost, and improve production efficiency under the premise of keeping its test performance.
Description
Technical Field
The invention relates to the technical field of testing and inspection of microwave devices, in particular to a system and a method for expanding a testing function of a vector network analyzer.
Background
The vector network analyzer is a test device for electromagnetic wave energy; it can measure the amplitude of various parameters of single-port network or two-port network, and can measure phase position. The vector network analyzer can display test data by using a Smith chart, and is more convenient for engineering application and debugging. The vector network analyzer has many functions, is called as 'king of instrument', is a universal meter in the field of radio frequency microwaves, and has higher requirements on professional techniques of users; the vector network analyzer is mainly divided according to frequency, and the higher the frequency is, the higher the price is.
In the production process and production inspection links of the microwave device, the amplitude-frequency characteristic needs to be measured by using a vector network analyzer at any time so as to judge whether the microwave device meets the design requirements. However, the existing vector network analyzer is very costly and not suitable for multiple production stations and large-scale applications where testing or inspection is at all times possible.
Disclosure of Invention
The invention provides a system and a method for expanding the test function of a vector network analyzer; by designing a corresponding control circuit and a data processing algorithm and based on a single vector network analyzer, the test function of the vector network analyzer is expanded in batch, and on the premise of keeping the test performance, the production cost is reduced and the production efficiency is improved.
In order to solve the technical problem, the invention provides a test function expanding system of a vector network analyzer, wherein the vector network analyzer comprises a plurality of test ports, each test port is respectively allocated to different test stations, each test port corresponds to a test station and is used for testing a device to be tested on the corresponding test station, and each test port is respectively allocated with a unique address;
the vector network analyzer test function expanding system comprises: the device comprises a control module, a data acquisition module, a data processing module and a display control interface module; wherein,
the data acquisition module is used for reading calibration data from the vector network analyzer before the test is started, and the control module is used for correcting each test port; after the test is finished, reading test data from the vector network analyzer;
the data processing module is used for fitting the test data acquired by the data acquisition module; the display control interface module is used for setting working parameters and working modes of the vector network analyzer according to a setting instruction input by a user, realizing control and data reading of the vector network analyzer, sending a control instruction to the control module after the data processing module performs fitting processing on test data, and distributing the fitted test data to a display of a corresponding sub-display computer through the control module for displaying.
Furthermore, the number of the test ports of the vector network analyzer is eight, and the eight test ports are correspondingly distributed to eight test stations; correspondingly, the number of the sub-display computers is eight, and each test station is correspondingly provided with one sub-display computer.
Further, when the data acquisition module acquires data, reading calibration data and test data from the vector network analyzer through a general interface bus GP-IB;
and when the data processing module fits the test data, fitting the test data in a polynomial interpolation fitting mode.
Correspondingly, in order to solve the above technical problem, the present invention further provides a method for expanding the test function of a vector network analyzer, wherein the method for expanding the test function of the vector network analyzer comprises:
step one, respectively allocating a plurality of test ports of a vector network analyzer to a plurality of test stations, wherein each test port corresponds to one test station and is used for testing a device to be tested of the corresponding station, and each test port is respectively allocated with a unique address;
setting working parameters and a working mode of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode;
step three, monitoring whether each test port is accessed with a device to be tested in real time, and when one test port is monitored to be accessed with the device to be tested, distributing test resources according to the current working condition of the vector network analyzer and continuously acquiring test data of the device to be tested;
and step four, fitting the complete test data after the complete test data of the device to be tested is acquired, and sending the fitted data to a display of a corresponding sub-display computer for display according to the address of a corresponding test port so as to allow an operator to check the test result.
Furthermore, in the first step, the number of the test ports of the vector network analyzer is eight, and the eight test ports are correspondingly distributed to eight test stations;
correspondingly, the number of the sub-display computers in the fourth step is eight, and each test station is correspondingly provided with one sub-display computer.
Further, the second step comprises:
carrying out port correction on each test port of the vector network analyzer;
setting a working mode of the vector network analyzer on a main control computer, and sending a control instruction to the vector network analyzer through a general interface bus GP-IB;
and setting the starting frequency, the ending frequency and the number of frequency sweeping points of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode.
Further, the port calibration of each test port of the vector network analyzer specifically includes:
inputting a starting frequency, a terminating frequency, a test point number and a port number to be corrected through a main control computer;
and reading the correction file from the vector network analyzer through a general interface bus GP-IB to finish the correction of the corresponding test port.
Further, the third step includes:
automatically monitoring the input condition of each test port in a multi-detector parallel monitoring mode;
when monitoring that a corresponding test port is accessed by a device to be tested, automatically recording the address of the test port and the real-time working condition of the current vector network analyzer, and allocating test resources to start testing the device to be tested;
after the test is started, the current test port number, the current test frequency point information of the vector network analyzer and the time information are automatically recorded until all the frequency points of the test port are tested.
Further, the fourth step includes:
after each scanning period of the vector network analyzer is finished, reading test data in the vector network analyzer;
reintegrating the data of the same test port according to the sequence of frequency from low to high, and carrying out curve fitting processing on the integrated test data;
and the test data after the fitting processing is distributed to a display of a sub-display computer corresponding to the corresponding test station through a network to be displayed, so that the test is completed.
Further, the curve fitting process is performed on the integrated test data, specifically: and fitting the test data by adopting a polynomial interpolation fitting mode.
The technical scheme of the invention has the following beneficial effects:
the invention distributes a plurality of test ports of a vector network analyzer to a plurality of test stations respectively, and distributes an address for each test port; setting working parameters and a working mode of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode; monitoring whether each test port is accessed with a device to be tested in real time;
when one of the test ports is monitored to be accessed to the device to be tested, distributing test resources according to the current working condition of the vector network analyzer and continuously acquiring test data of the device to be tested; and after the complete test data of the device to be tested is acquired, fitting the complete test data, and sending the processed data to a display of a corresponding sub-display computer for display according to the address of a corresponding test port so that an operator can check the test result. Therefore, on the basis of a single vector network analyzer, the test functions of the vector network analyzer are expanded in batches, the production cost is greatly reduced on the premise of keeping the test performance of the vector network analyzer, and the production efficiency is improved.
Drawings
Fig. 1 is a schematic diagram of software function division of a test function development system of a vector network analyzer according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of connection between a main control computer and each sub-display computer in the test function expanding system of the vector network analyzer according to the first embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
First embodiment
Referring to fig. 1 and fig. 2, the present embodiment provides a system for expanding a test function of a vector network analyzer, where the vector network analyzer includes eight test ports, the eight test ports are respectively allocated to eight different test stations, each test port corresponds to a test station and is used for testing a device to be tested on the corresponding test station, and each test port is respectively allocated with a unique address; meanwhile, each test station is correspondingly provided with a sub-display computer, namely the system comprises eight sub-display computers.
The vector network analyzer test function expanding system mainly comprises: the device comprises a control module, a data acquisition module, a data processing module and a display control interface module; the control module comprises a detection circuit, a frequency measurement circuit and a control time sequence generation circuit;
the data acquisition module is used for reading calibration data from the vector network analyzer by a general interface bus GP-IB before the test is started, and the correction of each test port is realized by the control module; after the test is finished, the general interface bus GP-IB reads the test data from the vector network analyzer; the data processing module is used for fitting the test data acquired by the data acquisition module in a polynomial interpolation fitting mode;
the display control interface module is used for setting working parameters and working modes of the vector network analyzer according to a setting instruction input by a user, realizing control and data reading of the vector network analyzer, sending a control instruction to the control module after the data processing module performs fitting processing on test data, and distributing the fitted test data to a display of a corresponding sub-display computer through the network switch by the control module for display so as to be checked and checked by an operator.
Specifically, the working principle of the system is as follows:
a) correcting each test port (1-8); and inputting the starting frequency, the terminating frequency, the number of measurement points and the port number to be corrected from a display control interface of the master control computer. The correction file is read from the vector network analyzer via the GP-IB, stored and displayed on the respective display.
b) Monitoring in parallel through the first detector and the second detector to obtain signals at the first port and the second port and switching time sequences of the first port and the second port;
c) the Mini IFM (instantaneous frequency measurement) measures the instantaneous frequency, 20us pulse width chopping is adopted, 4-level frequency division is adopted, the frequency corresponding to 400 MHz-300 MHz is 25 MHz-187.5 MHz, and the frequency measurement precision can reach 0.03MHz (r.m.s);
d) learning the output frequency characteristic of the vector network analyzer through IFM frequency measurement;
e) judging and switching output ports of the first switch and the second switch according to the frequency measured by the Mini IFM and the measurement of the first detector and the second detector;
f) reading the measurement data of the vector network analyzer through the GP-IB interface after each measurement of the frequency range is finished;
g) sorting the corresponding relation between the measured data and the port according to the measured data and the control time sequence;
h) adopting data fitting to output 801 point measurement data of eight measurement ports;
i) the respective measurement data are displayed on the displays of the eight sub-display computers.
The control sequence of the system is as follows:
a) after the vector network analyzer sets the number of scanning points, the system needs to measure the duration time of each frequency, deduces the transition time between frequency points according to the duration time, and the duration time is used for determining the switching time point of the switch.
b) And judging according to the detection signal, and reading corresponding test data when the vector network analyzer finishes measurement.
c) The system software reassembles the measured data into new data packets based on the measured data and the switch position data.
d) And the master control software performs interpolation fitting on the recombined data to generate a data packet of each tested piece.
e) The data packets are distributed to different displays for display.
The system of the embodiment expands the test function of a single vector network analyzer in batch on the basis of designing a corresponding control circuit and a data processing algorithm, realizes the measurement of the microwave devices to be tested of eight test stations by adopting a time-sharing measurement method through the vector network expander, and distributes the measurement data to the sub-display computers corresponding to the test stations through a network after processing the measurement data to display. The requirement of simultaneous measurement of eight test stations is met. On the premise of keeping the test performance, the production cost is reduced, and the production efficiency is improved.
Second embodiment
The embodiment provides a test function expanding method for a vector network analyzer, which comprises the following steps:
step one, respectively allocating eight test ports of a vector network analyzer to eight test stations, wherein each test port corresponds to one test station and is used for testing a device to be tested of the corresponding station, and each test port is allocated with a unique address;
setting working parameters and a working mode of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode;
it should be noted that the specific implementation process of the above steps is as follows:
inputting a starting frequency, a terminating frequency, a test point number and a port number to be corrected through a main control computer;
reading a correction file from the vector network analyzer through a general interface bus GP-IB to finish the correction of the corresponding test port;
setting a working mode of the vector network analyzer on a main control computer, and sending a control instruction to the vector network analyzer through a general interface bus GP-IB;
and setting the starting frequency, the ending frequency and the number of frequency sweeping points of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode.
Step three, monitoring whether each test port is accessed with a device to be tested in real time, and when one test port is monitored to be accessed with the device to be tested, distributing test resources according to the current working condition of the vector network analyzer and continuously acquiring test data of the device to be tested;
it should be noted that the specific implementation process of the above steps is as follows:
automatically monitoring the input condition of each test port in a multi-detector parallel monitoring mode;
when monitoring that a corresponding test port is accessed by a device to be tested, automatically recording the address of the test port and the real-time working condition of the current vector network analyzer, and allocating test resources to start testing the device to be tested;
after the test is started, the current test port number, the current test frequency point information of the vector network analyzer and the time information are automatically recorded until all the frequency points of the test port are tested.
And step four, fitting the complete test data after the complete test data of the device to be tested is acquired, and sending the fitted data to a display of a corresponding sub-display computer for display according to the address of a corresponding test port so as to allow an operator to check the test result.
It should be noted that the specific implementation process of the above steps is as follows:
after each scanning period of the vector network analyzer is finished, reading test data in the vector network analyzer;
data of the same test port are reintegrated according to the sequence of frequency from low to high, and the integrated test data are fitted in a polynomial interpolation fitting mode;
and the test data after the fitting processing is distributed to a display of a sub-display computer corresponding to the corresponding test station through a network to be displayed, so that the test is completed.
Furthermore, it should be noted that, in the above steps, the data of the same test port is reintegrated in a sequence from low to high in frequency, because the time when the device to be tested is accessed to the vector network analyzer is arbitrary, the current frequency point at which the device to be tested starts to measure is also uncertain, and therefore, the data recorded by the main control computer that the device to be tested is accessed to the test port needs to be rearranged in a sequence from small to large in frequency.
The invention distributes a plurality of test ports of a vector network analyzer to a plurality of test stations respectively, and distributes an address for each test port; setting working parameters and a working mode of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode; monitoring whether each test port is accessed with a device to be tested in real time;
when one of the test ports is monitored to be accessed to the device to be tested, distributing test resources according to the current working condition of the vector network analyzer and continuously acquiring test data of the device to be tested; and after the complete test data of the device to be tested is acquired, fitting the complete test data, and sending the processed data to a display of a corresponding sub-display computer for display according to the address of a corresponding test port so that an operator can check the test result. Therefore, on the basis of a single vector network analyzer, the test functions of the vector network analyzer are expanded in batches, the production cost is greatly reduced on the premise of keeping the test performance of the vector network analyzer, and the production efficiency is improved.
Furthermore, it should be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
It should also be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (10)
1. A test function expanding system of a vector network analyzer is characterized in that the vector network analyzer comprises a plurality of test ports, each test port is respectively allocated to different test stations, each test port corresponds to a test station and is used for testing a device to be tested on the corresponding test station, and each test port is respectively allocated with a unique address;
the vector network analyzer test function expanding system comprises: the device comprises a control module, a data acquisition module, a data processing module and a display control interface module; wherein,
the data acquisition module is used for reading calibration data from the vector network analyzer before the test is started, and the control module is used for correcting each test port; after the test is finished, reading test data from the vector network analyzer;
the data processing module is used for fitting the test data acquired by the data acquisition module; the display control interface module is used for setting working parameters and working modes of the vector network analyzer according to a setting instruction input by a user, realizing control and data reading of the vector network analyzer, sending a control instruction to the control module after the data processing module performs fitting processing on test data, and distributing the fitted test data to a display of a corresponding sub-display computer through the control module for displaying.
2. The system for expanding the test function of the vector network analyzer as claimed in claim 1, wherein the number of the test ports of the vector network analyzer is eight, and the eight test ports are correspondingly distributed to eight test stations; correspondingly, the number of the sub-display computers is eight, and each test station is correspondingly provided with one sub-display computer.
3. The system for expanding the test function of the vector network analyzer as claimed in claim 1, wherein when the data acquisition module acquires data, the data acquisition module reads calibration data and test data from the vector network analyzer through a general interface bus GP-IB;
and when the data processing module fits the test data, fitting the test data in a polynomial interpolation fitting mode.
4. A test function expanding method of a vector network analyzer is characterized by comprising the following steps:
step one, respectively allocating a plurality of test ports of a vector network analyzer to a plurality of test stations, wherein each test port corresponds to one test station and is used for testing a device to be tested of the corresponding station, and each test port is respectively allocated with a unique address;
setting working parameters and a working mode of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode;
step three, monitoring whether each test port is accessed with a device to be tested in real time, and when one test port is monitored to be accessed with the device to be tested, distributing test resources according to the current working condition of the vector network analyzer and continuously acquiring test data of the device to be tested;
and step four, fitting the complete test data after the complete test data of the device to be tested is acquired, and sending the fitted data to a display of a corresponding sub-display computer for display according to the address of a corresponding test port so as to allow an operator to check the test result.
5. The method for expanding the test functions of the vector network analyzer as claimed in claim 4, wherein in the first step, the number of the test ports of the vector network analyzer is eight, and the eight test ports are correspondingly distributed to eight test stations;
correspondingly, the number of the sub-display computers in the fourth step is eight, and each test station is correspondingly provided with one sub-display computer.
6. The vector network analyzer test function expanding method according to claim 4, wherein the second step includes:
carrying out port correction on each test port of the vector network analyzer;
setting a working mode of the vector network analyzer on a main control computer, and sending a control instruction to the vector network analyzer through a general interface bus GP-IB;
and setting the starting frequency, the ending frequency and the number of frequency sweeping points of the vector network analyzer to enable the vector network analyzer to work in a cyclic frequency sweeping working mode.
7. The method for expanding the test function of the vector network analyzer according to claim 6, wherein the port calibration is performed on each test port of the vector network analyzer, and specifically comprises:
inputting a starting frequency, a terminating frequency, a test point number and a port number to be corrected through a main control computer;
and reading the correction file from the vector network analyzer through a general interface bus GP-IB to finish the correction of the corresponding test port.
8. The vector network analyzer test function expanding method according to claim 4, wherein the third step includes:
automatically monitoring the input condition of each test port in a multi-detector parallel monitoring mode;
when monitoring that a corresponding test port is accessed by a device to be tested, automatically recording the address of the test port and the real-time working condition of the current vector network analyzer, and allocating test resources to start testing the device to be tested;
after the test is started, the current test port number, the current test frequency point information of the vector network analyzer and the time information are automatically recorded until all the frequency points of the test port are tested.
9. The vector network analyzer test function expanding method according to claim 4, wherein the fourth step includes:
after each scanning period of the vector network analyzer is finished, reading test data in the vector network analyzer;
reintegrating the data of the same test port according to the sequence of frequency from low to high, and carrying out curve fitting processing on the integrated test data;
and the test data after the fitting processing is distributed to a display of a sub-display computer corresponding to the corresponding test station through a network to be displayed, so that the test is completed.
10. The method for expanding the test function of the vector network analyzer according to claim 9, wherein the curve fitting process is performed on the integrated test data, and specifically comprises: and fitting the test data by adopting a polynomial interpolation fitting mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910568613.8A CN110149249A (en) | 2019-06-27 | 2019-06-27 | A kind of vector network analyzer test function extension system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910568613.8A CN110149249A (en) | 2019-06-27 | 2019-06-27 | A kind of vector network analyzer test function extension system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110149249A true CN110149249A (en) | 2019-08-20 |
Family
ID=67596625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910568613.8A Pending CN110149249A (en) | 2019-06-27 | 2019-06-27 | A kind of vector network analyzer test function extension system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110149249A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110460503A (en) * | 2019-09-17 | 2019-11-15 | 昆山普尚电子科技有限公司 | Network Analyzer stability test method |
| CN111766425A (en) * | 2020-06-18 | 2020-10-13 | 深圳市极致汇仪科技有限公司 | Vector network analyzer supporting multi-port parallel test |
| CN113759370A (en) * | 2021-08-10 | 2021-12-07 | 桂林电子科技大学 | Multi-user electromagnetic wave imaging and measuring system based on CTDM technology |
| CN114522908A (en) * | 2022-02-16 | 2022-05-24 | 上海华岭集成电路技术股份有限公司 | System and method for improving abnormal inspection efficiency of test workshop |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040162689A1 (en) * | 2003-02-18 | 2004-08-19 | Tiberiu Jamneala | Multiport network analyzer calibration employing reciprocity of a device |
| CN101871973A (en) * | 2010-05-14 | 2010-10-27 | 西安电子科技大学 | Time sharing multiplex measurement system and method based on vector network analyzer |
| CN103164311A (en) * | 2011-12-16 | 2013-06-19 | 环旭电子股份有限公司 | Method for automatically testing communication function of object to be tested |
| CN204405758U (en) * | 2014-12-25 | 2015-06-17 | 苏州市大富通信技术有限公司 | The debug system of wave filter |
| CN106990302A (en) * | 2016-01-20 | 2017-07-28 | 上海原动力通信科技有限公司 | A kind of wave filter debugging system and adjustment method |
-
2019
- 2019-06-27 CN CN201910568613.8A patent/CN110149249A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040162689A1 (en) * | 2003-02-18 | 2004-08-19 | Tiberiu Jamneala | Multiport network analyzer calibration employing reciprocity of a device |
| CN101871973A (en) * | 2010-05-14 | 2010-10-27 | 西安电子科技大学 | Time sharing multiplex measurement system and method based on vector network analyzer |
| CN103164311A (en) * | 2011-12-16 | 2013-06-19 | 环旭电子股份有限公司 | Method for automatically testing communication function of object to be tested |
| CN204405758U (en) * | 2014-12-25 | 2015-06-17 | 苏州市大富通信技术有限公司 | The debug system of wave filter |
| CN106990302A (en) * | 2016-01-20 | 2017-07-28 | 上海原动力通信科技有限公司 | A kind of wave filter debugging system and adjustment method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110460503A (en) * | 2019-09-17 | 2019-11-15 | 昆山普尚电子科技有限公司 | Network Analyzer stability test method |
| CN110460503B (en) * | 2019-09-17 | 2021-03-02 | 昆山普尚电子科技有限公司 | Stability testing method for network analyzer |
| CN111766425A (en) * | 2020-06-18 | 2020-10-13 | 深圳市极致汇仪科技有限公司 | Vector network analyzer supporting multi-port parallel test |
| CN113759370A (en) * | 2021-08-10 | 2021-12-07 | 桂林电子科技大学 | Multi-user electromagnetic wave imaging and measuring system based on CTDM technology |
| CN114522908A (en) * | 2022-02-16 | 2022-05-24 | 上海华岭集成电路技术股份有限公司 | System and method for improving abnormal inspection efficiency of test workshop |
| CN114522908B (en) * | 2022-02-16 | 2024-05-03 | 上海华岭集成电路技术股份有限公司 | System and method for improving abnormal inspection efficiency of test workshop |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110149249A (en) | A kind of vector network analyzer test function extension system and method | |
| CN109725198B (en) | Afterglow generation method of frequency spectrograph and frequency spectrograph | |
| US9020496B2 (en) | System for testing mobile communication apparatus and test method therefor | |
| CN111934760B (en) | Signal processing transmission delay characteristic detection device and method and terminal equipment | |
| CN116723140B (en) | Multithreaded excitation signal configuration method based on vector network analyzer | |
| CN113315774A (en) | Instrument testing method and instrument testing device | |
| CN102752059A (en) | Automatic equipment test method and system | |
| CN103344854A (en) | Automatic test system and method for logical function device | |
| CN112985867B (en) | Steering engine testing method, device, equipment and storage medium | |
| CN114167132A (en) | Power consumption detection method and device of wireless terminal, electronic equipment and storage medium | |
| CN103698639B (en) | Crystal oscillator waveform parameter automatic measurement system and method | |
| CN111157906B (en) | SOC precision testing method, device and system | |
| CN108872902A (en) | waveform output method and device | |
| CN207752144U (en) | A kind of radar component test equipment | |
| CN103401734A (en) | Method and device for debugging signal quality of high-speed data buses | |
| CN107861033B (en) | Calibration method and system for positioning error of oscillation wave partial discharge detection system | |
| CN113419126B (en) | Performance parameter recording method and device, frequency converter, air conditioning equipment and storage medium | |
| CN105182131A (en) | General test platform and test method | |
| CN117156120A (en) | Eye diagram measuring method, eye diagram measuring device, electronic equipment and computer readable storage medium | |
| CN114638096A (en) | Method, device and equipment for displaying logic among program variables and storage medium | |
| CN114460443A (en) | System, method and storage medium for virtualization automatic test equipment | |
| WO2018072458A1 (en) | Microwave converter input isolation testing method and system | |
| CN203630784U (en) | On-chip simulating system | |
| CN108226743B (en) | Test vector generation method and device | |
| CN102447433B (en) | Rotating speed estimation method and computer readable media applying same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190820 |