CN103401734A - Method and device for debugging signal quality of high-speed data buses - Google Patents
Method and device for debugging signal quality of high-speed data buses Download PDFInfo
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Abstract
The invention discloses a method and a device for debugging signal quality of high-speed data buses, and relates to the technical field of communication. With adoption of the technical scheme of the invention, the process of debugging the high-speed data buses is simple, and the test is carried out on basis of states of practical transmission signals of the high-speed data buses, so that the debugging result is more accurate. The method specifically comprises the following steps: controlling to generate a reference signal, and inputting the reference signal into a sending terminal; sending the reference signal from the sending terminal to the receiving terminal by using the high-speed data buses and sequentially using all power weighted values in a first power weighted value set, and acquiring statistical information, wherein the number of the high-speed data buses is two at least; according to the statistical information, acquiring a second power weighted value set with the error rate not higher than a preset error rate from the first power weighted value set; according to the second power weighted value set, adjusting the transmission power of high-frequency component in the transmission signals of the high-speed data buses. The method and the device can be used for debugging the signal quality of the high-speed data buses.
Description
Technical field
The present invention relates to communication technical field, relate in particular to the method and apparatus of the signal quality debugging of high speed data bus.
Background technology
Development along with the communication technology, traffic rate presents more and more faster trend, the 10000000000 speed even interface of 100,000,000,000 speed more and more appear in the middle of communication equipment, and in order to make equipment reach two-forty, the speed of device interior bus must be not less than the speed of panel interface, and namely the speed of device interior bus may be greater than 10,000,000,000 speed.And the speed of digital signal is higher, and the clock cycle of this digital signal is shorter, and receiving terminal judges whether to sample, and to set up the retention time also shorter, at receiving terminal, erroneous judgement easily occurs and then cause error of transmission.Concrete, receiving terminal need to be sampled after the signal stabilization that receives, due to, the clock cycle of the signal that receives shortens, and receiving terminal may just not sampled when the signal that receives is stablized, therefore, cause receiving terminal may collect wrong data.
Digital signal externally shows as square wave, and essence is the stack of the sine wave of different frequency, and as shown in Figure 1, frequency is higher, and sinusoidal wave amplitude is less, and corresponding power is also just less, and namely the power of signal high fdrequency component is lower.Due to, the power of signal high fdrequency component is lower than the power of low frequency component, and therefore, in the situation that noise power is identical, the signal to noise ratio of signal high fdrequency component, less than the signal to noise ratio of low frequency component, causes the signal high fdrequency component to produce huge decay in transmission.
Data signal rate is higher, the highest frequency of the high fdrequency component that this digital signal comprises is also just higher, and power is lower on the contrary, the attenuation ratio low frequency component that produces in transmission is much bigger, in order to address this problem, a lot of equipment can improve the power weighted value (can be in fact to improve amplitude) of the signal high fdrequency component of transmitting terminal transmission by debugging, to guarantee receiving terminal, enough setting up the retention time arranged, and make receiving terminal can sample correct signal.
The method of current debugging to high speed data bus can comprise:
By register corresponding to manual configuration signal high fdrequency component weighted value; Use the waveform of high-speed oscilloscope test receiving terminal; Constantly adjust the power of signal high fdrequency component, finally make receiving terminal obtain enough setting up the retention time, can make receiving terminal sample correct signal, guarantee the optimization of transmission.
In order to reach higher speed, high speed data bus can comprise many group receiving and transmitting signal lines, and equipment comprises many group high speed data buss toward contact, every group of high speed data bus is because cabling is different, and the attenuation degree of its signal high fdrequency component is also different, causes testing respectively every group of high speed data bus respectively, cause expending more time and manpower, in addition, the high-speed oscilloscope that test is used belongs to valuable scarce resource, has increased debugging cost.
Summary of the invention
Embodiments of the invention provide a kind of method and apparatus of signal quality debugging of high speed data bus, after adopting this programme, the process that high speed data bus is debugged is simple, and in conjunction with the state of high speed data bus actual transmission signal, tests, and makes debug results more accurate.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, provide a kind of method of signal quality debugging of high speed data bus, comprising:
Control generating reference signal and be input to transmitting terminal;
Also use successively each power weighted value in the first power weighted value set that described reference signal is sent to receiving terminal and obtains statistical information from transmitting terminal by high speed data bus, described power weighted value is used for characterizing described high speed data bus and transmits the weight of the power of described reference signal high fdrequency component, described the first power weighted value set comprises at least one power weighted value, and the quantity of described high speed data bus is at least two;
Obtain error rate according to described statistical information not higher than the second power weighted value set of default error rate from described the first power weighted value set, described statistical information is used for characterizing by described high speed data bus and uses successively described each power weighted value to transmit the error rate of described reference signal;
Adjust the through-put power of described high speed data bus signal transmission high fdrequency component according to described the second power weighted value set.
Second aspect, provide a kind of device of signal quality debugging of high speed data bus, comprising:
Control module, be used for controlling generating reference signal, and the described reference signal that will generate is input to initiator block;
Initiator block, be used for receiving the described reference signal that described control module generates, also use successively each power weighted value in the first power weighted value set that described reference signal is sent to the receiving terminal module from transmitting terminal by high speed data bus, described power weighted value is used for characterizing described high speed data bus and transmits the weight of the power of described reference signal high fdrequency component, described the first power weighted value set comprises at least one power weighted value, and the quantity of described high speed data bus is at least two;
The receiving terminal module, be used for receiving the described reference signal that described initiator block sends by described high speed data bus;
Described control module, also be used for obtaining the statistical information of the described reference signal that described receiving terminal module receives, obtain error rate according to described statistical information not higher than the second power weighted value set of default error rate from described the first power weighted value set, described statistical information is used for characterizing by described high speed data bus and uses successively described each power weighted value to transmit the error rate of described reference signal; And for adjust the through-put power of described high speed data bus signal transmission high fdrequency component according to described the second power weighted value set.
The method and apparatus of the signal quality debugging of the high speed data bus that the embodiment of the present invention provides, during the real work of simulation high speed data bus, the state of signal transmission is tested high speed data bus, namely can comprise: for high speed data bus signal transmission high fdrequency component arranges different power weighted values, and obtain statistical information corresponding to each power weighted value; The power weighted value of signal transmission high fdrequency component while then according to statistical information, determining the high speed data bus real work, definite power weighted value can make the error rate of the signal that receiving terminal receives lower than default error rate.Compare with the power weighted value of adjusting the signal high fdrequency component by the mode of high-speed oscilloscope test bus receiving terminal waveform and signal quality in prior art, the process that adopts this programme to debug high speed data bus is simple, and the state in conjunction with the high speed data bus actual transmission signal is tested, make debug results more accurate, in addition, it can test many high speed data buss simultaneously, saves the testing time, improves testing efficiency.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram that concerns of square wave and sine wave;
Fig. 2 provides a kind of flow chart of method of signal quality debugging of high speed data bus for the present embodiment;
Fig. 3 provides the flow chart of method of the signal quality debugging of another kind of high speed data bus for the present embodiment;
Fig. 4 provides a kind of structural representation of device of signal quality debugging of high speed data bus for the present embodiment;
Fig. 5 provides the structural representation of device of the signal quality debugging of another kind of high speed data bus for the present embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment that obtains, belong to the scope of protection of the invention.
In prior art, in order to reach higher speed, high speed data bus can comprise many group receiving and transmitting signal lines, and equipment comprises many group high speed data buss toward contact, and every group of high speed data bus is different due to cabling, the attenuation degree of its high fdrequency component is also different, cause and need to test respectively every group of high speed data bus, cause expending more time and manpower, in addition, the high-speed oscilloscope that test is used belongs to valuable scarce resource, has increased debugging cost.
In order to address the above problem, the present embodiment provides a kind of method of signal quality debugging of high speed data bus, in order to be described following examples more clearly, at first the applied system configuration of embodiment is described, this method can be applied to electronic equipment (as, computers etc.), electronic equipment can comprise: signal generating apparatus, communication equipment, and can control signal generation generating reference signal.
The present embodiment provides a kind of executive agent of method of signal quality debugging of high speed data bus, for being arranged in electronic equipment, as shown in Figure 2, can comprise:
201, control generating reference signal and be input to transmitting terminal.
The control module of the present embodiment debugged apparatus is by controlling generating reference signal, and the state of signal transmission while with reference to signal, by high speed data bus, transmitting to simulate the high speed data bus real work, to realize the test (, for easy description, can be described as in subsequent content under test mode) to the high-speed transfer bus.The present embodiment is mainly that test mode is described, namely under test mode, by high speed data bus is tested, determine the power weighted value of high speed data bus actual transmission signal high fdrequency component, then, under the actual transmissions state, high speed data bus uses the power weighted value of the high fdrequency component of determining to carry out the transmission of signal, wherein, the power weighted value of determining makes the error rate of the signal that receiving terminal receives lower than default error rate.
In order for subsequent step, to make place mat, generating reference signal at first.
Further, the control module of debugged apparatus control generating reference signal and be input to transmitting terminal method can but be not limited to:
Utilize the tester generated data to be input to transmitting terminal as the reference signal; Or the control debugged apparatus carries out the data that produce after broadcast storm and is input to transmitting terminal as the reference signal.
The present embodiment is not construed as limiting the generation method of reference signal, is technology well known to those skilled in the art, and can sets according to actual needs, does not repeat them here.
202, also use successively each power weighted value in the first power weighted value set to be sent to receiving terminal and to obtain statistical information from transmitting terminal with reference to signal by high speed data bus.
Wherein, the power weighted value can be used for the weight of the power of sign high speed data bus transmission of reference signals high fdrequency component, the first power weighted value set can comprise at least one power weighted value, the quantity of high speed data bus is at least two, namely can test at least two high speed data buss simultaneously.
As an embodiment of the present embodiment, the first power weighted value set can set in advance, each power weighted value that the first power weighted value set comprises also can arrange according to preset order, so that the control module of debugged apparatus can be used each power weighted value in the first power weighted value set successively according to preset order, arrange once, control and be sent to receiving terminal once with reference to signal from transmitting terminal by high speed data bus.
203, obtain error rate not higher than the second power weighted value set of presetting error rate from the first power weighted value set according to the statistical information of obtaining.
Under test mode, if the power weighted value that arranges is improper, may cause receiving terminal to set up the retention time shorter, and then cause receiving terminal to receive wrong signal, the error rate of the signal that therefore, can receive by receiving terminal judges whether the power weighted value of Set For Current is suitable.
Concrete, the power weighted value of high speed data bus transmission of reference signals high fdrequency component is set to each power weighted value in the first power weighted value set successively, then, obtain statistical information corresponding to each power weighted value, statistical information can be used for characterizing by high speed data bus also uses the error rate of each power weighted value transmission of reference signals successively.
204, adjust the through-put power of high speed data bus signal transmission high fdrequency component according to the second power weighted value set.
Each power weighted value that the second power weighted value set comprises all can make the error rate of the signal that receiving terminal receives not higher than default error rate, therefore, can adjust according to the second power weighted value set the through-put power of high speed data bus signal transmission high fdrequency component, the weighted value of the through-put power of high fdrequency component that namely can signal is set to any power weighted value in the second power weighted value set, like this, make the error rate of the signal that receiving terminal receives in the actual transmissions process lower than default error rate.
In the present embodiment, while by generating reference signal, simulating the high speed data bus real work, the state of signal transmission is tested high speed data bus, namely can comprise: for high speed data bus signal transmission high fdrequency component arranges different power weighted values, and obtain statistical information corresponding to each power weighted value; The power weighted value of signal transmission high fdrequency component while then according to statistical information, determining the high speed data bus real work, definite power weighted value can make the error rate of the signal that receiving terminal receives lower than default error rate.Compare with the power weighted value of adjusting the signal high fdrequency component by the mode of high-speed oscilloscope test bus receiving terminal waveform and signal quality in prior art, the process that adopts this programme to debug high speed data bus is simple, and the state in conjunction with the high speed data bus actual transmission signal is tested, make debug results more accurate, in addition, it can test many high speed data buss simultaneously, saves the testing time, improves testing efficiency.This method can be applied to possess the network communication equipment of high speed data bus, and network communication equipment can comprise as debugged apparatus: control module, and respectively as the high-speed port of transmitting terminal and receiving terminal, ether port for example.Wherein, control module can be controlled generating reference signal, and controls and the power weighted value of high speed data bus signal transmission high fdrequency component to be set and from transmitting terminal, to send to receiving terminal, can control collection equipment and obtain statistical information.
The present embodiment provides the further optimization to method shown in Figure 2, after namely carrying out adjustment method shown in Figure 2, can delete the Partial Power weighted value in the first power weighted value set, carry out again method shown in Figure 2, in detail as shown in Figure 3, the method for the signal quality of the high speed data bus that provides of the present embodiment debugging specifically can comprise:
301, the default power weighted value of deletion from the first power weighted value set, Partial Power weighted value are to make the power weighted value of the error rate of the reference signal that receiving terminal receives higher than default error rate.
Before high speed data bus is tested, at first determine the first power weighted value set, then the power weighted value of high speed data bus signal transmission high fdrequency component being set gradually is each power weighted value in the first weighted value set.
In order to test high speed data bus faster, execute one take turns test after, the control module of debugged apparatus can be from the first power weighted value set deletion power weighted value, obtain the first power weighted value set, can reduce like this quantity of power weighted value to be tested.
Wherein, the Partial Power weighted value is to make the power weighted value of the error rate of the reference signal that receiving terminal receives higher than default error rate.
For example, all default power weighted values comprise any number in 0 to 15, when the power weighted value of having determined the high fdrequency component of high speed data bus is set in 12 to 15 any number, the error rate of the signal that receiving terminal receives is higher than default error rate, be that the Partial Power weighted value comprises 12 to 15, with 12 to 15 deletions, the first power weighted value set of determining can comprise any number in 0 to 11.
302, control generating reference signal.
The present embodiment is the control module generating reference signal at first of debugged apparatus, and the state of signal transmission while with reference to signal, by high speed data bus, transmitting to simulate the high speed data bus real work, to realize the test (, for easy description, can be described as in subsequent content under test mode) to the high-speed transfer bus.The present embodiment is mainly that test mode is described, namely under test mode, by high speed data bus is tested, determine the power weighted value of high speed data bus actual transmission signal high fdrequency component, then, under the actual transmissions state, high speed data bus uses the power weighted value of determining to carry out the transmission of signal, wherein, the power weighted value of determining makes the error rate of the signal that receiving terminal receives lower than default error rate.
303, the power weighted value of high speed data bus transmission of reference signals high fdrequency component being set gradually is each power weighted value in the first power weighted value set.
As an embodiment of the present embodiment, the first power weighted value set can set in advance, each power weighted value that the first power weighted value set comprises also can arrange according to preset order, in order to can use successively each power weighted value in the first power weighted value set to be sent to receiving terminal with reference to signal from transmitting terminal according to preset order.
For example, the first power weighted value set can comprise any number in 0 to 11 in order successively, it is any number in 0 to 11 that the power weighted value of high speed data bus signal transmission high fdrequency component is set gradually, namely at first the power weighted value of high speed data bus signal transmission high fdrequency component is set to 0 and carries out reference signal transmission, then be set to 1 and carry out reference signal transmission, then be set to 2 and carry out reference signal transmission, according to this order, be set to till 11 always.
Wherein, the power weighted value can be used for the weight of the power of sign high speed data bus transmission of reference signals high fdrequency component, and the first power weighted value set can comprise at least one power weighted value.
The present embodiment is not construed as limiting the order of the numerical value that comprises in the first power weight set, can set according to actual needs, can think random order, and for example, the first power weight set can comprise: 0,5,7,2,3 etc.
304, at the appointed time in section, by high speed data bus and use successively each power weighted value in the first power weighted value set to be sent to receiving terminal with reference to signal from transmitting terminal.
, as an embodiment of the present embodiment,, in order to save the transfer resource that consumes under test mode, can only pass through the high speed data bus transmission of reference signals in the Preset Time section.Concrete, can, at default initial time indication high speed data bus transmission reference information, in the default finish time, can indicate high speed data bus to stop transmission of reference signals.
The present embodiment is not construed as limiting the fixed time section, can set according to actual needs, does not repeat them here.
305, obtain statistical information at receiving terminal.
Wherein, statistical information can also be used the error rate of each power weighted value transmission of reference signals successively for characterizing by high speed data bus.
For example, can obtain by collection equipment the statistical information of power weighted value 0 to 11 correspondence, namely the power weighted value at high speed data bus is set to 0, then obtain statistical information after transferring to receiving terminal by high speed data bus with reference to signal, the power weighted value that can obtain again high speed data bus according to the method is followed successively by statistical information corresponding to any number in 1 to 11.
306, obtain error rate according to statistical information not higher than the second power weighted value set of presetting error rate from the first power weighted value set.
Under test mode, if the power weighted value that arranges is improper, may cause receiving terminal to set up the retention time shorter, and then cause receiving terminal to receive wrong data, the error rate of the data that therefore, can receive by receiving terminal judges whether the power weighted value of high fdrequency component of Set For Current is suitable.
Concrete, the power weighted value of high speed data bus transmission of reference signals high fdrequency component is set to each power weighted value in the first power weighted value set successively, then, obtains statistical information corresponding to each power weighted value.
Further, default error rate can be 0.
For example, after the power weighted value of high speed data bus was set to 10,11, the error rate of the reference signal that receiving terminal receives was higher than default error rate, and the second power weighted value set can comprise any number in 0 to 9.
307, adjust the through-put power of high speed data bus signal transmission high fdrequency component according to the second power weighted value set.
The power weighted value that the second power weighted value set comprises can make the error rate of the signal that receiving terminal receives not higher than default error rate, therefore, can adjust according to the second power weighted value set the through-put power of high speed data bus signal transmission high fdrequency component, namely can through-put power be set to any power weighted value in the second power weighted value set, like this, make the error rate of the signal that receiving terminal receives in the actual transmissions process lower than default error rate.
Due to, under the application scenarioss such as different STRESS VARIATION, different reference signals, the number range of the second power weighted value set may reduce or increase, therefore,, for definite power weighted value can be applied under different scenes, can be positioned at middle power weighted value with being set to numerical value in the second power weighted value set.
Further, specifically can comprise according to the through-put power of the second power weighted value set adjustment high speed data bus carry high frequency component:
Obtain numerical value and be positioned at middle power weighted value from the second power weighted value set; Through-put power is set to numerical value and is positioned at middle power corresponding to power weighted value.
For example, the second power weighted value set can comprise any number in 0 to 9, the power weighted value of signal transmission high fdrequency component in the time of can being set to the high speed data bus real work with 4 or 5.
Further, the quantity of high speed data bus is at least two.
In other words, the present embodiment can be tested at least two high speed data buss simultaneously, i.e. generating reference signal at first; Then, also use successively each power weighted value in corresponding the first power weighted value set to be sent to corresponding receiving terminal with reference to signal from transmitting terminal by at least two high speed data buss.Concrete, the testing procedure of each high speed data bus can, with reference to the content of step 301 to record in step 307, not repeat them here.
In the present embodiment, while utilizing the real work of reference signal simulation high speed data bus, the state of signal transmission is tested high speed data bus, namely can comprise: for high speed data bus signal transmission high fdrequency component arranges different power weighted values, and obtain statistical information corresponding to each power weighted value; The power weighted value of signal transmission high fdrequency component while then according to statistical information, determining the high speed data bus real work, definite power weighted value can make the error rate of the signal that receiving terminal receives lower than default error rate.Compare with the power weighted value of adjusting the signal high fdrequency component by the mode of high-speed oscilloscope test bus receiving terminal waveform and signal quality in prior art, the process that adopts this programme to debug high speed data bus is simple, and the state in conjunction with the high speed data bus actual transmission signal is tested, and makes debug results more accurate; In addition, it is concurrent testing that the present embodiment can also adopt said method simultaneously a plurality of high speed data buss to be tested, and the middle high-speed oscilloscope that adopts is tested a plurality of high speed data buss compared to existing technology, has reduced testing cost.
Some device embodiment below are provided, and this device embodiment is corresponding with the above-mentioned corresponding embodiment of the method that provides respectively.
The present embodiment provides a kind of device of signal quality debugging of high speed data bus, as shown in Figure 4, comprising:
Receiving terminal module 43, be used for the reference signal that the receiving end/sending end module sends by high speed data bus;
In the present embodiment, when the reference signal of utilizing control module to control generation is simulated the high speed data bus real work, the state of signal transmission is tested high speed data bus, namely can comprise: the power weighted value of different high fdrequency components is set for the high speed data bus signal transmission, and obtains statistical information corresponding to each power weighted value; The power weighted value of signal transmission high fdrequency component while then according to statistical information, determining the high speed data bus real work, definite power weighted value can make the error rate of the signal that receiving terminal receives lower than default error rate.Compare with the power weighted value of adjusting the signal high fdrequency component by the mode of high-speed oscilloscope test bus receiving terminal waveform and signal quality in prior art, the process that adopts this programme to debug high speed data bus is simple, and the state in conjunction with the high speed data bus actual transmission signal is tested, make debug results more accurate, in addition, it can test many high speed data buss simultaneously, saves the testing time, improves testing efficiency.
The present embodiment provides the device of the signal quality debugging of another kind of high speed data bus, and this device is to the further expanding of device shown in Figure 4, and as shown in Figure 5, can comprise:
Receiving terminal module 53, be used for the reference signal that the receiving end/sending end module sends by high speed data bus;
Further, control module 51 comprises:
The first setting unit 511, it is each power weighted value of the first power weighted value set that the power weighted value that is used for the reference signal high fdrequency component that initiator block is sent by high speed data bus sets gradually.
Acquiring unit 513, be used for obtaining numerical value from the second power weighted value set and be positioned at middle power weighted value;
The second setting unit 514, be set to numerical value for through-put power and be positioned at middle power corresponding to power weighted value.
In the present embodiment, while utilizing the real work of signal generating apparatus simulation high speed data bus, the state of signal transmission is tested high speed data bus, namely can comprise: the power weighted value of different high fdrequency components is set for the high speed data bus signal transmission, and obtains statistical information corresponding to each power weighted value; The power weighted value of signal transmission high fdrequency component while then according to statistical information, determining the high speed data bus real work, definite power weighted value can make the error rate of the signal that receiving terminal receives lower than default error rate.Compare with the power weighted value of adjusting the signal high fdrequency component by the mode of high-speed oscilloscope test bus receiving terminal waveform and signal quality in prior art, the process that adopts this programme to debug high speed data bus is simple, and the state in conjunction with the high speed data bus actual transmission signal is tested, and makes debug results more accurate; In addition, it is concurrent testing that the present embodiment can also adopt said method simultaneously a plurality of high speed data buss to be tested, and the middle high-speed oscilloscope that adopts is tested a plurality of high speed data buss compared to existing technology, has reduced testing cost.
Through the above description of the embodiments, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but in a lot of situation, the former is better execution mode.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium that can read, floppy disk as computer, hard disk or CD etc., comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. the method for the signal quality of high speed data bus debugging, is characterized in that, comprising:
Control generating reference signal and be input to transmitting terminal;
Also use successively each power weighted value in the first power weighted value set that described reference signal is sent to receiving terminal and obtains statistical information from transmitting terminal by high speed data bus, described power weighted value is used for characterizing described high speed data bus and transmits the weight of the power of described reference signal high fdrequency component, described the first power weighted value set comprises at least one power weighted value, and the quantity of described high speed data bus is at least two;
Obtain error rate according to described statistical information not higher than the second power weighted value set of default error rate from described the first power weighted value set, described statistical information is used for characterizing by described high speed data bus and uses successively described each power weighted value to transmit the error rate of described reference signal;
Adjust the through-put power of described high speed data bus signal transmission high fdrequency component according to described the second power weighted value set.
2. the method for the signal quality of high speed data bus according to claim 1 debugging, it is characterized in that, described by high speed data bus and use successively each power weighted value in the first power weighted value set that described reference signal is comprised from the method that transmitting terminal is sent to receiving terminal:
The power weighted value of described transmitting terminal by the described reference signal high fdrequency component of described high speed data bus transmission set gradually as each power weighted value in described the first power weighted value set, be sent to described receiving terminal after the power weight setting of described reference signal high fdrequency component is completed.
3. the method for the signal quality of high speed data bus according to claim 1 debugging, is characterized in that, described method also comprises:
The default power weighted value of deletion from described the first power weighted value set, described Partial Power weighted value are to make the power weighted value of the error rate of the described reference signal that described receiving terminal receives higher than described default error rate.
4. the method for the signal quality of high speed data bus according to claim 1 and 2 debugging, it is characterized in that, described by high speed data bus and use successively each power weighted value in the first power weighted value set with described reference signal from the method that transmitting terminal is sent to receiving terminal, to be:
At the appointed time in the section, also use successively each power weighted value in the first power weighted value set that described reference signal is sent to described receiving terminal from transmitting terminal by described high speed data bus, described fixed time section is to determine according to the regulated efficiency of the power weighted value of the required precision of described high speed data bus signal transmission and described high fdrequency component.
5. the method for the signal quality of high speed data bus according to claim 1 and 2 debugging, is characterized in that, the described through-put power of adjusting described high speed data bus signal transmission high fdrequency component according to described the second power weighted value set comprises:
Obtain numerical value and be positioned at middle power weighted value from described the second power weighted value set;
Described through-put power is set to described numerical value and is positioned at middle power corresponding to power weighted value.
6. the method for the signal quality of high speed data bus according to claim 5 debugging, is characterized in that, described control generating reference signal and the method that is input to transmitting terminal are:
Utilize the tester generated data to be input to transmitting terminal as the reference signal; Or,
Control is carried out the data that produce after broadcast storm and is input to transmitting terminal as the reference signal.
7. the device of the signal quality of high speed data bus debugging, is characterized in that, comprising:
Control module, be used for controlling generating reference signal, and the described reference signal that will generate is input to initiator block;
Initiator block, be used for receiving the described reference signal that described control module generates, also use successively each power weighted value in the first power weighted value set that described reference signal is sent to the receiving terminal module from transmitting terminal by high speed data bus, described power weighted value is used for characterizing described high speed data bus and transmits the weight of the power of described reference signal high fdrequency component, described the first power weighted value set comprises at least one power weighted value, and the quantity of described high speed data bus is at least two;
The receiving terminal module, be used for receiving the described reference signal that described initiator block sends by described high speed data bus;
Described control module, also be used for obtaining the statistical information of the described reference signal that described receiving terminal module receives, obtain error rate according to described statistical information not higher than the second power weighted value set of default error rate from described the first power weighted value set, described statistical information is used for characterizing by described high speed data bus and uses successively described each power weighted value to transmit the error rate of described reference signal; And for adjust the through-put power of described high speed data bus signal transmission high fdrequency component according to described the second power weighted value set.
8. the device of the signal quality of high speed data bus according to claim 7 debugging, is characterized in that, described control module comprises:
The first setting unit, the power weighted value that is used for the described reference signal high fdrequency component that described initiator block is sent by described high speed data bus sets gradually each power weighted value into described the first power weighted value set, is sent to described receiving terminal module after the power weight setting of described reference signal high fdrequency component is completed.
9. the device of the signal quality of according to claim 7 or 8 described high speed data buss debugging, is characterized in that, described control module also comprises:
Control unit, concrete being used at the appointed time in section, also use successively each power weighted value in the first power weighted value set that described reference signal is sent to described receiving terminal module from described initiator block by described high speed data bus, described fixed time section is to determine according to the regulated efficiency of the power weighted value of the required precision of described high speed data bus signal transmission and described high fdrequency component.
10. the device of the signal quality of according to claim 7 or 8 described high speed data buss debugging, is characterized in that, described control module comprises:
Acquiring unit, be used for obtaining numerical value from described the second power weighted value set and be positioned at middle power weighted value;
The second setting unit, be set to described numerical value for described through-put power and be positioned at middle power corresponding to power weighted value.
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| CN114424144A (en) * | 2019-09-26 | 2022-04-29 | 苹果公司 | Adaptive on-chip digital power estimator |
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