CN110149059B - Design method for low stray inductance loop of high-frequency inverter - Google Patents

Design method for low stray inductance loop of high-frequency inverter Download PDF

Info

Publication number
CN110149059B
CN110149059B CN201910390769.1A CN201910390769A CN110149059B CN 110149059 B CN110149059 B CN 110149059B CN 201910390769 A CN201910390769 A CN 201910390769A CN 110149059 B CN110149059 B CN 110149059B
Authority
CN
China
Prior art keywords
inductance
busbar
loop
main busbar
capacitor module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910390769.1A
Other languages
Chinese (zh)
Other versions
CN110149059A (en
Inventor
刁利军
刘博�
李伟杰
顾诚博
刁利坚
梅伟耀
张艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Tongli Zhida Technology Co ltd
Beijing Jiaotong University
Original Assignee
Beijing Tongli Zhida Technology Co ltd
Beijing Jiaotong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Tongli Zhida Technology Co ltd, Beijing Jiaotong University filed Critical Beijing Tongli Zhida Technology Co ltd
Priority to CN201910390769.1A priority Critical patent/CN110149059B/en
Publication of CN110149059A publication Critical patent/CN110149059A/en
Application granted granted Critical
Publication of CN110149059B publication Critical patent/CN110149059B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Inverter Devices (AREA)

Abstract

The invention belongs to the technical field of high-frequency inverters, and particularly relates to a design method of a low stray inductance loop of a high-frequency inverter. The main busbar of the commutation loop adopts a laminated structure, the main busbar comprises two layers of copper bars, namely a positive copper bar and a negative copper bar, and the width, the length and the thickness of the positive copper bar and the negative copper bar are the same; determining the size specification of the main busbar under the expected value of the inductance according to the influence of the width and the length of the copper bars in the main busbar row and the distance between two layers of copper bars on the impurity dispersion inductance of the main busbar row; the absorption capacitor module is arranged on the main bus and used for inhibiting a voltage peak caused by bus inductance and reducing loop equivalent inductance; the absorption capacitor module comprises a plurality of small capacitors which are arranged in parallel, and the capacitance value of the small capacitors in the absorption capacitor module is determined through an equivalent circuit of the double-pulse test circuit; and based on Q3D and simlorer joint simulation, the power loop which meets the final inductance expected value is obtained by changing the number of small capacitors in the absorption capacitor module or changing the size specification of the main busbar.

Description

Design method for low stray inductance loop of high-frequency inverter
Technical Field
The invention belongs to the technical field of high-frequency inverters, and particularly relates to a design method of a low-stray inductance loop of a high-frequency inverter.
Background
Inverters are widely used in many fields such as communication, traffic, and electric power, and are being developed in a direction of high frequency, high efficiency, and small volume. As the requirements for size and efficiency of inverters increase, their operating frequency must be increased continuously. Faster switching speeds result in switching devices that are more sensitive to stray inductance, which can easily cause serious problems in the switching process, such as voltage stress, electromagnetic interference and additional power losses. Therefore, the requirement of the high-frequency inverter on the loop stray parameters is more severe, and particularly in a high-power inverter, in order to eliminate the problem of voltage overshoot caused by stray inductance, the stray parameters of the main loop must be optimized as much as possible.
In the prior art, laminated busbars are designed, and absorption capacitors are also provided, so that the problems that a systematic busbar design principle and absorption capacitor selection and layout principle do not exist are solved. In a high-frequency inverter, the switching speed is high, the current change rate is large, and voltage overshoot is generated under the action of the current change rate and loop inductance, so that the normal use of a power device is influenced.
Therefore, at present, the high-frequency inverter busbar is not designed systematically with low inductance, and a large voltage overshoot is generated for the switch tube, which is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
Aiming at the technical problem, the invention provides a design method of a low stray inductance loop of a high-frequency inverter, wherein a main busbar of a commutation loop adopts a laminated structure, and stray inductance of the main busbar is reduced by utilizing a coupling principle of mirror current; in addition, the absorption capacitor module is arranged on the main bus bar, and the voltage overshoot and the electromagnetic interference at two ends of the switch tube can be effectively inhibited under the condition of double tubes.
The invention is realized by the following technical scheme:
a method of high frequency inverter low stray inductance loop design, the method comprising:
the main busbar of the commutation loop adopts a laminated structure so as to reduce the stray inductance of the main busbar by utilizing the coupling principle of the mirror current; the main busbar comprises two layers of copper bars, namely a positive copper bar and a negative copper bar, and the width, the length and the thickness of the positive copper bar and the negative copper bar are the same; determining the size specification of the main busbar under an inductance expected value according to the influence of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars on the inductance of the main busbar;
the absorption capacitor module is arranged on the main bus and used for inhibiting a voltage peak caused by bus inductance and reducing loop equivalent inductance; the absorption capacitor module comprises a plurality of small capacitors arranged in parallel, and the capacitance value of the small capacitors in the absorption capacitor module is determined through an equivalent circuit of the double-pulse test circuit;
and based on the Q3D and simlorer joint simulation, a power loop which meets the final inductance expected value is obtained by changing the number of small capacitors in the absorption capacitor module or by changing the size specification of the main busbar.
Further, the size specification of the main busbar under the inductance expected value is determined according to the influence of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars on the stray inductance of the main busbar, and specifically comprises the following steps:
(1) obtaining a calculation formula of the stray inductance of the busbar through the Bio Saval law and the ampere loop theorem:
Figure BDA0002056414280000021
in the formula, mu0Is a constant, mu0＝4π×10-7H/m, b is the width of the copper bars in the main busbar, l is the length of the copper bars in the main busbar, and D is the distance between two layers of copper bars in the main busbar; l isbbThe inductor is a laminated main bus, namely a bus stray inductor;
(2) drawing (b, D, L) by taking one of the width and the length of the copper bars in the main busbar and the distance between two copper bars as a limiting condition according to the actual layoutbb)、(D,l,Lbb) Or (b, L, L)bb) A graph;
(3) in the (b, D, L)bb)、(D,l,Lbb) Or (b, L, L)bb) Drawing an inductance contour line in the curve chart, obtaining a relational expression of inductance and (b, D), (D, l) or (b, l), and determining the size specification of the main busbar under the expected value of the inductance;
(4) and (3) performing finite element simulation through Q3D, extracting the busbar inductance, finishing the design if the requirement is met, and if the requirement is not met, entering the step (2) to adjust the limiting conditions and redesigning.
Further, the determining, by an equivalent circuit of the double-pulse test circuit, a capacitance value of a small capacitor in the absorption capacitor module specifically includes:
in the equivalent circuit of the double-pulse test circuit, the stray inductance L of the busbarbbComprising Lbb1And Lbb2Two moieties, Lbb＝Lbb1+Lbb2；
After the SiC MOSFET switch power device is switched off, the busbar stray inductance LbbGenerates resonance with the absorption capacitor module, LbbThe energy stored in the energy storage device is transferred to the absorption capacitor module;
energy E released by busbar stray inductanceLComprises the following steps:
Figure BDA0002056414280000031
in the formula IoffTransient current at the turn-off time of the switching device;
according to a capacitor energy storage formula, the total energy stored by all capacitors in the absorption capacitor module is obtained as follows:
Figure BDA0002056414280000041
the absorbed energy of the capacitor is more than or equal to the released energy of the inductor, and the capacitance capacity C of each small capacitor in the absorbed capacitance module is obtained1Satisfies the following conditions:
Figure BDA0002056414280000042
n is the number of all parallel small capacitors in the absorption capacitor module, IoffIs the transient current value, L, at the turn-off time of the switching power devicebbIs bus stray inductance value,. DELTA.U1The peak voltage value caused by the stray inductance of the busbar.
Further, based on Q3D and simlorer joint simulation, by changing the number of small capacitors in the absorption capacitor module or by changing the size specification of the main bus bar, a power loop meeting the final inductance expected value is obtained, specifically:
(1) establishing a simulation platform based on Q3D and simlorer combined simulation;
(2) measuring the circuit change rate di/dt and the voltage spike delta Uds in the loop;
(3) calculating the stray inductance of the loop: l isloop＝△Uds/(di/dt)；
(4) Judging whether the loop stray inductance meets the final inductance expected value or not; if the bus bar meets the design requirements, determining the design scheme of the bus bar; and if not, returning to the step (1) by changing the number of the small capacitors in the absorption capacitor module or changing the size specification of the main busbar until the loop stray inductance meets the final inductance expected value.
Further, the positive copper bars and the negative copper bars are placed in a laminated mode, and insulating materials are laid in the middle and on two sides of the two layers of the copper bars; the number of the small capacitors arranged in parallel in the absorption capacitor module is 3-6.
The invention has the beneficial technical effects that:
the loop inductance comprises a busbar inductance and other partial inductances, and the busbar design method can directly reduce the busbar stray inductance Lbb and can control the busbar inductance to be less than 20 nH; in addition, an absorption capacitor module is arranged on the main busbar, the absorption capacitor inhibits voltage peaks caused by busbar inductance Lbb and source inductance LS, the loop equivalent inductance Lloop is reduced, the absorption capacitor reduces parasitic inductance Lsnub of the absorption capacitor in parallel, and voltage overshoot and electromagnetic interference at two ends of the switching tube can be effectively inhibited under the condition of double tubes.
Drawings
FIG. 1 is a main busbar with a laminated structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a busbar structure after the optimized design in the embodiment of the invention;
fig. 3 is a flowchart illustrating a process of determining a size specification of a main busbar under an expected inductance value according to an embodiment of the present invention;
FIG. 4 shows the width and length (b, L, L) of the copper bars in the main bus-bar and the inductor in the embodiment of the present inventionbb) A graph;
FIG. 5 shows the width of the inductor and the copper bars in the main bus bar and the distance (b, D, L) between two copper bars in the embodiment of the present inventionbb) A graph;
FIG. 6 shows the length of the inductor and the copper bars in the main bus bar and the distance (D, L, L) between two copper bars in the embodiment of the present inventionbb) A graph;
fig. 7 is a schematic view of a main busbar lamination structure according to an embodiment of the invention;
FIG. 8 is a diagram of a built-up double pulse test circuit according to an embodiment of the present invention;
FIG. 9 is an equivalent circuit diagram of a double pulse test circuit according to an embodiment of the present invention;
fig. 10 is a flow chart of the busbar for obtaining the expected value of the final inductance based on the Q3D and simlorer joint simulation in the embodiment of the present invention;
FIG. 11 is a block diagram of a test system in an embodiment of the invention;
reference numerals: 1. a first vertical portion; 2. a horizontal portion; 3. a second vertical portion; 4. a small capacitance; 5. a switching power device interface; 6. a first set of capacitive interfaces; 7. a second set of capacitive interfaces; bus bar supported capacitive interface.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
The invention provides an embodiment of a design method of a low stray inductance loop of a high-frequency inverter, which comprises the following steps:
the main busbar of the commutation loop adopts a laminated structure so as to reduce the stray inductance of the main busbar by utilizing the coupling principle of the mirror current; the main busbar comprises two layers of copper bars, namely a positive copper bar and a negative copper bar, and the width, the length and the thickness of the positive copper bar and the negative copper bar are the same; determining the size specification of the main busbar under an inductance expected value according to the influence of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars on the inductance of the main busbar;
the absorption capacitor module is arranged on the main bus and used for inhibiting a voltage peak caused by bus inductance and reducing loop equivalent inductance; the absorption capacitor module comprises a plurality of small capacitors arranged in parallel, and the capacitance value of the small capacitors in the absorption capacitor module is determined through an equivalent circuit of the double-pulse test circuit;
and based on the Q3D and simlorer joint simulation, a power loop which meets the final inductance expected value is obtained by changing the number of small capacitors in the absorption capacitor module or by changing the size specification of the main busbar.
Preferably, in the embodiment of the present invention, as shown in fig. 1-2, the positive copper bar and the negative copper bar are stacked, and an insulating material is laid between and on both sides of the two copper bars; the two ends of the main bus bar are folded towards the same side to form a U-shaped double-layer folding structure, the U-shaped double-layer folding structure comprises a first vertical part, a horizontal part and a second vertical part which are sequentially connected, and the first vertical part is a direct current input end;
arranging a first group of capacitor interfaces on one side of the horizontal part close to the first vertical part, arranging a bus supporting capacitor interface at the upper end of the second vertical part, arranging a second group of capacitor interfaces at the lower end of the second vertical part, and arranging a switch device interface between the first group of capacitor interfaces and the second group of capacitor interfaces; the first group of capacitor interfaces and the second group of capacitor interfaces are connected to a plurality of small capacitors arranged in parallel in the absorption capacitor module.
In this embodiment, the determining, according to the influence of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars on the stray inductance of the main busbar, the size specification of the main busbar under the inductance expected value is specifically as shown in fig. 3:
(1) calculating through Bio Saval law and ampere loop theorem to obtain a calculation formula of the stray inductance of the busbar:
Figure BDA0002056414280000071
in the formula, mu0＝4π×10-7H/m, b is the width of the copper bars in the main busbar, l is the length of the copper bars in the main busbar, and D is the distance between two layers of copper bars in the main busbar; l isbbThe inductor is a laminated main bus, namely a bus stray inductor;
(2) drawing (b, D, L) by taking one of the width and the length of the copper bars in the main busbar and the distance between two copper bars as a limiting condition according to the actual layoutbb)、(D,l,Lbb) Or (b, L, L)bb) Graphs, as shown in FIGS. 4-6;
(3) in the (b, D, L)bb)、(D,l,Lbb) Or (b, L, L)bb) Drawing an inductance contour line in the curve chart, obtaining a relational expression of inductance and (b, D), (D, l) or (b, l), and determining the size specification of the main busbar under the expected value of the inductance;
(4) and (3) performing finite element simulation through Q3D, extracting the busbar inductance, finishing the design if the requirement is met, and if the requirement is not met, entering the step (2) to adjust the limiting conditions and redesigning.
When the expected value of the given inductance is less than 20nH, the size specification of the main busbar is obtained to meet the following conditions, wherein l, b and D are calculated by taking a centimeter as a unit:
Figure BDA0002056414280000081
in the step (1), the determination process of the laminated busbar inductance calculation formula is as follows:
referring to fig. 7, the model of the main busbar is obtained by using biot savart law and ampere loop theorem:
Figure BDA0002056414280000082
Figure BDA0002056414280000083
wherein, I represents the current flowing through the busbar; x is the X axis of the coordinate system; b represents magnetic induction intensity; mu.s0Represents the vacuum permeability; r represents the distance from the current element to the coordinate origin;
wherein r is2＝(D/2)2+x2，μ0＝4π×10-7H/m；
Figure BDA0002056414280000091
ψoSpecifically, the magnetic flux represents the magnetic flux of the magnetic flux interlinking outside the busbar; s represents the area of the busbar;
when width b > >2D
Figure BDA0002056414280000092
Wherein h is the thickness of the copper bar in the main busbar; the thickness h of the busbar is very small, h < b, and b is more than l/3;
simplified analysis:
Figure BDA0002056414280000093
in this embodiment, the determining, by the equivalent circuit of the double-pulse test circuit, the capacitance value of the small capacitor in the absorption capacitor module specifically includes:
as shown in fig. 9, the bus bar stray inductance LbbComprising Lbb1And Lbb2Two moieties, Lbb＝Lbb1+Lbb2. Absorption capacitance is only to Lbb1Has effect so that the closer the absorption capacitor is to the power device Lbb2The smaller is, up to Lbb2→0，Lbb1→Lbb，Lbb1The larger the size, the smaller the impact caused by the inductance of the impurity dissipation of the mother board after absorption. Theoretically, the closer the switching device interface and the absorption capacitor interface are, the closer the absorption capacitor module is to the SiC MOSFET switching power device, the smaller the impact caused by the absorbed busbar stray inductance is, but in practical engineering, the distance between the two is limited by the overall layout, and the distance between the two can only be shortened as much as possible. In the embodiment of the present invention as shown in fig. 2, preferably, in order to reduce the impact caused by absorbing the stray inductance of the post-bus, the switching device interface is disposed between the two sets of absorption capacitor interfaces of the first set of capacitor interfaces and the second set of capacitor interfaces, which is the most effective way compared with other arrangements.
In addition, in this embodiment, the main bus bar only includes two copper bars, namely a positive copper bar and a negative copper bar, and can bear a large direct-current voltage; three layers of insulating materials are arranged in the middle and on two sides of the two layers of copper bars, so that the insulating capability is well improved, and the insulating resistance is more than 20M omega; the device can bear DC1000V with the DC voltage and the humidity of 95%.
In the equivalent circuit of the double-pulse test circuit, the stray inductance L of the busbarbbComprising Lbb1And Lbb2Two moieties, Lbb＝Lbb1+Lbb2；LDIs the stray inductance between the two switching power devices; when the SiC MOSFET switch power device is turned off, the voltage of the two ends of the SiC MOSFET switch power device is equal to the voltage of the absorption capacitor module; at the moment, the bus capacitor, the bus stray inductor and the absorption capacitor module form a series loop;
after the SiC MOSFET switch power device is switched off, the busbar stray inductance LbbGenerates resonance with the absorption capacitor module, LbbThe energy stored in the energy storage device is transferred to the absorption capacitor module;
energy E released by busbar stray inductanceLComprises the following steps:
Figure BDA0002056414280000101
in the formula IoffTo openSwitching off the transient current at the moment of switching off the device;
according to a capacitor energy storage formula, the total energy stored by all capacitors in the absorption capacitor module is obtained as follows:
Figure BDA0002056414280000102
the absorbed energy of the capacitor is more than or equal to the released energy of the inductor, and the capacitance capacity C of each small capacitor in the absorbed capacitance module is obtained1Satisfies the following conditions:
Figure BDA0002056414280000103
n is the number of all parallel small capacitors in the absorption capacitor module, IoffIs the transient current value, L, at the turn-off time of the switching power devicebbIs bus stray inductance value,. DELTA.U1A peak voltage value caused by stray inductance of the busbar, wherein, the value of delta U1＝Lbb(di/dt), by measuring the rate of change of current di/dt, Δ U can be calculated1。
The stray inductance of the busbar can be completely inhibited after the capacitance value reaches a certain value, but the capacitance itself has parasitic inductance, the inductance is smaller in parallel, the stray inductance brought by the absorption capacitance is reduced as much as possible by adopting a plurality of small capacitors in parallel connection, but the small capacitors are excessive in quantity, so that excessive space is occupied, longer busbar is needed, the inhibiting effect is weakened, the stray inductance of a loop is increased even, and the quantity of the parallel absorption capacitance is not excessive. The technical personnel can select the quantity of the parallel absorption capacitors according to the design index requirements. Preferably, N is preferably 3 to 6 according to the results of multiple experiments.
In this embodiment, as shown in fig. 10, based on the Q3D and simlorer joint simulation, the size specification of the main busbar and the number of small capacitors in the absorption capacitor module are determined, and a busbar meeting the final inductance expected value is obtained, specifically:
(1) establishing a simulation platform based on Q3D and simlorer combined simulation;
(2) measuring the circuit change rate di/dt and the voltage spike delta Uds in the loop;
(3) calculating the stray inductance of the loop: l isloop＝△Uds/(di/dt)；
(4) Judging whether the loop stray inductance meets the final inductance expected value or not; if the bus bar meets the design requirements, determining the design scheme of the bus bar; and if not, returning to the step (1) by changing the number of the small capacitors in the absorption capacitor module or changing the size specification of the main busbar until the loop stray inductance meets the final inductance expected value.
In this embodiment, the maximum power density of the high-frequency inverter low-stray inductance busbar can reach 15.84W/cm3(ii) a According to withstand voltage test experimental data, the high-frequency inverter low-stray-inductance busbar can bear a voltage of at least DC 5000V.
In the embodiment, after the bus structure is determined after the optimization design, and the number and the capacitance value of the small capacitors in the absorption capacitor module are determined; the stray inductance of the busbar after the optimal design is determined to test whether the expected requirement is met, and the test method of the stray inductance of the busbar after the optimal design comprises the following steps:
(1) a double-pulse test circuit is built by adopting a tested busbar and comprises a direct-current power supply DC and a charge and discharge control relay S as shown in figure 81And S2And a discharge resistor RdBus capacitor CbusCapacitance C of direct current busbar and absorption capacitor modulesnubLoad inductance LloadAn upper tube silicon carbide Schottky freewheeling diode SBD, a lower tube silicon carbide MOSFET and a load inductor LloadThe upper tube silicon carbide Schottky freewheeling diode SBD is connected in parallel; l isbus，Ls， LsnubThe inductance is the bus capacitance inductance, the source inductance and the absorption capacitance parasitic inductance. When the double pulse test is performed, the bus capacitor C is closed S1busCharging and then disconnecting S1 and beginning the test. After the test is completed, S2 is closed, and the discharge can be rapidly performed. In the figure, Rd is connected with a bus capacitor and a direct current power supply in parallel; the absorption capacitor is connected with the switching device in parallel and then connected with the source electrode inductor and the bus capacitor in series.
Before the measurement begins, the charge and discharge control relay S is ensured1And S2Are all open;
closing switch S1Bus capacitor CbusMeasuring after charging is finished;
FIG. 8 is a block diagram of a test system employed in embodiments of the present invention, where RdWhen a double-pulse test is performed for discharging the resistor, firstly, the bus capacitor C is closed by the charging and discharging controller S1busCharging, then the test was started by the charge and discharge controller turning off S1. And controlling the pulse generator to send a pulse signal through the trigger controller, carrying out double-pulse test, displaying a measured waveform on the oscilloscope, reading measured data through the oscilloscope, transmitting the measured data to the control platform, and carrying out calculation. After the test is completed, S2 is closed, and the discharge can be rapidly performed.
In the prior art, the most common measurement method of stray inductance is mainly an indirect measurement method, but due to the existence of loop stray resistance, the measurement result of stray inductance is also affected by the interval selection difference. When the traditional indirect measurement method is used for measuring the stray inductance, the reading is complex, the measurement is not accurate, and high-bandwidth current measurement equipment is relied on, so that the measurement cost is high. The method for determining the stray inductance of the optimally designed busbar provided by the invention can test whether the busbar design method meets the expected requirements, and can effectively determine the stray inductance of the busbar by measuring the resonance period by using the resonance principle. The method has good suppression effect on voltage overshoot at two ends of the switching tube, and the test process is simpler and more accurate than that of the traditional integral method. The capacitance and the inductance value can be accurately obtained through a data manual, the stray inductance value can be determined only by reading the resonance period, and the measurement result is more accurate; the influence of different selection of the integral interval of the integral method on the extraction result of the stray inductance caused by the existence of the loop stray resistance is avoided; the voltage and the current do not need to be measured, and the measurement cost is reduced.
The method provided by the embodiment of the invention is applied to extracting an actual auxiliary inverter direct-current busStray inductance parameter, use 1200V/300A's carborundum MOSFET device, at direct current bus voltage 700V, carry out the dipulse experimental test under load current 300A's the operating mode, use the integral method to female row of this stromatolite to carry out the parameter and draw, according to the experimental result, the total stray inductance in return circuit is 21.4nH when not parallelly connected absorption capacitor module, and the total stray inductance in return circuit can be expressed as Lloop＝Lbb+LS+LD+Lsnub，Lbb＝Lbb1+Lbb2(ii) a Wherein L isbb1And Lbb2A total of 13nH, L for the DC bus to remove impurities and dissipate inductanceDIs the stray inductance between the two devices. The total stray inductance of the loop after the three small absorption capacitors of 0.47uF are connected in parallel is 12.4nH, and the total stray inductance of the loop after the six small absorption capacitors of 0.47uF are connected in parallel is reduced to 10.9 nH. By adopting the method in the embodiment, the bus bar design method directly reduces the bus bar inductance LbbThe absorption capacitor inhibits the bus inductance LbbAnd LSThe voltage peak caused by the voltage peak reduces the equivalent inductance L of the looploopAbsorption capacitance parallel connection reduces Lsnub。
If L is completely suppressed after parallel connection of absorption capacitorsbb1The desired value of the total stray inductance of the loop is 21.4-13 ═ 8.4nH, but Lbb2The parasitic inductance of the absorption capacitor can be introduced after the absorption capacitor is connected in parallel, so that the parasitic inductance is still more than 8.4nH after the absorption capacitor is added for suppression. In addition, there is an error between simulation and experiment, and when explaining the effect of the absorption capacitor, it is more appropriate to use 21.4nH of the total stray inductance of the loop before the absorption capacitor is not connected in parallel and 12.4nH and 10.9nH of the total stray inductance of the loop after three or six small absorption capacitors are connected in parallel under the same experiment condition.
It should be understood that the above-described embodiments are not intended to limit the scope of the invention, but rather to conform with the broadest scope consistent with the structures, principles and novel features disclosed herein.

Claims (4)

1. A method for designing a low stray inductance loop of a high-frequency inverter is characterized by comprising the following steps:
the main busbar of the commutation loop adopts a laminated structure so as to reduce the stray inductance of the main busbar by utilizing the coupling principle of the mirror current; the main busbar comprises two layers of copper bars, namely a positive copper bar and a negative copper bar, and the width, the length and the thickness of the positive copper bar and the negative copper bar are the same; determining the size specification of the main busbar under the expected value of the inductance according to the influence of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars on the inductance of the main busbar;
the absorption capacitor module is arranged on the main bus and used for inhibiting a voltage peak caused by bus inductance and reducing loop equivalent inductance; the absorption capacitor module comprises a plurality of small capacitors arranged in parallel, and the capacitance value of the small capacitors in the absorption capacitor module is determined through an equivalent circuit of the double-pulse test circuit;
based on Q3D and simlorer combined simulation, the power loop which accords with the final inductance expected value is obtained by changing the number of small capacitors in the absorption capacitor module or changing the size specification of the main busbar;
according to the influence of the width and the length of the copper bars in the main busbar row and the distance between two layers of copper bars on the impurity dispersion inductance of the main busbar row, the size specification of the main busbar under the inductance expected value is determined, and the method specifically comprises the following steps:
(1) obtaining a calculation formula of the stray inductance of the busbar through the Bio Saval law and the ampere loop theorem:
Figure FDA0002424877890000011
in the formula, mu0Is a constant, mu0＝4π×10-7H/m, b is the width of the copper bars in the main busbar, l is the length of the copper bars in the main busbar, and D is the distance between two layers of copper bars in the main busbar; l isbbThe inductor is a laminated main bus, namely a bus stray inductor;
(2) according to the actual layout, drawing (b, D, L) by taking one of the width and the length of the copper bars in the main busbar and the distance between two layers of copper bars as a limiting conditionbb)、(D,l,Lbb) Or (b, L, L)bb) A graph;
(3) in the (b, D, L)bb)、(D,l,Lbb) Or (b, l,Lbb) Drawing an inductance contour line in the curve chart, obtaining a relational expression of inductance and (b, D), (D, l) or (b, l), and determining the size specification of the main busbar under the expected value of the inductance;
(4) and (3) performing finite element simulation through Q3D, extracting the busbar inductance, finishing the design if the requirement is met, and if the requirement is not met, entering the step (2) to adjust the limiting conditions and redesigning.
2. The method for designing a low stray inductance loop of a high-frequency inverter according to claim 1, wherein the capacitance value of the small capacitor in the absorption capacitor module is determined by an equivalent circuit of a double-pulse test circuit, specifically:
in the equivalent circuit of the double-pulse test circuit, the stray inductance L of the busbarbbComprising Lbb1And Lbb2Two moieties, Lbb＝Lbb1+Lbb2；
After the SiC MOSFET switch power device is switched off, the busbar stray inductance LbbGenerates resonance with the absorption capacitor module, LbbThe energy stored in the energy storage device is transferred to the absorption capacitor module;
energy E released by busbar stray inductanceLComprises the following steps:
Figure FDA0002424877890000021
in the formula IoffTransient current at the turn-off time of the switching device;
according to a capacitor energy storage formula, the total energy stored by all capacitors in the absorption capacitor module is obtained as follows:
Figure FDA0002424877890000031
the absorbed energy of the capacitor is more than or equal to the released energy of the inductor, and the capacitance capacity C of each small capacitor in the absorbed capacitance module is obtained1Satisfies the following conditions:
Figure FDA0002424877890000032
n is the number of all parallel small capacitors in the absorption capacitor module, IoffFor the transient current value, L, at the turn-off time of the switching power devicebbStray inductance value of delta U for busbar1The peak voltage value caused by the stray inductance of the busbar.
3. The method for designing the low stray inductance loop of the high-frequency inverter according to claim 1, wherein a power loop meeting a final inductance expected value is obtained by changing the number of small capacitors in an absorption capacitor module or by changing the size specification of a main bus bar based on the Q3D and simlorer joint simulation, and specifically comprises the following steps:
(1) establishing a simulation platform based on Q3D and simlorer combined simulation;
(2) measuring the circuit change rate di/dt and the voltage spike delta Uds in the loop;
(3) calculating the stray inductance of the loop: l isloop＝ΔUds/(di/dt)；
(4) Judging whether the loop stray inductance meets the final inductance expected value or not; if the bus bar meets the design requirements, determining the design scheme of the bus bar; and if the inductance does not meet the expected inductance value, the step (1) is returned to until the stray inductance of the loop meets the expected inductance value finally by changing the number of small capacitors in the absorption capacitor module or changing the size specification of the main busbar.
4. The design method of the low stray inductance loop of the high-frequency inverter according to claim 1, wherein the positive copper bar and the negative copper bar are stacked, and insulating materials are laid between the two copper bars and on the two sides of the two copper bars; the number of the small capacitors arranged in parallel in the absorption capacitor module is 3-6.
CN201910390769.1A 2019-05-10 2019-05-10 Design method for low stray inductance loop of high-frequency inverter Active CN110149059B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910390769.1A CN110149059B (en) 2019-05-10 2019-05-10 Design method for low stray inductance loop of high-frequency inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910390769.1A CN110149059B (en) 2019-05-10 2019-05-10 Design method for low stray inductance loop of high-frequency inverter

Publications (2)

Publication Number Publication Date
CN110149059A CN110149059A (en) 2019-08-20
CN110149059B true CN110149059B (en) 2020-10-20

Family

ID=67595213

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910390769.1A Active CN110149059B (en) 2019-05-10 2019-05-10 Design method for low stray inductance loop of high-frequency inverter

Country Status (1)

Country Link
CN (1) CN110149059B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112636578B (en) * 2020-12-03 2022-06-21 佛山市顺德区美的电子科技有限公司 PFC circuit and noise reduction circuit
CN113380548B (en) * 2021-06-09 2022-07-08 上海临港电力电子研究有限公司 Capacitor parallel structure applied to power electronic device
CN113380547B (en) * 2021-06-09 2022-07-08 上海临港电力电子研究有限公司 Capacitor parallel structure applied to power electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102355122B (en) * 2011-09-30 2013-06-19 清华大学 Passive, nondestructive and non-contact integrated direct current busbar method based on transient power balancing
CN103116080B (en) * 2013-01-29 2014-12-24 上海电气集团股份有限公司 Circuit and method for measuring stray inductance of current conversion circuit of three-level converter
US20180122566A1 (en) * 2016-11-03 2018-05-03 Jiangsu Leader Electronics Inc. Transformer simulating circuit and simulating method of transformer

Also Published As

Publication number Publication date
CN110149059A (en) 2019-08-20

Similar Documents

Publication Publication Date Title
CN110149059B (en) Design method for low stray inductance loop of high-frequency inverter
BR112017008991B1 (en) Switching cell for a branch of a power converter, a plurality thereof, phase arm for a power converter, branch of a power converter with coupled phase arms, power converter for carrying a load and method for controlling the same
Roscoe et al. LV converters: Improving efficiency and EMI using Si MOSFET MMC and experimentally exploring slowed switching
CN109167518B (en) Vehicle-mounted power supply bidirectional DC-DC converter and control method thereof
Wen et al. Design and optimization of laminated busbar to reduce transient voltage spike
CN206698143U (en) A kind of T-shaped translation circuit and corresponding three-phase translation circuit and converting means
Waffler et al. Multi-objective optimization and comparative evaluation of Si soft-switched and SiC hard-switched automotive DC-DC converters
Wen et al. Analysis and minimisation of DC bus surge voltage for electric vehicle applications
Ren et al. Multi-commutation loop induced over-voltage issue on non-active switches in fast switching speed three-level active neutral point clamped phase leg
Zou et al. Study on DC busbar structure considering stray inductance for the back-to-back IGBT-based converter
Mermet-Guyennet et al. Electrical analysis and packaging solutions for high-current fast-switching SiC components
Wu et al. 3Φ4W grid-connected hybrid-frequency parallel inverter system with ripple compensation to achieve fast response and low current distortion
Karutz et al. Ultra compact three-phase PWM rectifier
Zhang et al. High power density medium-voltage megawatt-scale power converter for aviation hybrid-electric propulsion applications
Mazgaj et al. Soft-switching system with safe connections of capacitors and inductors in three-phase two-level voltage source inverter
Chen et al. Investigation of switching oscillations for silicon carbide MOSFETs in three-level active neutral-point-clamped inverters
Yu et al. Laminated busbar design and stray parameter analysis of three-level converter based on HVIGBT series connection
CN103780118A (en) Resonant DC link three-level soft switching inverter circuit
Rujas et al. Design and experimental validation of a silicon carbide 100kW battery charger operating at 60kHz
Yuan et al. The large-size low-stray-parameter planar bus bar for high power IGBT-based inverters
Li et al. Simulation-Assisted Design of a Power Stack for Improving Static Current Sharing Among Three IGBT Modules Connected in Parallel
Jin et al. Power loss and efficiency analysis of a four-level π-type converter
Wen et al. Design of a high-power power electronics building block based on SiC MOSFET modules
Fu et al. Influence of RCD snubber circuit on the commutation process of high-power three-level inverter with 4.5 kV IEGTs
Ming et al. An FPGA-based fault-tolerant method for reliable current commutation of direct matrix converter

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant