CN110149059A - A kind of high-frequency inverter low spurious inductor loop design method - Google Patents
A kind of high-frequency inverter low spurious inductor loop design method Download PDFInfo
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- CN110149059A CN110149059A CN201910390769.1A CN201910390769A CN110149059A CN 110149059 A CN110149059 A CN 110149059A CN 201910390769 A CN201910390769 A CN 201910390769A CN 110149059 A CN110149059 A CN 110149059A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
Abstract
The invention belongs to high-frequency inverter technical fields, and in particular to a kind of high-frequency inverter low spurious inductor loop design method.The main busbar of commutation circuit uses laminated construction, and the main busbar includes two layers of copper bar of positive copper bar and negative copper bar, and the width of positive copper bar and negative copper bar, length and thickness are identical；Influence according to the spacing of the width of copper bar, length and two layers of copper bar in the main busbar to main busbar stray inductance determines the dimensions of the main busbar under inductance desired value；Absorption Capacitance module is set on the main busbar, for inhibiting due to voltage spikes caused by busbar inductance, reduces circuit equivalent inductance；Absorption Capacitance module includes the small capacitances that several are arranged in parallel, and the capacitance of small capacitances in the Absorption Capacitance module is determined by the equivalent circuit that dipulse tests circuit；Based on Q3D and simplorer associative simulation, and by changing the quantity of small capacitances or the dimensions by changing main busbar in Absorption Capacitance module, the loop of power circuit for meeting final inductance desired value is obtained.
Description
Technical field
The invention belongs to high-frequency inverter technical fields, and in particular to a kind of high-frequency inverter low spurious inductor loop is set
Meter method.
Background technique
Inverter is widely used in the numerous areas such as communication, traffic and electric power, and towards high-frequency, efficiently
The direction of rate and small size is developed.Requirement with inverter to volume and efficiency improves, and working frequency must be mentioned constantly
It is high.Faster switching speed causes switching device more sensitive to stray inductance, is easy to bring serious ask in switching process
Topic, such as voltage stress, electromagnetic interference and additional power loss etc..Therefore requirement of the high-frequency inverter to loop stray parameter
It is harsher, especially in high-power inverter, in order to eliminate voltage-overshoot problem caused by stray inductance, it is necessary to as far as possible
Optimize the stray parameter of major loop.
The prior art is also also to have proposition Absorption Capacitance, problem is do not have systematic busbar by designing stack bus bar
Design principle and Absorption Capacitance selection and layout principles.In high-frequency inverter, switching speed is fast, and current changing rate is big, and electric current becomes
Rate and loop inductance effect can generate voltage overshoot, influence power device normal use.
Therefore, to the low sense design of high-frequency inverter busbar progress, system, switch tube do not cause voltage overshoot larger at present
It is those skilled in the art's urgent problem to be solved.
Summary of the invention
In view of the above technical problems, the present invention provides a kind of high-frequency inverter low spurious inductor loop design method, the change of current
The main busbar in circuit uses laminated construction, and the stray inductance of main busbar is reduced using the coupling principle of image current；In addition,
Absorption Capacitance module is set on main busbar, is worked along both lines, can effectively inhibit the voltage overshoot at switching tube both ends and electromagnetism dry
It disturbs.
The present invention is achieved by the following technical solutions:
A kind of high-frequency inverter low spurious inductor loop design method, which comprises
The main busbar of commutation circuit uses laminated construction, reduces the miscellaneous of main busbar with the coupling principle using image current
Dissipate inductance；The main busbar includes two layers of copper bar of positive copper bar and negative copper bar, width, length and the thickness of positive copper bar and negative copper bar
It is identical；Influence according to the spacing of the width of copper bar, length and two layers of copper bar in the main busbar to main busbar inductance, really
Determine the dimensions of the main busbar under inductance desired value；
Absorption Capacitance module is arranged on the main busbar to be reduced back for inhibiting due to voltage spikes caused by busbar inductance
Road equivalent inductance；The Absorption Capacitance module includes the small capacitances that several are arranged in parallel, by dipulse test circuit etc.
Effect circuit determines the capacitance of small capacitances in the Absorption Capacitance module；
Based on Q3D and simplorer associative simulation, and by changing the quantity of small capacitances in Absorption Capacitance module or leading to
The dimensions for changing main busbar is crossed, the loop of power circuit for meeting final inductance desired value is obtained.
Further, the spacing according to the width of copper bar, length and two layers of copper bar in the main busbar is to main mother
The influence for arranging stray inductance, determines the dimensions of the main busbar under inductance desired value, specifically:
(1) law is cut down by Biot's Sa and Ampère circuital theorem obtains busbar stray inductance calculation formula:
In formula, μ0For constant, μ0=4 π × 10-7H/m, b are the width of copper bar in main busbar, and l is copper bar in main busbar
Length, D are the spacing of two layers of copper bar in main busbar；LbbFor the inductance of the main busbar of lamination, i.e. busbar stray inductance；
(2) according to practical layout, by one in main busbar in the spacing of the width of copper bar, length and two layers of copper bar
As restrictive condition, (b, D, L are drawnbb)、(D,l,Lbb) or (b, l, Lbb) curve graph；
(3) in (b, D, the Lbb)、(D,l,Lbb) or (b, l, Lbb) inductance isopleth is drawn in curve graph, obtain electricity
The relational expression of sense and (b, D), (D, l) or (b, l), determines the dimensions of main busbar under inductance desired value；
(4) finite element simulation is done by Q3D, extracts busbar inductance and is such as unsatisfactory for if meeting the requirements i.e. complete design,
(2) adjustment restrictive condition is then entered step, design is re-started.
Further, the equivalent circuit for testing circuit by dipulse determines small electricity in the Absorption Capacitance module
The capacitance of appearance, specifically:
In the equivalent circuit of dipulse test circuit, busbar stray inductance LbbIncluding Lbb1And Lbb2Two parts, Lbb=
Lbb1+Lbb2；
After the shutdown of SiC switch mosfet power device, busbar stray inductance LbbResonance is generated with Absorption Capacitance module,
LbbThe energy of middle storage is shifted to Absorption Capacitance module；
The ENERGY E of busbar stray inductance releaseLAre as follows:
In formula, IoffMoment transient current is turned off for switching device；
According to capacitive energy storage formula, be absorbed all capacitor storage gross energies in capacitance module are as follows:
Capacitive absorption energy releases energy more than or equal to inductance, each in capacitance module that is absorbed small capacitances
Capacitance C1Meet:
N is the number of all small capacitances in parallel in Absorption Capacitance module, IoffMoment transient state is turned off for switching power devices
Current value, LbbFor busbar stray electrical inductance value, △ U1For peak voltage value caused by busbar stray inductance.
Further, it is based on Q3D and simplorer associative simulation, and by changing small capacitances in Absorption Capacitance module
Quantity or the dimensions by changing main busbar obtain the loop of power circuit for meeting final inductance desired value, specifically:
(1) it is based on Q3D and simplorer associative simulation, establishes emulation platform；
(2) circuit variation rate di/dt and due to voltage spikes △ Uds in circuit is measured；
(3) counter circuit stray inductance: Lloop=△ Uds/ (di/dt)；
(4) judge whether loop stray inductance meets final inductance desired value；If met, the design side of busbar is determined
Case；If do not met, by changing the quantity of small capacitances or the dimensions of the main busbar of change in Absorption Capacitance module, return
Step (1), until loop stray inductance meets final inductance desired value.
Further, the positive copper bar and the negative copper bar lamination are placed, and are laid in the centre of two layers copper bar and two sides
Insulating materials；The quantity for the small capacitances being arranged in parallel in the Absorption Capacitance module is 3-6.
Advantageous effects of the invention:
Loop inductance includes busbar inductance and other parts inductance, and busbar design method can be reduced directly in the present invention
Busbar stray inductance Lbb can control busbar inductance less than 20nH；In addition, Absorption Capacitance module is arranged on main busbar, inhale
It receives capacitor and inhibits due to voltage spikes caused by busbar inductance Lbb and source inductance LS, reduce circuit equivalent inductance Lloop, absorb electricity
Hold it is in parallel reduce Absorption Capacitance parasitic inductance Lsnub, work along both lines, can effectively inhibit switching tube both ends voltage overshoot and
Electromagnetic interference.
Detailed description of the invention
Fig. 1 is the main busbar in the embodiment of the present invention with laminated construction；
Fig. 2 is busbar structural schematic diagram after optimization design in the embodiment of the present invention；
Fig. 3 is the flow chart that the dimensions of the main busbar under inductance desired value is determined in the embodiment of the present invention；
Fig. 4 is width, length (b, l, the L of inductance and copper bar in main busbar in the embodiment of the present inventionbb) curve graph；
Fig. 5 is spacing (b, D, the L of the width of copper bar in inductance and main busbar in the embodiment of the present invention, two layers copper barbb) bent
Line chart；
Fig. 6 is spacing (D, l, the L of the length of copper bar in inductance and main busbar in the embodiment of the present invention, two layers copper barbb) bent
Line chart；
Fig. 7 is main busbar schematic diagram of laminated structure in the embodiment of the present invention；
Fig. 8 is that the dipulse built in the embodiment of the present invention tests circuit diagram；
Fig. 9 is the equivalent circuit diagram that dipulse tests circuit in the embodiment of the present invention；
Figure 10 is that Q3D and simplorer associative simulation is based in the embodiment of the present invention, and acquisition meets final inductance expectation
The busbar flow chart of value；
Figure 11 is test macro block diagram in the embodiment of the present invention；
Appended drawing reference: 1. first vertical portions；2. horizontal part；3. the second vertical portion；4. small capacitances；5. switching power devices
Interface；6. first group of capacitive interface；7. second group of capacitive interface；8. bus Support Capacitor interface.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments,
The present invention is explained in further detail.It should be appreciated that specific embodiment described herein is used only for explaining this hair
It is bright, it is not intended to limit the present invention.
On the contrary, the present invention covers any substitution done on the essence and scope of the present invention being defined by the claims, repairs
Change, equivalent method and scheme.Further, in order to make the public have a better understanding the present invention, below to of the invention thin
It is detailed to describe some specific detail sections in section description.Part without these details for a person skilled in the art
The present invention can also be understood completely in description.
The present invention provides a kind of high-frequency inverter low spurious inductor loop design method embodiment, which comprises
The main busbar of commutation circuit uses laminated construction, reduces the miscellaneous of main busbar with the coupling principle using image current
Dissipate inductance；The main busbar includes two layers of copper bar of positive copper bar and negative copper bar, width, length and the thickness of positive copper bar and negative copper bar
It is identical；Influence according to the spacing of the width of copper bar, length and two layers of copper bar in the main busbar to main busbar inductance, really
Determine the dimensions of the main busbar under inductance desired value；
Absorption Capacitance module is arranged on the main busbar to be reduced back for inhibiting due to voltage spikes caused by busbar inductance
Road equivalent inductance；The Absorption Capacitance module includes the small capacitances that several are arranged in parallel, by dipulse test circuit etc.
Effect circuit determines the capacitance of small capacitances in the Absorption Capacitance module；
Based on Q3D and simplorer associative simulation, and by changing the quantity of small capacitances in Absorption Capacitance module or leading to
The dimensions for changing main busbar is crossed, the loop of power circuit for meeting final inductance desired value is obtained.
Preferably, in embodiments of the present invention, as shown in Figs. 1-2, the positive copper bar and the negative copper bar lamination are placed,
Insulating materials is laid in the centre of two layers copper bar and two sides；The both ends of the main busbar are folded to the same side, are formed U-shaped
Double-layer folding structure, the U-shaped double-layer folding structure include that sequentially connected first vertical portion, horizontal part and second are vertical
Portion, first vertical portion are direct-flow input end；
First group of capacitive interface is set close to the side of first vertical portion in the horizontal part, it is perpendicular described second
Bus Support Capacitor interface is arranged in the upper end in straight portion, second group of capacitive interface is arranged in the lower end of second vertical portion, in institute
State setting switching device interface between first group of capacitive interface and second group of capacitive interface；First group of capacitive interface and institute
It states second group of capacitive interface and accesses the small capacitances that several in the Absorption Capacitance module are arranged in parallel.
In the present embodiment, the spacing pair according to the width of copper bar, length and two layers of copper bar in the main busbar
The influence of main busbar stray inductance determines the dimensions of the main busbar under inductance desired value, as shown in figure 3, specifically:
(1) law is cut down by Biot's Sa and Ampere circuit theorem obtains busbar stray inductance calculation formula:
In formula, μ0=4 π × 10-7H/m, b are the width of copper bar in main busbar, and l is the length of copper bar in main busbar, and D is
The spacing of two layers of copper bar in main busbar；LbbFor the inductance of the main busbar of lamination, i.e. busbar stray inductance；
(2) according to practical layout, by one in main busbar in the spacing of the width of copper bar, length and two layers of copper bar
As restrictive condition, (b, D, L are drawnbb)、(D,l,Lbb) or (b, l, Lbb) curve graph, as Figure 4-Figure 6；
(3) in (b, D, the Lbb)、(D,l,Lbb) or (b, l, Lbb) inductance isopleth is drawn in curve graph, obtain electricity
The relational expression of sense and (b, D), (D, l) or (b, l), determines the dimensions of main busbar under inductance desired value；
(4) finite element simulation is done by Q3D, extracts busbar inductance and is such as unsatisfactory for if meeting the requirements i.e. complete design,
(2) adjustment restrictive condition is then entered step, design is re-started.
When the inductance desired value given is less than 20nH, the dimensions for obtaining main busbar meets the following conditions, and following
L in part, b, D have been calculated centimetre for unit:
Wherein, in step (1), the determination process of stack bus bar inductance calculation formula are as follows:
Referring to Fig. 7, the model of main busbar cuts down law and Ampère circuital theorem by Biot's Sa:
In formula, I indicates that electric current flows through the electric current of busbar；X is coordinate system X-axis；B indicates magnetic induction intensity；μ0Indicate vacuum
Magnetic conductivity；R expression is calculated institute's obtaining current member to the distance of coordinate origin；
Wherein, r2=(D/2)2+x2, μ0=4 π × 10-7H/m；
ψoThe specific magnetic flux for indicating magnetic flux and interlinking outside busbar；S indicates busbar area；
As width b > > 2D
Wherein, h is the thickness of copper bar in main busbar；Busbar thickness h is very small, h<<b,and b>l/3；
Simplified analysis:
In the present embodiment, the equivalent circuit for testing circuit by dipulse determines in the Absorption Capacitance module
The capacitance of small capacitances, specifically:
As shown in figure 9, busbar stray inductance LbbIncluding Lbb1And Lbb2Two parts, Lbb=Lbb1+Lbb2.Absorption Capacitance is only right
Lbb1There is effect, so Absorption Capacitance is more close to power device Lbb2With regard to smaller, until Lbb2→ 0, Lbb1→Lbb, Lbb1It is bigger, it inhales
It is just smaller to receive stepmother's row's stray inductance bring impact.I.e. theoretically, switching device interface is closer with Absorption Capacitance interface, inhales
Capacitance module is received more close to SiC switch mosfet power device, absorption stepmother's row's stray inductance bring impact is just smaller,
But in practical projects, it is limited by integral layout, can only be to try to shorten distance between the two.As shown in Figure 2 in this hair
In bright embodiment, it is preferable that absorb stepmother's row's stray inductance bring impact to reduce, the switching device interface is set
It is placed between two groups of Absorption Capacitance interfaces of first group of capacitive interface and second group of capacitive interface, it, should compared with other set-up modes
Set-up mode effect is optimal.
Also, in the present embodiment, the main busbar only includes two layers of copper bar of positive copper bar and negative copper bar, be able to bear compared with
Big DC voltage；And three-layer insulated material is set in the centre of two layers copper bar and two sides altogether, improves insulation energy well
Power, insulation resistance > 20M Ω；The DC voltage DC1000V being able to bear, humidity 95%.
In the equivalent circuit of dipulse test circuit, busbar stray inductance LbbIncluding Lbb1And Lbb2Two parts, Lbb=
Lbb1+Lbb2；LDIt is the stray inductance between two switching power devices；When the shutdown of SiC switch mosfet power device,
SiC switch mosfet power device both end voltage is equal to Absorption Capacitance module end voltage；At this point, bus capacitor, busbar are spuious
Inductance and Absorption Capacitance module form series loop；
After the shutdown of SiC switch mosfet power device, busbar stray inductance LbbResonance is generated with Absorption Capacitance module,
LbbThe energy of middle storage is shifted to Absorption Capacitance module；
The ENERGY E of busbar stray inductance releaseLAre as follows:
In formula, IoffMoment transient current is turned off for switching device；
According to capacitive energy storage formula, be absorbed all capacitor storage gross energies in capacitance module are as follows:
Capacitive absorption energy releases energy more than or equal to inductance, each in capacitance module that is absorbed small capacitances
Capacitance C1Meet:
N is the number of all small capacitances in parallel in Absorption Capacitance module, IoffMoment transient state is turned off for switching power devices
Current value, LbbFor busbar stray electrical inductance value, △ U1For peak voltage value caused by busbar stray inductance, wherein △ U1=Lbb*
(di/dt), by measuring current changing rate di/dt, it can calculate and obtain △ U1。
Capacitor's capacity reaches the stray inductance that busbar can be completely inhibited after certain value, but capacitor per se with
Parasitic inductance, and the inductance the in parallel smaller, the purpose of taking multiple small capacitances parallel connections are to be reduced brought by Absorption Capacitance as far as possible
Stray inductance, but small capacitances quantity is excessive, can occupy excessive space, while needing longer busbar, can weaken inhibition effect
Fruit even results in loop stray inductance increase, so Absorption Capacitance quantity in parallel should not be excessive.Technical staff can be according to setting
Meter index request voluntarily selects Absorption Capacitance quantity in parallel.Preferably, N is according to many experiments result preferred 3-6.
In the present embodiment, as shown in Figure 10, it is based on Q3D and simplorer associative simulation, determines the size of main busbar
The quantity of small capacitances in specification and Absorption Capacitance module obtains the busbar for meeting final inductance desired value, specifically:
(1) it is based on Q3D and simplorer associative simulation, establishes emulation platform；
(2) circuit variation rate di/dt and due to voltage spikes △ Uds in circuit is measured；
(3) counter circuit stray inductance: Lloop=△ Uds/ (di/dt)；
(4) judge whether loop stray inductance meets final inductance desired value；If met, the design side of busbar is determined
Case；If do not met, by changing the quantity of small capacitances or the dimensions of the main busbar of change in Absorption Capacitance module, return
Step (1), until loop stray inductance meets final inductance desired value.
In the present embodiment, the power density highest of the busbar of the high-frequency inverter low spurious inductance can reach
15.84W/cm3；According to voltage-withstand test experimental data, the busbar of the high-frequency inverter low spurious inductance is able to bear voltage extremely
Few DC5000V.
In the present embodiment, busbar structure determination after optimization design, and in Absorption Capacitance module small capacitances number
And after capacitance determines；The stray inductance of busbar after optimization design is determined, to test whether to reach expected requirement, optimization
The test method of the stray inductance of busbar after design are as follows:
(1) dipulse test circuit is built using tested busbar, as shown in figure 8, dipulse test circuit includes straight
Galvanic electricity source DC, charge and discharge control relay S1And S2, discharge resistance Rd, bus capacitor Cbus, DC master row, Absorption Capacitance module
Capacitance Csnub, load inductance Lload, upper tube silicon carbide schottky freewheeling diode SBD, down tube silicon carbide MOSFET, load
Inductance LloadIt is in parallel with upper tube silicon carbide schottky freewheeling diode SBD；Lbus, Ls, Lsnub, respectively bus capacitor inductance, source
Pole inductance and Absorption Capacitance parasitic inductance.When carrying out dipulse test, closure S1 is by giving bus capacitor C firstbusCharging, then
S1 is disconnected, starts to be tested.After being completed, it is closed S2, can be discharged rapidly.In figure, Rd and bus capacitor and straight
Flow power sources in parallel；Absorption Capacitance and switching device are in parallel, then connect with source inductance, bus capacitor.
Before measurement starts, guarantee charge and discharge control relay S1And S2It is all to disconnect；
Closure switch S1, bus capacitor CbusIt is measured after charging complete；
Fig. 8 is the block diagram of test macro employed in the embodiment of the present invention, wherein RdFor discharge resistance, double arteries and veins are carried out
When punching test, S1 is closed by charging-discharging controller first and gives bus capacitor C by high-voltage DC power supplybusCharging, then passes through
Charging-discharging controller disconnects S1, starts to be tested.Impulse generator, which is controlled, by trigger controller sends pulse signal, into
The test of row dipulse, measured waveform read measurement data in oscilloscope display, by oscillograph, measurement data are sent to control
Platform processed, is calculated.After being completed, it is closed S2, can be discharged rapidly.
In the prior art, the most common predominantly indirect method of measurement of the measurement method of stray inductance, but due to loop stray
The presence of resistance, the difference that section is chosen can also affect the measurement result of stray inductance.Traditional indirect method of measurement measurement
Complicated, measurement is read when stray inductance inaccurately and relying on high bandwidth current measure device causes measurement cost higher.And this
Whether the method that the determination optimization design stepmother that invention the method provides arranges stray inductance, can test busbar design method
Reach expected requirement, using resonance principle, only need to measure harmonic period, can effectively determine the stray inductance of busbar.This method
The voltage overshoot at switch tube both ends has a better inhibition effect, and test process is easy compared with traditional quadrature method reading, also more
Accurately.Wherein, capacitor, inductance value all can accurately be obtained by databook, and need to only read to harmonic period can be true
Determine stray electrical inductance value, measurement result is more accurate；The presence for having avoided loop stray resistance causes integration method integrating range to be chosen not
It is influenced with the extraction result bring on stray inductance；It does not need to measure voltage and current, reduces measurement cost.
Method described in the embodiment of the present invention is applied to extract an actual subordinate inverter DC master row stray electrical
Parameter is felt, using the silicon carbide MOSFET device of 1200V/300A, in DC bus-bar voltage 700V, the work of load current 300A
Dipulse experiment test is carried out under condition, parameter extraction is carried out to the stack bus bar using integration method, according to experimental result, not
The total stray inductance in circuit is 21.4nH when Absorption Capacitance module in parallel, and the total stray inductance in circuit is represented by Lloop=Lbb+LS+
LD+Lsnub, Lbb=Lbb1+Lbb2；Wherein Lbb1And Lbb2For DC master row stray inductance, 13nH, L altogetherDIt is between two devices
Stray inductance.The total stray inductance in circuit is 12.4nH after three small Absorption Capacitances of 0.47uF in parallel, and six 0.47uF of parallel connection are small
The total stray inductance in circuit is reduced to 10.9nH after Absorption Capacitance.Using method described in the present embodiment, busbar design method is direct
Reduce busbar inductance Lbb, Absorption Capacitance inhibition busbar inductance LbbAnd LSCaused due to voltage spikes reduces circuit equivalent inductance Lloop,
Absorption Capacitance parallel connection reduces Lsnub。
If completely inhibiting L after Absorption Capacitance in parallelbb1, the ideal value of the total stray inductance in circuit is 21.4-13=
8.4nH, but Lbb2It is the failure to inhibition, the parasitic inductance of Absorption Capacitance itself in addition can be introduced after Absorption Capacitance in parallel,
So plus being still greater than 8.4nH after Absorption Capacitance inhibition.In addition, there are errors between emulation and experiment, illustrating Absorption Capacitance effect
When fruit, the total stray inductance 21.4nH in circuit and three, six in parallel before Absorption Capacitance not in parallel under same experiment condition are used
Total stray inductance 12.4nH, 10.9nH in circuit after a small Absorption Capacitance is more particularly suitable.
It should be noted that above-described embodiment, is not intended to limit the scope of protection of the present invention, and it is to fit to and this hair
Bright disclosed structure, principle and the consistent widest scope of features of novelty.
Claims (5)
1. a kind of high-frequency inverter low spurious inductor loop design method, which is characterized in that the described method includes:
The main busbar of commutation circuit uses laminated construction, and the stray electrical of main busbar is reduced with the coupling principle using image current
Sense；The main busbar includes two layers of copper bar of positive copper bar and negative copper bar, and the width of positive copper bar and negative copper bar, length and thickness are identical；
Influence according to the spacing of the width of copper bar, length and two layers of copper bar in the main busbar to main busbar inductance, determines inductance
The dimensions of main busbar under desired value；
Absorption Capacitance module is set on the main busbar, for inhibiting due to voltage spikes caused by busbar inductance, reduces circuit etc.
Imitate inductance；The Absorption Capacitance module includes the small capacitances that several are arranged in parallel, and the equivalent electricity of circuit is tested by dipulse
Road determines the capacitance of small capacitances in the Absorption Capacitance module；
Based on Q3D and simplorer associative simulation, and by changing the quantity of small capacitances in Absorption Capacitance module or passing through change
The dimensions of main busbar obtains the loop of power circuit for meeting final inductance desired value.
2. a kind of high-frequency inverter low spurious inductor loop design method according to claim 1, which is characterized in that described
Influence according to the spacing of the width of copper bar, length and two layers of copper bar in the main busbar to main busbar stray inductance determines electricity
Feel the dimensions of the main busbar under desired value, specifically:
(1) law is cut down by Biot's Sa and Ampère circuital theorem obtains busbar stray inductance calculation formula:
In formula, μ0For constant, μ0=4 π × 10-7H/m, b are the width of copper bar in main busbar, and l is the length of copper bar in main busbar, D
For the spacing of two layers of copper bar in main busbar；LbbFor the inductance of the main busbar of lamination, i.e. busbar stray inductance；
(2) according to practical layout, by one in main busbar in the spacing of the width of copper bar, length and two layers of copper bar as limit
Condition processed draws (b, D, Lbb)、(D,l,Lbb) or (b, l, Lbb) curve graph；
(3) in (b, D, the Lbb)、(D,l,Lbb) or (b, l, Lbb) inductance isopleth is drawn in curve graph, obtain inductance and
The relational expression of (b, D), (D, l) or (b, l) determine the dimensions of main busbar under inductance desired value；
(4) finite element simulation is done by Q3D, extracts busbar inductance and be such as unsatisfactory for if meeting the requirements i.e. complete design, then into
Enter step (2) adjustment restrictive condition, re-starts design.
3. a kind of high-frequency inverter low spurious inductor loop design method according to claim 1, which is characterized in that described logical
The equivalent circuit for crossing dipulse test circuit determines the capacitance of small capacitances in the Absorption Capacitance module, specifically:
In the equivalent circuit of dipulse test circuit, busbar stray inductance LbbIncluding Lbb1And Lbb2Two parts, Lbb=Lbb1+
Lbb2；
After the shutdown of SiC switch mosfet power device, busbar stray inductance LbbResonance, L are generated with Absorption Capacitance modulebbIn
The energy of storage is shifted to Absorption Capacitance module；
The ENERGY E of busbar stray inductance releaseLAre as follows:
In formula, IoffMoment transient current is turned off for switching device；
According to capacitive energy storage formula, be absorbed all capacitor storage gross energies in capacitance module are as follows:
Capacitive absorption energy releases energy more than or equal to inductance, the capacitor of each in capacitance module that is absorbed small capacitances
Capacity C1Meet:
N is the number of all small capacitances in parallel in Absorption Capacitance module, IoffMoment transient current is turned off for switching power devices
Value, LbbFor busbar stray electrical inductance value, △ U1For peak voltage value caused by busbar stray inductance.
4. a kind of high-frequency inverter low spurious inductor loop design method according to claim 1, which is characterized in that be based on
Q3D and simplorer associative simulation, and by the quantity of small capacitances in change Absorption Capacitance module or by changing main busbar
Dimensions obtains the loop of power circuit for meeting final inductance desired value, specifically:
(1) it is based on Q3D and simplorer associative simulation, establishes emulation platform；
(2) circuit variation rate di/dt and due to voltage spikes △ Uds in circuit is measured；
(3) counter circuit stray inductance: Lloop=△ Uds/ (di/dt)；
(4) judge whether loop stray inductance meets final inductance desired value；If met, the design scheme of busbar is determined；Such as
Fruit does not meet, by changing the quantity of small capacitances or the dimensions of the main busbar of change, return step in Absorption Capacitance module
(1), until loop stray inductance meets final inductance desired value.
5. a kind of high-frequency inverter low spurious inductor loop design method according to claim 1, which is characterized in that it is described just
Copper bar and the negative copper bar lamination are placed, and are laid with insulating materials in the centre of two layers copper bar and two sides；The Absorption Capacitance mould
The quantity for the small capacitances being arranged in parallel in block is 3-6.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112636578A (en) * | 2020-12-03 | 2021-04-09 | 佛山市顺德区美的电子科技有限公司 | PFC circuit and noise reduction circuit |
| CN113380548A (en) * | 2021-06-09 | 2021-09-10 | 上海临港电力电子研究有限公司 | Capacitor parallel structure applied to power electronic device |
| CN113380547A (en) * | 2021-06-09 | 2021-09-10 | 上海临港电力电子研究有限公司 | Capacitor parallel structure applied to power electronic device |
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| CN113380548A (en) * | 2021-06-09 | 2021-09-10 | 上海临港电力电子研究有限公司 | Capacitor parallel structure applied to power electronic device |
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