CN110148582A - The manufacturing method of contact hole - Google Patents
The manufacturing method of contact hole Download PDFInfo
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- CN110148582A CN110148582A CN201910297143.6A CN201910297143A CN110148582A CN 110148582 A CN110148582 A CN 110148582A CN 201910297143 A CN201910297143 A CN 201910297143A CN 110148582 A CN110148582 A CN 110148582A
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- Prior art keywords
- contact hole
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
The invention discloses a kind of manufacturing methods of contact hole, including rapid: providing the semiconductor substrate that surface is formed with first grid structure and level 0 interlayer film；Formation nitration case the first hard mask layers of composition are simultaneously graphical, and the first hard mask layers are covered on the region for not forming contact hole in spacer region；It forms first layer interlayer film and is planarized；Photoetching defines the forming region of contact hole and dummy contact hole simultaneously, remains with the first hard mask layers in the forming region in dummy contact hole；Perform etching the opening for being formed simultaneously contact hole and dummy contact hole；Form the outside that the opening of contact hole and dummy contact hole is filled up completely and is extended to opening by the first metal layer；It is planarized using metallochemistry mechanical milling tech.The present invention can prevent from generating butterfly defect after the metal CMP of contact hole and thereby can prevent metal residual in butterfly defect, so as to improve product yield.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacturing method of contact hole.
Background technique
In existing advanced logic chip technique, gate structure and source region and drain region require to draw by contact hole, grid
Spacing between structure is different, this meeting is so that the spacing between contact hole also can be different.It is needed during forming contact hole
It is initially formed the opening of contact hole, then fills metal layer in the opening, metallochemistry mechanical lapping is carried out to metal layer again later
(CMP) contact hole that the metal layer in opening forms is only filled with by 2 to be formed；But not due to the spacing between contact hole
Together, this meeting is so that the load of the metal CMP in each region is inconsistent, the amount of grinding meeting in the biggish region of spacing, to interlayer film
Increase, thus the butterfly defect with recess easy to form.This butterfly defect is along with the defects of other technical process
Superimposed effect, which is easy to cause, generates metal residual in butterfly fault location after the completion of the copper metal chemical mechanical grinding of last part technology,
This will cause copper wire short circuit, directly impact product yield.
It is the device junction composition in each step of manufacturing method of existing contact hole, existing contact as shown in Figure 1A to Figure 1B
The manufacturing method in hole includes the following steps:
Step 1: as shown in Figure 1A, providing semi-conductive substrate (not shown), being formed in the semiconductor substrate surface
Multiple first grid structures 101 and the interlayer film 105 being made of oxide layer, the interlayer film 105 are filled in each first grid
In spacer region between pole structure 101 and the top of the first grid structure 101 is extended to, the interlayer film 105 has flat
Smoothization surface.
The semiconductor substrate is silicon substrate.
The first grid structure 101 is formed by stacking by gate dielectric layer 102 and grid conducting material layer 103.
In general, the material of the gate dielectric layer 102 uses high dielectric constant material (HK).The grid conducting material layer
103 be metal gate (MG)；The first grid structure 101 is HKMG.HKMG is usually applied in 28nm or less process node.?
It can are as follows: the material of the gate dielectric layer 102 uses oxide layer, and the grid conducting material layer 103 is polysilicon gate.
In existing method, the interlayer film 105 includes level 0 interlayer film and first layer interlayer film, the level 0 interlayer
Film is filled in the spacer region between each first grid structure 101, the level 0 interlayer film and the first grid knot
The surface of structure 101 is equal, and the first layer interlayer film is covered on the first grid structure 101 and the level 0 interlayer film
On surface.
The first grid structure 101 uses dummy gate structure in forming process, and the dummy gate structure is by the grid
Dielectric layer 102 and dummy poly grid are formed by stacking.The level 0 interlayer film is formed between the adjacent dummy gate structure
The isolated area in, the level 0 interlayer film formation after, the dummy poly grid of the dummy gate structure are gone
It removes, filling metal forms the metal gate in dummy poly grid removal region；It is formed after forming the metal gate
The first layer interlayer film.
It is further comprised the steps of: before forming the level 0 interlayer film
Side wall 104 is formed in the side of the dummy gate structure.
Source region and drain region are formed in the two sides autoregistration of the dummy gate structure.
Step 2: as shown in Figure 1A, the forming region of contact hole 9 is gone out using lithographic definition.
Step 3: as shown in Figure 1A, performing etching the opening to form the contact hole 9.
Step 4: as shown in Figure 1A, forming the first metal layer 106a, the first metal layer 106a is by the contact hole 9
Opening be filled up completely and extend to the contact hole 9 opening outside.
In general, the body layer of the first metal layer 106a is tungsten layer；In the tungsten layer for forming the first metal layer 106a
Further include the steps that forming barrier layer before, the barrier layer is formed in the interior surface of the opening of the contact hole 9 and extension
To the outer surface of the opening of the contact hole 9.
The barrier layer is formed by stacking by titanium layer and titanium nitride layer.
Step 5: as shown in Figure 1B, being planarized using metallochemistry mechanical milling tech, the contact after planarization
The first metal layer 106a of the open outside in hole 9 is removed, and described in the opening by remaining in the contact hole 9
One metal layer 106a forms the contact hole 9.
As shown in Figure 1B it is found that since the interval between the contact hole 9 between two neighboring device cell is larger, this
Meeting is produced in spacer region so that the grinding load of the metallochemistry mechanical milling tech in each region namely corresponding grinding rate are different
The raw butterfly defect with sunk structure.This butterfly defect is easy to produce metal residual in the CMP of subsequent metal such as copper,
To influence whether the yield of product.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of contact hole, can prevent the gold in contact hole
Belong to CMP to generate butterfly defect later and thereby can prevent metal residual in butterfly defect, so as to improve product yield.
In order to solve the above technical problems, the manufacturing method of contact hole provided by the invention includes the following steps:
Step 1: provide semi-conductive substrate, the semiconductor substrate surface be formed with multiple first grid structures and
The level 0 interlayer film being made of oxide layer, the level 0 interlayer film are filled in the interval between each first grid structure
Qu Zhong, the surface of the level 0 interlayer film are equal with the surface of the first grid structure.
Step 2: the surface of the first grid structure and the level 0 interlayer film sequentially form the first oxide layer,
Second nitration case and third oxide layer, by second nitration case as the first hard mask layers.
Step 3: carrying out lithographic definition and successively the third oxide layer and second nitration case being performed etching and formed
The patterned structures of first hard mask layers；First hard mask layers after graphical are covered in the spacer region
And the region that first hard mask layers are covered is the region for not forming contact hole.
Step 4: form the first layer interlayer film being made of oxide layer and the first layer interlayer film is planarized,
The first layer interlayer film after planarization covers the outside of first hard mask layers and first hard mask layers
First oxide layer.
Step 5: going out the forming region of contact hole using lithographic definition and simultaneously defining the formation area in dummy contact hole
Domain remains with first hard mask layers in the forming region in the dummy contact hole.
It is formed simultaneously the opening of the contact hole and the opening in the dummy contact hole Step 6: performing etching, it is described to connect
The region that the opening of contact hole is passed through all is oxide layer, and the opening in the dummy contact hole can be across first hardmask
Layer, the etch rate of first hard mask layers is slower than the etch rate of oxide layer so that opening for the dummy contact hole
Mouth depth is shallower than the opening depth of the contact hole.
Step 7: forming the first metal layer, the first metal layer is by the opening of the contact hole and the dummy contact
The opening in hole is filled up completely and extends to the outside of the opening of the contact hole and the opening in the dummy contact hole.
Step 8: planarized using metallochemistry mechanical milling tech, after planarization the opening of the contact hole and
The first metal layer of the outside of the opening in the dummy contact hole is all removed, by remaining in the opening of the contact hole
The first metal layer form the contact hole, the first metal layer group as described in the opening for remaining in the dummy contact hole
At the dummy contact hole, the dummy contact hole setting so that in the planarization process each region grinding Load Balanced
Property improve, prevent in the spacer region generate butterfly defect.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the first grid structure is formed by stacking by gate dielectric layer and grid conducting material layer.
A further improvement is that the material of the gate dielectric layer uses oxide layer, the grid conducting material layer is polycrystalline
Si-gate.
A further improvement is that the material of the gate dielectric layer uses high dielectric constant material.
A further improvement is that the grid conducting material layer is metal gate.
A further improvement is that the first grid structure uses dummy gate structure, the dummy grid in forming process
Structure is formed by stacking by the gate dielectric layer and dummy poly grid.
The level 0 interlayer film is formed in the isolated area between the adjacent dummy gate structure, described
After zero layer interlayer film is formed, the dummy poly grid of the dummy gate structure are removed, and are removed in the dummy poly grid
Metal is filled in region forms the metal gate.
A further improvement is that being further comprised the steps of: before forming the level 0 interlayer film
Side wall is formed in the side of the dummy gate structure.
Source region and drain region are formed in the two sides autoregistration of the dummy gate structure.
Form the contact hole etching stop-layer being made of nitration case.
A further improvement is that the material of the side wall includes oxide layer or nitration case.
A further improvement is that being all respectively formed at the top of the source region, the drain region and the first grid structure
There is the corresponding contact hole.
A further improvement is that the material of the metal gate includes Al.
A further improvement is that first hard mask layers are removed after planarization in step 8.
A further improvement is that the body layer of the first metal layer described in step 7 is tungsten layer；Forming first gold medal
Further include the steps that forming barrier layer before belonging to the tungsten layer of layer, the barrier layer is formed in the opening and the void of the contact hole
The interior surface of the opening of quasi- contact hole and the outside for extending to the opening of the contact hole and the opening in the dummy contact hole
Surface.
A further improvement is that the barrier layer is formed by stacking by titanium layer and titanium nitride layer.
A further improvement is that the dummy contact hole retains or removes after planarizing in step 8.
The present invention is by increasing to be formed by the second nitration case after level 0 interlayer film and first grid structure are formed
The step of the first oxide layer and third oxide layer later before the first hard mask layers and the first hard mask layers of composition
Suddenly, the first hard mask layers are patterned later, re-form first layer interlayer film later and planarize first layer interlayer film；
The step of carrying out the definition of opening in dummy contact hole while the definition of the opening of contact hole again later, it is graphical after the
In the region that the opening that one hard mask layers are placed only in dummy contact hole is passed through, the first hard mask layers can make dummy contact
The etch rate of the open area in hole is slack-off, and it is more shallow to be formed simultaneously depth in the subsequent opening etching for carrying out contact hole in this way
Dummy contact hole opening；After filling the first metal layer in the opening in contact hole and dummy contact hole, to the first metal
Layer carries out in the planarization process using metallochemistry mechanical milling tech, and the grinding Load Balanced in each region of energy improves,
I.e. the present invention is provided with dummy contact hole in the spacing with biggish contact hole, that is, not formed contact hole spacer region, virtually
The load in each region can be made consistent after the setting of contact hole, so as to prevent from generating butterfly defect in spacer region, so this hair
It is bright to prevent from generating butterfly defect after the metal CMP of contact hole and thereby can prevent metal residual in butterfly defect, from
And product yield can be improved.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Figure 1B is the device junction composition in each step of manufacturing method of existing contact hole；
Fig. 2 is the flow chart of the manufacturing method of contact hole of the embodiment of the present invention；
Fig. 3 A- Fig. 3 J is the device junction composition in each step of manufacturing method of contact hole of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the flow chart of the manufacturing method of contact hole of the embodiment of the present invention；As shown in Fig. 3 A to Fig. 3 J, it is
Device junction composition in each step of the manufacturing method of contact hole of the embodiment of the present invention, the manufacturing method of contact hole of the embodiment of the present invention
Include the following steps:
Step 1: as shown in Figure 3A, providing semi-conductive substrate (not shown), being formed in the semiconductor substrate surface
Multiple first grid structures 1 and the level 0 interlayer film 61 being made of oxide layer, the level 0 interlayer film 61 are filled in each institute
It states in the spacer region between first grid structure 1, the table on the surface of the level 0 interlayer film 61 and the first grid structure 1
Face is equal.
The semiconductor substrate is silicon substrate.
The first grid structure 1 is formed by stacking by gate dielectric layer 2 and grid conducting material layer 3.
In present invention method, the material of the gate dielectric layer 2 uses high dielectric constant material.The Gate Electrode Conductive
Material layer 3 is metal gate；The material of the metal gate includes Al.The first grid structure 1 is HKMG.HKMG is usually applied to
In 28nm or less process node.Also can in other embodiments are as follows: the material of the gate dielectric layer 2 uses oxide layer, the grid
Pole conductive material layer 3 is polysilicon gate.
The first grid structure 1 uses dummy gate structure in forming process, and the dummy gate structure is situated between by the grid
Matter layer 2 and dummy poly grid are formed by stacking.The level 0 interlayer film 61 is formed between the adjacent dummy gate structure
In the isolated area, after the level 0 interlayer film 61 formation, the dummy poly grid of the dummy gate structure are gone
It removes, filling metal forms the metal gate in dummy poly grid removal region.
It is further comprised the steps of: before forming the level 0 interlayer film 61
Side wall 4 is formed in the side of the dummy gate structure.The material of the side wall includes oxide layer or nitration case.
Source region and drain region are formed in the two sides autoregistration of the dummy gate structure.
Form the contact hole etching stop-layer 5 being made of nitration case.It is also formed in the bottom of contact hole etching stop-layer 5
Oxide layer 5a.
Step 2: as shown in Figure 3B, in the surface of the first grid structure 1 and the level 0 interlayer film 61 successively shape
At the first oxide layer 62, the second nitration case 7 and third oxide layer 63, the first hard mask layers are used as by second nitration case 7
7。
Step 3: carrying out lithographic definition, the coating of photoresist 201 as shown in Figure 3B is carried out in photoetching process first；It connects
Be exposed and develop to form the graphic structure of photoresist 201 as shown in Figure 3 C.
It as shown in Figure 3D, is mask successively to the third oxide layer 63 and described using the figure of the photoresist 201
Nitride layer 7 performs etching the patterned structures to form first hard mask layers 7；First hard after graphical is covered
It is the area for not forming contact hole 9 that mold layer 7, which is covered on the region that in the spacer region and first hard mask layers 7 are covered,
Domain.
Step 4: as shown in FIGURE 3 E, forming the first layer interlayer film 64 being made of oxide layer.As illustrated in Figure 3 F, then to institute
It states first layer interlayer film 64 to be planarized, the first layer interlayer film 64 after planarization covers first hard mask layers
7 and first hard mask layers 7 outside first oxide layer 62.
Step 5: as shown in Figure 3 G, goes out the forming region of contact hole 9 using lithographic definition and define simultaneously and virtually connect
The forming region of contact hole 9a remains with first hard mask layers 7 in the forming region of the dummy contact hole 9a.
The second hard mask layers are additionally used in step 5, as shown in Figure 3 G, are initially formed by nitration case 202 and oxide layer
203 the second hard mask layers being formed by stacking, are coated photoresist 204 later, are exposed and develop to the photoetching later
Glue 204 is patterned.
Step 6: as shown in figure 3h, performing etching the opening 205a and the dummy contact for being formed simultaneously the contact hole 9
The opening 205b of hole 9a, the region that the opening 205a of the contact hole 9 is passed through all is oxide layer, the dummy contact hole 9a's
The 205b that is open can pass through first hard mask layers 7, and the etch rate of first hard mask layers 7 is slower than the quarter of oxide layer
Rate is lost so that the opening 205b depth of the dummy contact hole 9a is shallower than the opening 205a depth of the contact hole 9.
Step 7: as shown in fig. 31, the first metal layer 206 is formed, the first metal layer 206 is by the contact hole 9
The opening 205b of the opening 205a and dummy contact hole 9a is filled up completely and extends to opening 205a and the institute of the contact hole 9
State the outside of the opening 205b of dummy contact hole 9a.
In present invention method, the body layer of the first metal layer 206 is tungsten layer；Forming first metal
Further include the steps that being formed barrier layer before the tungsten layer of layer 206, the barrier layer be formed in the contact hole 9 opening 205a and
The interior surface of the opening 205b of the dummy contact hole 9a simultaneously extends to the opening 205a of the contact hole 9 and described virtually connects
The outer surface of the opening 205b of contact hole 9a.
The barrier layer is formed by stacking by titanium layer and titanium nitride layer.
Step 8: as shown in figure 3j, being planarized using metallochemistry mechanical milling tech, the contact after planarization
The first metal layer 206 of the outside of the opening 205b of the opening 205a and the dummy contact hole 9a in hole 9 is all removed, by
The first metal layer 206 remained in the opening 205a of the contact hole 9 forms the contact hole 9, described by remaining in
The first metal layer 206 described in the opening 205b of dummy contact hole 9a forms the dummy contact hole 9a, the dummy contact hole
9a setting so that in the planarization process each region grinding Load Balanced improve, prevent from generating in the spacer region
Butterfly defect.
First hard mask layers 7 are removed after planarization.
In Fig. 3 J, the dummy contact hole 9a retains after planarization.Also can in other embodiments are as follows: increase metallization
The amount of grinding for learning mechanical milling tech removes the dummy contact hole 9 after planarization.
As shown in Fig. 3 J it is found that at the source region of the grid conducting material layer 3 and two sides and the top in the drain region
All it is formed with the corresponding contact hole 9.There is biggish spacing between the spacer region, the two neighboring contact hole 9,
But by the setting of the dummy contact hole 9a, the pattern density in each region can be made uniform, to make described planarized
The grinding Load Balanced in each region improves in journey.
The embodiment of the present invention by after level 0 interlayer film 61 and first grid structure 1 are formed, increase to be formed by
The first oxide layer 62 before the first hard mask layers 7 and the first hard mask layers 7 of second nitration case 7 composition and later
The step of third oxide layer 63, is later patterned the first hard mask layers 7, re-forms first layer interlayer film 64 later simultaneously
Planarize first layer interlayer film 64；Carry out dummy contact hole 9a's while the definition of the opening 205a of contact hole 9 again later
Be open 205b definition the step of, it is graphical after the first hard mask layers 7 be placed only in the opening 205b of dummy contact hole 9a
In the region passed through, the first hard mask layers 7 can make the etch rate in the opening region 205b of dummy contact hole 9a slack-off, this
Sample can be formed simultaneously the opening of the more shallow dummy contact hole 9a of depth in the subsequent opening 205a etching for carrying out contact hole 9
205b；After filling the first metal layer 206 in the opening 205b of contact hole 9 and dummy contact hole 9a, to the first metal layer 206
It carrying out in the planarization process using metallochemistry mechanical milling tech, the grinding Load Balanced in each region of energy improves, namely
The embodiment of the present invention is provided with dummy contact in the spacing with biggish contact hole 9, that is, not formed contact hole 9 spacer region
Hole 9a can make the load in each region consistent after the setting of dummy contact hole 9a, so as to prevent the generation butterfly in spacer region to lack
It falls into, so the embodiment of the present invention can prevent from generating butterfly defect after the metal CMP of contact hole 9 and thereby metal can be prevented residual
It stays in butterfly defect, so as to improve product yield.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of contact hole, which comprises the steps of:
Step 1: providing semi-conductive substrate, multiple first grid structures are formed in the semiconductor substrate surface and by oxygen
Change the level 0 interlayer film of layer composition, the level 0 interlayer film is filled in the spacer region between each first grid structure
In, the surface of the level 0 interlayer film is equal with the surface of the first grid structure；
Step 2: sequentially forming the first oxide layer, second on the surface of the first grid structure and the level 0 interlayer film
Nitration case and third oxide layer, by second nitration case as the first hard mask layers；
Step 3: carrying out described in lithographic definition and successively performing etching to the third oxide layer and second nitration case to be formed
The patterned structures of first hard mask layers；First hard mask layers after graphical are covered in the spacer region and institute
Stating the region that the first hard mask layers are covered is the region for not forming contact hole；
Step 4: form the first layer interlayer film being made of oxide layer and the first layer interlayer film is planarized, it is flat
The first layer interlayer film after change covers the institute of the outside of first hard mask layers and first hard mask layers
State the first oxide layer；
Step 5: the forming region of contact hole is gone out using lithographic definition and simultaneously defines the forming region in dummy contact hole,
First hard mask layers are remained in the forming region in the dummy contact hole；
The opening of the contact hole and the opening in the dummy contact hole, the contact hole are formed simultaneously Step 6: performing etching
The region that is passed through of opening be all oxide layer, the opening in the dummy contact hole can be across first hard mask layers, institute
The etch rate for stating the first hard mask layers is slower than the etch rate of oxide layer so that the opening in the dummy contact hole is deep
Degree is shallower than the opening depth of the contact hole；
Step 7: forming the first metal layer, the first metal layer is open the contact hole and the dummy contact hole
Opening is filled up completely and extends to the outside of the opening of the contact hole and the opening in the dummy contact hole；
Step 8: planarized using metallochemistry mechanical milling tech, the opening of the contact hole and described after planarization
The first metal layer of the outside of the opening in dummy contact hole is all removed, the institute in opening by remaining in the contact hole
It states the first metal layer and forms the contact hole, form institute by remaining in the first metal layer described in the opening in the dummy contact hole
Dummy contact hole is stated, the dummy contact hole is arranged so that the grinding Load Balanced in each region mentions in the planarization process
Height prevents from generating butterfly defect in the spacer region.
2. the manufacturing method of contact hole as described in claim 1, it is characterised in that: the semiconductor substrate is silicon substrate.
3. the manufacturing method of contact hole as claimed in claim 2, it is characterised in that: the first grid structure is by gate dielectric layer
It is formed by stacking with grid conducting material layer.
4. the manufacturing method of contact hole as claimed in claim 3, it is characterised in that: the material of the gate dielectric layer is using oxidation
Layer, the grid conducting material layer are polysilicon gate.
5. the manufacturing method of contact hole as claimed in claim 3, it is characterised in that: the material of the gate dielectric layer uses Gao Jie
Permittivity material.
6. the manufacturing method of contact hole as claimed in claim 5, it is characterised in that: the grid conducting material layer is metal
Grid.
7. the manufacturing method of contact hole as claimed in claim 6, it is characterised in that: the first grid structure is in forming process
Middle to use dummy gate structure, the dummy gate structure is formed by stacking by the gate dielectric layer and dummy poly grid；
The level 0 interlayer film is formed in the isolated area between the adjacent dummy gate structure, in the level 0
After interlayer film is formed, the dummy poly grid of the dummy gate structure are removed, and remove region in the dummy poly grid
Middle filling metal forms the metal gate.
8. the manufacturing method of contact hole as claimed in claim 7, it is characterised in that: before forming the level 0 interlayer film
It further comprises the steps of:
Side wall is formed in the side of the dummy gate structure；
Source region and drain region are formed in the two sides autoregistration of the dummy gate structure；
Form the contact hole etching stop-layer being made of nitration case.
9. the manufacturing method of contact hole as claimed in claim 8, it is characterised in that: the material of the side wall include oxide layer or
Nitration case.
10. the manufacturing method of contact hole as claimed in claim 8, it is characterised in that: in the source region, the drain region and described
The top of first grid structure is all respectively formed with the corresponding contact hole.
11. the manufacturing method of contact hole as claimed in claim 6, it is characterised in that: the material of the metal gate includes Al.
12. the manufacturing method of contact hole as described in claim 1, it is characterised in that: in step 8, described first after planarization
Hard mask layers are removed.
13. the manufacturing method of contact hole as described in claim 1, it is characterised in that: the first metal layer described in step 7
Body layer is tungsten layer；Further include the steps that forming barrier layer, the barrier layer before the tungsten layer for forming the first metal layer
It is formed in the interior surface of the opening of the contact hole and the opening in the dummy contact hole and extends to opening for the contact hole
The outer surface of the opening in mouth and the dummy contact hole.
14. the manufacturing method of contact hole as claimed in claim 13, it is characterised in that: the barrier layer is by titanium layer and titanium nitride
Layer is formed by stacking.
15. the manufacturing method of contact hole as claimed in claim 13, it is characterised in that: the void after being planarized in step 8
Quasi- contact hole retains or removal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910297143.6A CN110148582A (en) | 2019-04-15 | 2019-04-15 | The manufacturing method of contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910297143.6A CN110148582A (en) | 2019-04-15 | 2019-04-15 | The manufacturing method of contact hole |
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