CN110148564A - A kind of DDD UHV MOS device structure and its manufacturing method - Google Patents
A kind of DDD UHV MOS device structure and its manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 62
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 77
- 239000000463 material Substances 0.000 description 19
- 239000002245 particle Substances 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910005889 NiSix Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
Abstract
The application provides a kind of DDD UHV MOS device structure and its manufacturing method, it could be formed with grid on substrate, shallow doped region is formed in the substrate of grid two sides, source-drain area can be formed in shallow doped region, source-drain area can form metal silicide layer, in this way when source-drain area is connect with the contact plug in peripheral circuit, while the breakdown voltage for ensuring UHV high, metal silicide layer can be formed with source-drain area and well be contacted, reduce the contact resistance between contact plug and source and drain, to reduce the overall power of device, device performance is improved.
Description
Technical field
This application involves semiconductor devices and its manufacturing field, in particular to a kind of DDD UHV MOS device structure and its
Manufacturing method.
Background technique
With the continuous development of semiconductor technology, MOS device gradually tends to high speed and high-performance, DDD UHV MOS (high pressure
Extra-high voltage metal-oxide semiconductor (MOS), Double Diffused Drain Ultra High Voltage are leaked in double diffusion
MOSFET) device is a kind of higher device of operating voltage, and operating voltage can be widely used in electricity in 10~40V or so
Road output interface, LCD driving circuit etc..DDD UHV MOS device is easy to be compatible with traditional cmos process, and technique is compared to LD
MOS (lateral diffusion metal oxide semiconductor, Lateral Diffused MOS) device is simpler, and manufacturing cost is also lower.
It can be connected with other devices in DDD UHV MOS device, to form high performance chip, specifically, can lead to
It crosses metal and semiconductor material contacts to form electrical connection.And in traditional DDD UHV MOS device based on WSI process technique
Contact resistance between metal and semiconductor material is usually larger, causes the power consumption of device larger.
Summary of the invention
In view of this, the application's is designed to provide a kind of DDD UHV MOS device structure and its manufacturing method, reduce
Contact resistance in superelevation voltage device, improves device performance.
To achieve the above object, the application has following technical solution:
The embodiment of the present application provides a kind of manufacturing method of DDD UHV MOS device structure, comprising:
Substrate is provided, grid is formed on the substrate, is formed with shallow doped region in the substrate of the grid two sides；
Source-drain area is formed in the shallow doped region；
Metal silicide layer is formed in the source-drain area.
It is optionally, described to form metal silicide layer in the source-drain area, comprising:
Form the mask layer of the exposure source-drain area；
It is masking with the mask layer, the metal silicide layer is formed in the source-drain area by silication technique for metal.
Optionally, source-drain area described in the mask layer expose portion.
Optionally, the grid be polysilicon or amorphous silicon, the method also includes:
Metal silicide layer is formed in the grid.
It is optionally, described to form metal silicide layer in the grid, comprising:
Form the mask layer of the exposure grid；
It is masking with the mask layer, the metal silicide layer is formed in the grid by silication technique for metal.
Optionally, grid described in the mask layer expose portion.
The embodiment of the present application provides a kind of DDD UHV MOS device structure, comprising:
Substrate；
Grid on the substrate；
Shallow doped region in the substrate of the grid two sides, the source-drain area in the shallow doped region；
The metal silicide layer of the source-drain area.
Optionally, source-drain area described in the metal silicide layer covering part.
Optionally, the grid is polysilicon or amorphous silicon, the device further include:
Metal silicide layer on the grid.
Optionally, grid described in the metal silicide layer covering part.
The embodiment of the present application provides a kind of DDD UHV MOS device structure and its manufacturing method, on substrate can be with shape
At there is grid, it is formed with shallow doped region in the substrate of grid two sides, source-drain area can be formed in shallow doped region, source-drain area can be with
Metal silicide layer is formed, in this way when source-drain area is connect with the contact plug in peripheral circuit, in the breakdown voltage for ensuring UHV high
While, metal silicide layer can be formed with source-drain area and well be contacted, the contact resistance between contact plug and source and drain is reduced, from
And the overall power of device is reduced, improve device performance.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the application
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
The process that Fig. 1 shows a kind of manufacturing method of DDD UHV MOS device structure provided by the embodiments of the present application is shown
It is intended to；
Fig. 2-7 is shown according to the structure in a kind of DDD UHV MOS device configuration process provided by the embodiments of the present application
Schematic diagram, wherein diagram a is the schematic top plan view of DDD UHV MOS device structure in the embodiment of the present application, and diagram b is diagram a
The sectional view along AA of middle device architecture；
Fig. 8 shows the performance schematic diagram of DDD UHV MOS device provided by the embodiments of the present application.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.
Many details are explained in the following description in order to fully understand the application, but the application can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to the application intension
In the case of do similar popularization, therefore the application is not limited by the specific embodiments disclosed below.
Secondly, the application combination schematic diagram is described in detail, when the embodiment of the present application is described in detail, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the range of the application protection.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, when DDD UHV MOS device is connect with other devices, can by metal and
Semiconductor material contact in DDD UHV MOS device can form contact plug, source and drain to form electrical connection, such as in source-drain area
It is the contact between semiconductor and metal between area and contact plug, and the contact resistance between metal and semiconductor material is usual
It is larger, cause the overall power of DDD UHV MOS device higher, device performance declines therewith.
Based on the above technical problem, the embodiment of the present application provides a kind of DDD UHV MOS device structure and its manufacturer
Method could be formed with grid on substrate, and shallow doped region is formed in the substrate of grid two sides, can be formed in shallow doped region
Source-drain area, source-drain area can form metal silicide layer, in this way when source-drain area is connect with the contact plug in peripheral circuit, true
While protecting the breakdown voltage of UHV high, metal silicide layer can be formed with source-drain area and well be contacted, and reduce contact plug and source and drain
Between contact resistance improve device performance to reduce the overall power of device.
In order to better understand the technical solution and technical effect of the application, below with reference to attached drawing to specific embodiment
It is described in detail.
Refering to what is shown in Fig. 1, being a kind of stream of the manufacturing method of DDD UHV MOS device structure provided by the embodiments of the present application
Cheng Tu, this method may comprise steps of:
S101 provides substrate 100, is formed with grid 112 on the substrate 100, in the substrate 100 of 112 two sides of grid
It is formed with shallow doped region 121, with reference to shown in Fig. 2,3,4 and 5.
In the embodiment of the present application, substrate 100 can be semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe
Substrate, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, semiconductor substrate can also be include that other elements semiconductor or compound are partly led
The substrate of body, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can also be other extensions
Structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, which can be silicon substrate.
Isolation structure (not shown go out) can be already formed in substrate 100, isolation structure may include silica
Or the material of other active areas that can separate device, isolation structure for example can be shallow trench isolation (STI, Shallow
Trench Isolation), the substrate area around isolation structure is active area, which can be trap doping
It can be adulterated without trap.
On the substrate 100 of active area, it is already formed with grid 112, is also formed with grid between grid 112 and substrate 100
Dielectric layer 111, refering to what is shown in Fig. 2, wherein Fig. 2 (a) is a kind of DDD UHV MOS provided by the embodiments of the present application in manufacturing process
In device architecture schematic top plan view, Fig. 2 (b) is diagrammatic cross-section of the device architecture on the direction AA in Fig. 2 (a).
In the embodiment of the present application, gate dielectric layer 111 for example can be thermal oxide layer or other suitable dielectric materials, such as
Silica or high K medium material, high K medium grid material such as hafnium base oxide, HFO2、HfSiO、HfSiON、HfTaO、HfTiO
Deng one of or in which several combinations.Grid 112 can be single or multi-layer structure, such as can be polysilicon, amorphous
Silicon or metal electrode material or their combination, metal electrode material can be a kind of or more for TiN, TiAl, Al, TaN, TaC, W
Kind combination.Can growth gate dielectric material and grid material after, be patterned, come formed gate dielectric layer 111 and its
On grid 112.Grid 112 after patterning can repair the defect on surface by oxidation technology.
After forming grid 112, shallow doped region 121, shallow doped region can be formed in the substrate 100 of 112 two sides of grid
121 can be used as the buffer area of device, refering to what is shown in Fig. 3, wherein, Fig. 3 (a) is a kind of DDD provided by the embodiments of the present application
The schematic top plan view of device architecture of the UHV MOS in manufacturing process, Fig. 3 (b) are the device architecture in Fig. 3 (a) in the direction AA
On diagrammatic cross-section.Formed shallow doped region 121 doping process can there are many, such as ion implanting, diffusion etc..Shallow doping
There can be the doping particle of N-type or p-type in area 121, the concentration for adulterating particle is lower, and the doping particle of n-type doping for example can be with
For N, P, As etc., the doping particle of p-type doping can be for example B, Al, Ga or In etc..
After forming shallow doped region 121, side wall 113 can be formed on the side wall of grid 112, side wall 113 can be folded
Layer structure, may include silica, silicon nitride, silicon oxynitride or their combination, in the embodiment of the present application, side wall 113 can
To include the lamination of the silica stacked gradually from inside to outside, silicon nitride.In the formation process of side wall 113, can successively it sink
Product silica and silicon nitride using anisotropic etching, such as can be RIE (reactive ion etching), vertically carry out
The etching of 113 material of side wall, until the surface of exposure substrate 100, in this way, except 112 side wall of 112 upper surface of grid and grid
Spacer material will all be removed, only the spacer material of 112 side wall of grid remains, thus, formed side wall 113, with reference to Fig. 4
Shown, Fig. 4 (a) is that a kind of vertical view of device architecture of the DDD UHV MOS provided by the embodiments of the present application in manufacturing process is shown
It is intended to, Fig. 4 (b) is diagrammatic cross-section of the device architecture on the direction AA in Fig. 4 (a).
S102 forms source-drain area 122 in shallow doped region 121, with reference to shown in Fig. 5.
Source-drain area 122 can be formed in shallow doped region 121, specifically, N-type can be injected according to the needs of type of device
Or the doping particle of p-type, the doping particle of source-drain area 122 is identical as the doping type of particle of shallow doped region 121, and source-drain area
122 doping particle concentration is greater than the doping particle concentration of shallow doped region 121.When the doping particle of shallow doped region 121 is N-type,
The doping particle of source-drain area 122 is N-type, and source-drain area 122 can be considered as the area N-type heavy doping (N plus, NP)；Shallow doped region 121
Doping particle when being p-type, the doping particle of source-drain area 122 is p-type, source-drain area 122 can be considered as p-type heavy doping (P plus,
PP) area.When it is implemented, can be by ion implantation doping particle, and annealing activation doping is carried out, to form source-drain area 122.
Refering to what is shown in Fig. 5, Fig. 5 (a) is a kind of device of the DDD UHV MOS provided by the embodiments of the present application in manufacturing process
The schematic top plan view of part structure, Fig. 5 (b) are diagrammatic cross-section of the device architecture on the direction AA in Fig. 5 (a).Wherein, flat
For row in the plane on 100 surface of substrate, source-drain area 122 can be located at the center of shallow doped region 121, and the area of source-drain area 122
It is significantly less than the area of shallow doped region 121, it, in this way can be to have one between source-drain area 122 and grid 112 with reference to shown in Fig. 5 (a)
Fixed distance, convenient for the normal work of DDD UHV MOS device under high pressure.The doping depth of source-drain area 122 can be less than shallow
The doping depth of doped region 121, with reference to shown in Fig. 5 (b).
S103 forms metal silicide layer 123 in source-drain area 122, with reference to Fig. 6 and 7.
After forming source-drain area 122, silication technique for metal can also be carried out, forms metal silicide on source-drain area 122
Layer 123 when grid 112 is polysilicon or amorphous silicon, can also form metal silicide layer 115, reference on grid 112 simultaneously
Shown in Fig. 7, Fig. 7 (a) is that the vertical view of device architecture of the DDD UHV MOS provided by the embodiments of the present application in manufacturing process is illustrated
Figure, Fig. 7 (b) are diagrammatic cross-section of the device architecture on the direction AA in Fig. 7 (a).
Metal silicide layer 115/123 can be formed by silication technique for metal, in silication technique for metal, generate metal
, can be by heat treatment process, so that react between metal and the semiconductor material being in contact with it after layer, and other are situated between
Material does not react with metal, to form metal silicide layer 115/123.
However, in the embodiment of the present application, source-drain area 122 only accounts for the area of shallow doped region 121, if directly passing through gold
Belong to silicification technics, then metal silicide layer will cover entire shallow doped region 121, and the electric conductivity of metal silicide layer compared to
The electric conductivity of shallow doped region is preferable, is easy to cause DDD UHV MOS device leakage current high.
Therefore, in the embodiment of the present application, before source-drain area 122 forms metal silicide layer 123, exposure mask can also be formed
Layer 114, refering to what is shown in Fig. 6, wherein, Fig. 6 (a) is device of the DDD UHV MOS provided by the embodiments of the present application in manufacturing process
The schematic top plan view of part structure, Fig. 6 (b) are diagrammatic cross-section of the device architecture on the direction AA in Fig. 6 (a).Mask layer 114
Source-drain area 122 can be exposed, certainly, if desired forms metal silicide layer 115 in grid 112, then the mask layer 114 can be with
Exposure grid 112.Specifically, can perform etching to obtain mask layer 114 to mask material with deposition of mask material.
In the specific implementation, the mask layer 114 of exposure source-drain area 122 is obtained by the deposition and etching of mask material
, if therefore it is not high to the etching alignment precision of mask material, mask layer 114 may the shallow doped region 121 of expose portion, in order to
So that the mask layer to be formed 114 is not exposed shallow doped region 121,114 expose portion source-drain areas 122 of mask layer can be enabled, even covering
The area of the source-drain area 122 of the exposure of film layer 114 is less than the gross area of 122 upper surface of source-drain area.Correspondingly, mask layer 114 can also
With only expose portion grid 112, even the area of the grid 112 of the exposure of mask layer 114 is less than total face of 112 upper surface of grid
Product.
After forming mask layer 114, it can be masking with mask layer, silication technique for metal be carried out, to form metallic silicon
Compound 115/123, with reference to shown in Fig. 7.Since the semiconductor material exposed only has source-drain area 122, or only source-drain area 122
With grid 112, then the metal silicide layer 123 formed only covers source-drain area 122, or the metal silicide layer 123 formed covers
Lid source-drain area 122, the metal silicide layer 115 being formed simultaneously cover grid 112.
In the embodiment of the present application, the material of metal for example can for Ni, Ti or Co etc., on exposed silicon by Ni,
After the silication technique for metal of Ti, Co etc., forming metal silicide layer is respectively NiSix、TiSix、CoSix.It is understood that
That metal layer and metal silicide layer herein is merely illustrative, can also for it is any other can be by metallic silicon can occur
Change the metal silicide layer that the metal material of reaction is formed, the application does not limit this particularly.
It is understood that in 114 expose portion source-drain areas 122 of mask layer, the metallic silicon that is formed on source-drain area 122
Also covering part source-drain area 122, that is, the area of the metal silicide layer 123 formed are less than table on source-drain area 122 to compound layer 123
The gross area in face；In 114 expose portion grids 112 of mask layer, the metal silicide layer 115 formed on grid 112 also only
Covering part grid 112, that is, the area of the metal silicide layer 115 formed are less than the gross area of 112 upper surface of grid.In this way may be used
To avoid the other positions of the covering of metal silicide layer 115/123 in the devices, therefore before the normal work for guaranteeing device
It puts, reduces contact resistance by increasing metal silicide layer 115/123, improve device performance.
Refering to what is shown in Fig. 8, for the performance schematic diagram of DDD HUV MOS device in the embodiment of the present application, including metal silication
Nitride layer from source-drain area under different relative positions, the relation curve of the electric current Id (unit: A) and voltage Vd (unit: V) of device,
Wherein, the curve that expression is completely covered is that the electric current of source-drain area and shallow doped region and the pass of voltage is completely covered in metal silicide layer
It is curve, the curve that 0um is indicated is the electric current and voltage in metal silicide region and device that source-drain area is completely coincident
Relation curve, the curve that 0.05um and 0.1um are indicated is respectively that the region where metal silicide is less than source-drain area, and metal
The relation curve of electric current and voltage in the device of the edge 0.05um and 0.1um of the Edge Distance source-drain area of silicide ,-
The curve that 0.05um is indicated is that the region where metal silicide is greater than source-drain area, and the Edge Distance source-drain area of metal silicide
Edge 0.05um device in electric current and voltage relation curve.It can be seen that when metal silicide is formed in source-drain area
Within when, device creepage is lower, and breakdown voltage can be higher than 25V；When except metal silicide being formed in source-drain area, electric leakage
Stream is higher, is easy to happen longitudinal break-through.
Later, other processing technologys that can continue device may include: to form interlayer dielectric layer on source-drain area 122
And the contact plug (not shown go out) etc. of interlayer dielectric layer to source-drain area 122, the metal of contact plug and source-drain area 122 can be penetrated through
Silicide layer 123 contacts；When grid 112 is polysilicon or amorphous silicon, perforation interlayer dielectric layer can also be formed to grid 112
Contact plug (not shown go out), contact plug is contacted with the metal silicide layer 115 on grid 112.
The embodiment of the present application provides a kind of manufacturing method of DDD UHV MOS device structure, can be formed on substrate
There is grid, shallow doped region is formed in the substrate of grid two sides, source-drain area can be formed in shallow doped region, source-drain area can be with shape
At metal silicide layer, in this way when source-drain area is connect with the contact plug in peripheral circuit, in the breakdown voltage for ensuring UHV high
Meanwhile metal silicide layer can be formed with source-drain area and well be contacted, and reduce the contact resistance between contact plug and source and drain, thus
The overall power of device is reduced, device performance is improved.
The manufacturing method of the DDD UHV MOS device structure of the embodiment of the present application is illustrated above, in addition, this Shen
Please embodiment additionally provide the DDD UHV MOS device structure formed by the above method, refering to what is shown in Fig. 7, including:
Substrate 100；
Grid 112 on the substrate 100；
Shallow doped region 121 in the 112 two sides substrate 100 of grid, the source-drain area 122 in the shallow doped region 121, institute
The area for stating source-drain area 122 is less than the shallow doped region 121；
The metal silicide layer 123 of the source-drain area 122.
Optionally, source-drain area 122 described in 123 covering part of metal silicide layer.
Optionally, the grid 112 is polysilicon or amorphous silicon, the device architecture further include:
The metal silicide layer 115 of the grid 112.
Optionally, grid 112 described in 115 covering part of metal silicide layer.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and the highlights of each of the examples are differences from other embodiments.Especially for memory
For part embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method reality
Apply the part explanation of example.
The above is only the preferred embodiment of the application, although the application has been disclosed in the preferred embodiments as above, so
And it is not limited to the application.Anyone skilled in the art is not departing from technical scheme ambit
Under, many possible changes and modifications all are made to technical scheme using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, all contents without departing from technical scheme, according to the application's
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within present techniques side
In the range of case protection.
Claims (10)
1. a kind of manufacturing method of DDD UHV MOS device structure characterized by comprising
Substrate is provided, grid is formed on the substrate, is formed with shallow doped region in the substrate of the grid two sides；
Source-drain area is formed in the shallow doped region；
Metal silicide layer is formed in the source-drain area.
2. the method according to claim 1, wherein described form metal silicide layer, packet in the source-drain area
It includes:
Form the mask layer of the exposure source-drain area；
It is masking with the mask layer, the metal silicide layer is formed in the source-drain area by silication technique for metal.
3. according to the method described in claim 2, it is characterized in that, source-drain area described in the mask layer expose portion.
4. the method is also the method according to claim 1, wherein the grid is polysilicon or amorphous silicon
Include:
Metal silicide layer is formed in the grid.
5. according to the method described in claim 4, it is characterized in that, described form metal silicide layer in the grid, comprising:
Form the mask layer of the exposure grid；
It is masking with the mask layer, the metal silicide layer is formed in the grid by silication technique for metal.
6. according to the method described in claim 5, it is characterized in that, grid described in the mask layer expose portion.
7. a kind of DDD UHV MOS device structure characterized by comprising
Substrate；
Grid on the substrate；
Shallow doped region in the substrate of the grid two sides, the source-drain area in the shallow doped region；
The metal silicide layer of the source-drain area.
8. device architecture according to claim 7, which is characterized in that source and drain described in the metal silicide layer covering part
Area.
9. device architecture according to claim 7, which is characterized in that the grid is polysilicon or amorphous silicon, the device
Part further include:
Metal silicide layer on the grid.
10. device architecture according to claim 9, which is characterized in that grid described in the metal silicide layer covering part
Pole.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100214523B1 (en) * | 1996-11-27 | 1999-08-02 | 구본준 | Manufacture of semiconductor device |
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| CN101211970A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and producing method thereof |
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2019
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100214523B1 (en) * | 1996-11-27 | 1999-08-02 | 구본준 | Manufacture of semiconductor device |
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| CN101211970A (en) * | 2006-12-28 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and producing method thereof |
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