CN110137194B - Pixel unit, image sensor and manufacturing method - Google Patents
Pixel unit, image sensor and manufacturing method Download PDFInfo
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- CN110137194B CN110137194B CN201910405372.5A CN201910405372A CN110137194B CN 110137194 B CN110137194 B CN 110137194B CN 201910405372 A CN201910405372 A CN 201910405372A CN 110137194 B CN110137194 B CN 110137194B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14601—Structural or functional details thereof
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- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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Abstract
The invention provides a pixel unit, an image sensor and a manufacturing method, wherein a charge storage element and a floating diffusion region are stacked on a photoelectric conversion element, so that the area of the photoelectric conversion element is increased, the full-well capacity of the photoelectric conversion element is improved, and the imaging quality is further improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a pixel unit, an image sensor and a manufacturing method.
Background
The image sensor functions to convert an optical image into a corresponding electrical signal. The image sensor is classified into a Complementary Metal Oxide Semiconductor image sensor (CMOS sensor for short) and a Charge-coupled device image sensor (CCD image sensor for short). The CCD image sensor has advantages of high image sensitivity and low noise, but the integration of the CCD image sensor with other devices is difficult and the power consumption of the CCD image sensor is high. In contrast, the CMOS image sensor has the advantages of simple process, easy integration with other devices, small volume, light weight, low power consumption, low cost, and the like. Therefore, CMOS image sensors have been widely used in still digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.
Global shutter pixel technology refers to the fact that all pixels in an imaging array start or stop exposure at the same time. Traditionally, global shutter pixel technology has been mainly used for CCD image sensors. Due to the increasing popularity of CMOS image sensors, and due to the demands of machine vision, motion picture production, industrial, automotive and scanning applications that must capture fast moving objects with high image quality, image sensor vendors have been working on overcoming the conventional barriers associated with using global shutter pixel technology on CMOS image sensors.
Among them, the Full Well Capacity (FWC) is an important parameter affecting the imaging quality of the CMOS image sensor. Fig. 1 is a schematic structural diagram of a conventional CMOS image sensor. Referring to fig. 1, the CMOS image sensor includes a photodiode 10, a memory diode 11, and a floating diffusion region 12. The photodiode 10 and the storage diode 11 can be conducted through a first transfer transistor TG1, and the storage diode 11 and the floating diffusion region 12 can be conducted through a second transfer transistor TG 2. The storage diode 11 and the floating diffusion region 12 are both disposed on an epitaxial wafer, that is, the storage diode 11, the floating diffusion region 12 and the photodiode 10 are disposed in parallel in a horizontal direction, so that the photodiode 10 has a small area and a full well capacity that cannot meet the requirement of the global shutter pixel technology under the condition of a certain wafer area.
Disclosure of Invention
The present invention is directed to a pixel unit, an image sensor and a manufacturing method thereof, which can improve the full well capacity of the photoelectric conversion element.
In order to solve the above problem, the present invention provides a pixel unit including: the photoelectric conversion element is used for receiving incident light to generate charges and comprises a first area and a second area; a charge storage element disposed above the photoelectric conversion element and corresponding to the first region, the charge storage element being insulated from the photoelectric conversion element, the charge storage element being for storing charges generated by the photoelectric conversion element; a channel layer covering at least a surface of the photoelectric conversion element located in the second region and contacting the charge storage element, for transferring charges generated by the photoelectric conversion element from the photoelectric conversion element to the charge storage element; the first transfer grid is arranged above the channel layer and insulated from the channel layer, the first transfer grid is at least arranged corresponding to the second area, and the first transfer grid is used for controlling the opening and closing of the channel layer; a floating diffusion region disposed above the charge storage element and in parallel with the first transfer gate, the floating diffusion region being insulated from the charge storage element and the first transfer gate, the floating diffusion region for storing charge from the charge storage element; and a second transfer gate disposed over and insulated from the floating diffusion region, the second transfer gate for controlling transfer of charge in the charge storage element to the floating diffusion region.
In an embodiment, the channel layer covers the charge storage element such that the channel layer is in contact with the charge storage element or the channel layer is in contact with a surface of the charge storage element facing the photoelectric conversion element.
In one embodiment, the height of at least a portion of the first transfer gate is lower than the height of the floating diffusion region.
In one embodiment, the pixel unit further includes a first insulating layer disposed between the charge storage element and the photoelectric conversion element to insulate the charge storage element from the photoelectric conversion element.
In one embodiment, the pixel cell further includes a second insulating layer covering the channel layer to insulate the first transfer gate from the channel layer and the floating diffusion region from the channel layer.
In one embodiment, the pixel unit further includes a third insulating layer disposed between the second transfer gate and the floating diffusion region to insulate the second transfer gate from the floating diffusion region.
In one embodiment, the pixel unit further includes an insulating wall disposed between the first transfer gate and the floating diffusion region to insulate the first transfer gate from the floating diffusion region.
In one embodiment, the pixel unit further includes: an interlayer dielectric layer at least covering the first transfer gate and the second transfer gate; a logic circuit layer formed above the interlayer dielectric layer; and a connection portion passing through the interlayer dielectric layer and electrically coupling the first transfer gate, the second transfer gate, and the floating diffusion layer to the logic circuit layer, respectively.
The invention also provides a CMOS image sensor which comprises the pixel unit.
The invention also provides a manufacturing method of the pixel unit, which comprises the following steps: providing a substrate; forming a photoelectric conversion element in the substrate, for receiving incident light to generate charges, the photoelectric conversion element including a first region and a second region; forming a charge storage element corresponding to the first region and insulated from the photoelectric conversion element for storing charges generated by the photoelectric conversion element, and a channel layer covering a surface of the photoelectric conversion element located in the second region and in contact with the charge storage element for transferring charges generated by the photoelectric conversion element from the photoelectric conversion element to the charge storage element, on the photoelectric conversion element; forming a first transfer gate and a floating diffusion region over the channel layer and the charge storage element, the first transfer gate being disposed at least corresponding to the second region and insulated from the channel layer, the first transfer gate being configured to control the opening and closing of the channel layer, the floating diffusion region corresponding to the charge storage element and being in parallel with the first transfer gate, the floating diffusion region being insulated from the charge storage element and the first transfer gate, the floating diffusion region being configured to store charge stored by the charge storage element; and forming a second transfer gate over the floating diffusion region, the second transfer gate being insulated from the floating diffusion region, the second transfer gate for controlling transfer of charge from the charge storage element to the floating diffusion region.
In one embodiment, the step of forming the charge storage element and the channel layer on the photoelectric conversion element further comprises the steps of: forming the charge storage element on the photoelectric conversion element, the charge storage element corresponding to the first region and being insulated from the photoelectric conversion element; the channel layer is formed on the surface of the photoelectric conversion element located in the second region and the charge storage element.
In one embodiment, the step of forming the charge storage element and the channel layer on the photoelectric conversion element further comprises the steps of: forming the channel layer on the photoelectric conversion element, the channel layer covering surfaces of the photoelectric conversion element located in the first region and the second region, and the channel layer being insulated from the photoelectric conversion element in the first region; forming the charge storage element on the channel layer, the charge storage element corresponding to a first region of the photoelectric conversion element.
In one embodiment, the step of forming the first transfer gate and the floating diffusion region over the channel layer and the charge storage element further comprises: forming a first gate layer over the channel layer and the charge storage element; forming an insulating layer on the first gate layer; forming a second gate layer on the insulating layer; patterning the second gate layer, the insulating layer and the first gate layer to divide the first gate layer, the insulating layer and the second gate layer into a first portion and a second portion, wherein the second portion corresponds to the charge storage element and at least corresponds to the second region; and filling an isolator between the first part and the second part to form an isolation wall so as to insulate the first part and the second part of the gate layer, wherein the region of the first gate layer positioned in the first part is a floating diffusion region, the region of the second gate layer positioned in the first part is the second transfer gate, and the region of the first gate layer positioned in the second part is the first transfer gate.
In one embodiment, in the step of patterning the second gate layer, the insulating layer and the first gate layer, portions of the second gate layer, the top insulating layer and the first gate layer corresponding to the second region are also removed, so that at least a portion of the first transfer gate is lower than the floating diffusion region.
In an embodiment, after the step of forming the second transfer gate over the floating diffusion region, the method for manufacturing the pixel unit further includes the steps of: forming an interlayer dielectric layer at least covering the first transfer gate and the second transfer gate; patterning the interlayer dielectric layer to form via holes respectively exposing the floating diffusion region, the first transfer gate and the second transfer gate; filling a conductive material in the via hole to form a connecting part; and forming a logic circuit layer on the interlayer dielectric layer, wherein the first transfer gate, the second transfer gate and the floating diffusion layer are electrically coupled to the logic circuit layer through the connecting part.
The photoelectric conversion device has the advantages that the charge storage element and the floating diffusion region are stacked on the photoelectric conversion element, so that the area of the photoelectric conversion element is increased, the Full Well Capacity (FWC) of the photoelectric conversion element is improved, and the imaging quality is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional CMOS image sensor;
FIG. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a pixel unit according to a third embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating steps of a method for fabricating a pixel unit according to the present invention;
FIGS. 6A-6K are process flow diagrams of a method for fabricating a pixel unit according to a first embodiment of the present invention;
FIGS. 7A-7D are a process flow diagram illustrating a method for fabricating a pixel cell according to a second embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method for fabricating a pixel unit according to a third embodiment of the present invention.
Detailed Description
The following describes in detail embodiments of a pixel unit, an image sensor and a manufacturing method according to the present invention with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the invention. Referring to fig. 2, the pixel unit of the present invention includes a photoelectric conversion device 20, a charge storage device 21, a channel layer 22, a first transfer gate 23, a floating diffusion region 24 and a second transfer gate 25.
The photoelectric conversion element 20 is configured to receive incident light to generate electric charges. The photoelectric conversion element 20 may be formed in a substrate 30. The substrate 30 includes, but is not limited to, a semiconductor substrate.
The photoelectric conversion element 20 includes, but is not limited to, a photodiode. The photoelectric conversion element 20 includes a first region a1 and a second region a 2. The first region a1 and the second region a2 may be arranged in sequence or may be arranged to intersect with each other. For example, in the present embodiment, the second region a2 surrounds the first region a1, that is, the second region a2 forms a ring-shaped structure, the first region a1 is located inside the ring-shaped structure, specifically, the photoelectric conversion element 20 is divided into two regions, that is, the first region a1 located inside and the second region a2 located at the edge, in a direction of looking down on the photoelectric conversion element 20, that is, in the Y direction in fig. 2.
The charge storage element 21 is disposed above the photoelectric conversion element 20 and corresponds to the first region a 1. That is, in the Y direction shown in fig. 2, the charge storage element 21 is disposed corresponding to the first region a1 of the photoelectric conversion element 20. The charge storage element 21 is used to store the charge generated by the photoelectric conversion element 20. The material of the charge storage element 21 is a material capable of storing charge, including but not limited to a semiconductor material, such as polysilicon. In the present embodiment, the charge storage element 21 is provided on the surface of the photoelectric conversion element 20 opposite to the light incident surface.
Wherein the charge storage element 21 is insulated from the photoelectric conversion element 20 to prevent the charge of the photoelectric conversion element 20 from being directly transferred from the photoelectric conversion element 20 to the charge storage element 21. Specifically, in the present embodiment, the pixel unit further includes a first insulating layer 31, and the first insulating layer 31 is disposed between the charge storage element 21 and the photoelectric conversion element 20 to insulate the charge storage element 21 from the photoelectric conversion element 20. The first insulating layer 31 may have a single-layer structure or a multi-layer structure, and the material thereof includes, but is not limited to, silicon oxide, silicon nitride, and combinations thereof.
The channel layer 22 covers the surface of the photoelectric conversion element 20 located in the second region a2 and is in contact with the charge storage element 21. The channel 22 is used to transfer the electric charge generated by the photoelectric conversion element 20 from the photoelectric conversion element 20 to the charge storage element 21. Specifically, the channel layer 22 is in contact with the surface of the photoelectric conversion element 20 located in the second region a2 and the charge storage element 21, and is capable of charge transfer. In the present embodiment, the channel layer 22 covers the surface of the photoelectric conversion element 20 located in the second region a2, and the channel layer 22 covers the charge storage element 21, so that charge transfer between the photoelectric conversion element 20 and the charge storage element 21 can be performed through the channel layer 22. The channel layer 22 covering the surface of the charge storage element 21 means that the channel layer 22 covers the surface of the charge storage element 21 not in contact with the first insulating layer 31. The material of the channel layer 22 is a material conventionally used in the field for a channel layer of a MOS transistor, such as a silicon material with P + type doping, and is not described herein again.
The first transfer gate 23 is disposed above the channel layer 22. That is, in the Y direction shown in fig. 2, the first transfer gate 23 is disposed corresponding to the channel layer 22. Specifically, in the Y direction, the orthographic projection area of the channel layer 22 completely overlaps with the orthographic projection area of the first transfer gate 23, or the area of the orthographic projection area of the channel layer 22 is larger than the area of the orthographic projection area of the first transfer gate 23, and the orthographic projection area of the channel layer 22 covers the orthographic projection area of the first transfer gate 23. For example, in the present embodiment, the area of the orthographic projection region of the channel layer 22 is larger than the area of the orthographic projection region of the first transfer gate 23, and the orthographic projection region of the channel layer 22 covers the orthographic projection region of the first transfer gate 23.
Wherein the first transfer gate 23 is disposed at least corresponding to the second region a 2. That is, in the Y direction shown in fig. 2, the orthographic projection area of the first transfer gate 23 at least covers the second area a 2. For example, in the present embodiment, in the Y direction, the orthographic projection area of the first transfer gate 23 covers not only the second area a2 but also the first area a 1. In other embodiments of the present invention, the first transfer gate 23 may cover only the second region a2 and not the first region a 1.
The first transfer gate 23 is used for controlling the channel layer 22 to be turned on and off. Specifically, when a voltage is applied to the first transfer gate 23, the channel layer 22 is turned on, and the charge in the photoelectric conversion element 20 is transferred into the charge storage element 21 through the channel layer 22; when the voltage applied to the first transfer gate 23 is removed, the channel layer 22 is turned off, and the charge storage element 21 temporarily stores the charge. Specifically, the principle that the channel layer 22 can be conducted is that the channel layer 22, the first transfer gate 23, the photoelectric conversion element 20, and the charge storage element 21 constitute one thin film transistor structure, and when a voltage is applied to the first transfer gate 23, the channel layer 22 corresponds to a channel region (channel) of a thin film transistor (MOS), and the channel layer 22 is conducted, so that electrons of the photoelectric conversion element 20 are transferred from the photoelectric conversion element 20 to the charge storage element 21 through the channel layer 22. Wherein, the opening and closing of the channel layer 22 can be controlled by timing control.
Note that the first transfer gate 23 is insulated from the channel layer 22. Specifically, in the present embodiment, the pixel unit further includes a second insulating layer 32, and the second insulating layer 32 covers the channel layer 22 to insulate the first transfer gate 23 from the channel layer 22. The first transfer gate 23 and the channel layer 22 may be respectively disposed on two sides of the second insulation layer 32 to insulate the first transfer gate 23 from the channel layer 22. The second insulating layer 32 may have a single-layer structure or a multi-layer structure, and the material thereof includes, but is not limited to, silicon oxide, silicon nitride, and combinations thereof.
The floating diffusion region 24 is disposed above the charge storage element 21 for storing charge from the charge storage element 21. That is, in the Y direction shown in fig. 2, the floating diffusion region 24 is disposed corresponding to the charge storage element 21. Specifically, in the Y direction, the orthogonal projection area of the floating diffusion region 24 completely overlaps the orthogonal projection area of the charge storage element 21, or the area of the orthogonal projection area of the charge storage element 21 is larger than the area of the orthogonal projection area of the floating diffusion region 24, and the orthogonal projection area of the charge storage element 21 covers the orthogonal projection area of the floating diffusion region 24. For example, in the present embodiment, the area of the forward projection region of the charge storage element 21 is larger than the area of the forward projection region of the floating diffusion region 24, and the forward projection region of the charge storage element 21 covers the forward projection region of the floating diffusion region 24.
The floating diffusion region 24 is arranged in parallel with the first transfer gate 23, that is, the floating diffusion region 24 and the first transfer gate 23 are arranged in sequence in the X direction shown in fig. 2. In this embodiment, in the X direction, the floating diffusion region 24 and the first transfer gate 23 are sequentially disposed, and in a direction (i.e., the Y direction shown in fig. 2) when the pixel unit is viewed from above, the first transfer gate 23 surrounds the floating diffusion region 24, that is, the first transfer gate 23 forms a ring structure, and the floating diffusion region 24 is located inside the ring structure.
Wherein the floating diffusion region 24 is insulated from the first transfer gate 23. Specifically, in the present embodiment, the pixel unit further includes an insulating wall 34, and the insulating wall 34 is disposed between the first transfer gate 23 and the floating diffusion region 24 to insulate the first transfer gate 23 from the floating diffusion region 24. The material of the insulating wall 34 may be any insulating material that is conventional in the art and will not be described herein.
The floating diffusion region 24 is insulated from the charge storage element 21. Specifically, in the present embodiment, since the channel layer 22 covers the charge storage element 21, the second insulating layer 32 also extends along the channel layer 22 and covers the upper region of the charge storage element 21, and the second insulating layer 32 isolates the floating diffusion region 24 from the charge storage element 24, insulating the floating diffusion region 24 from the charge storage element 24.
The second transfer gate 25 is disposed over the floating diffusion region 24. That is, in the vertical direction (Y direction shown in fig. 2), the second transfer gate 25 is disposed corresponding to the floating diffusion region 24. Specifically, in the Y direction, the orthogonal projection area of the second transfer gate 25 completely overlaps the orthogonal projection area of the floating diffusion region 24, or the area of the orthogonal projection area of the floating diffusion region 24 is larger than the area of the orthogonal projection area of the second transfer gate 25, and the orthogonal projection area of the floating diffusion region 24 covers the orthogonal projection area of the second transfer gate 25. For example, in the present embodiment, the orthographic projection area of the second transfer gate 25 completely overlaps with the orthographic projection area of the floating diffusion region 24, so that the second transfer gate 25 can act on the floating diffusion region 24 more effectively.
Wherein the second transfer gate 25 is insulated from the floating diffusion region 24. Specifically, in the present embodiment, the pixel unit further includes a third insulating layer 33, and the third insulating layer 33 is disposed between the second transfer gate 25 and the floating diffusion region 24 to insulate the second transfer gate 25 from the floating diffusion region 24. The third insulating layer 33 may have a single-layer structure or a multi-layer structure, and the material thereof includes, but is not limited to, silicon oxide, silicon nitride, and combinations thereof.
The second transfer gate 25 is used to control the transfer of charge in the charge storage element 21 to the floating diffusion region 24. Specifically, when a voltage is applied to the second transfer gate 25, the charge stored in the charge storage element 21 is transferred to the floating diffusion region 24; when the voltage applied to the second transfer gate 25 is removed, the charge storage element 21 does not transfer charge to the floating diffusion region 24. The transfer of the charge stored in the charge storage element 21 to the floating diffusion region 24 utilizes FN tunneling. Specifically, the charge storage element 21, the second insulating layer 32 and the floating diffusion region 24 form an FN tunneling transistor, and when a suitable voltage is applied to the second transfer gate 25, a gate field is formed that shortens the tunneling barrier of the charge storage element 21 (i.e., the source terminal of the FN tunneling transistor), and electrons can tunnel from the charge storage element 21 into the second insulating layer 32 and then drift to the floating diffusion region 24 (i.e., the drain terminal of the FN tunneling transistor). Wherein a voltage applied on the second transfer gate 25 may be controlled such that electrons tunnel to the floating diffusion region 24 without passing through the third insulating layer 33. For example, appropriate voltages are selected according to the thicknesses of the charge storage element 21, the second insulating layer 32, the floating diffusion region 24, the second transfer gate, and the like, so that electrons in the charge storage element 21 tunnel to the floating diffusion region 24 without passing through the third insulating layer 33.
It should be noted that when a voltage is applied to the second transfer gate 25, a partial voltage is applied to the first transfer gate 23 through the insulating wall 34, and the insulating wall 34 has a certain thickness to prevent the voltage applied to the first transfer gate 23 from being greater than the turn-on voltage of the channel layer 22 and turning on the channel layer 22. That is, the insulating wall 34 is provided so that the channel layer 22 does not conduct when a voltage is applied to the second transfer gate 25. Further, in the present embodiment, the pixel unit further includes an interlayer dielectric layer 26, a logic circuit layer 27 and a connection portion. The interlayer dielectric layer 26 covers at least the first transfer gate 23 and the second transfer gate 25. The interlayer dielectric layer 26 is made of an insulating material. The logic circuit layer 27 is formed over the interlayer dielectric layer 26. The logic circuit layer 27 is provided with circuits having the same structure as the conventional pixel unit. The connection portions pass through the interlayer dielectric layer 26 and electrically couple the first transfer gate 23, the second transfer gate 25, and the floating diffusion layer 24 to the logic circuit layer, respectively. Specifically, in the present embodiment, the connection portion includes a first conductive line 280, a second conductive line 281, and a third conductive line 282. The first conductive line 280 connects the first transfer gate 23 and the logic circuit layer 27 to electrically couple the first transfer gate 23 to the logic circuit layer 27. The second conductive line 281 connects with the second transfer gate 25 and the logic circuit layer 27 to electrically couple the second transfer gate 25 to the logic circuit layer 27. The third conductive line 282 is connected to the floating diffusion layer 24 and the logic circuit layer 27 to electrically couple the floating diffusion layer 24 to the logic circuit layer 27.
The pixel unit of the invention has the advantages that the charge storage element 21 and the floating diffusion region 24 are stacked on the photoelectric conversion element 20, the area of the photoelectric conversion element 20 is increased, the Full Well Capacity (FWC) of the photoelectric conversion element is improved, and the imaging quality is further improved. The charge storage element 21 can be turned on with the photoelectric conversion element 20 through the channel layer 22, so that charges in the photoelectric conversion element 20 can be transferred to the charge storage element 21, and the charge storage element 21 and the floating diffusion region 24 form an FN tunneling transistor, so that charges in the charge storage element 21 can be transferred to the floating diffusion region 24 under the control of the second transfer gate 25.
The pixel unit of the invention also provides a second embodiment. The second embodiment is different from the first embodiment in that the channel layer 22 and the charge storage element 21 are located at different positions. Specifically, in the second embodiment, the channel layer 22 is in contact with the surface of the charge storage element 21 facing the photoelectric conversion element 20. Fig. 3 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention, referring to fig. 3, the channel layer 22 covers the surface of the photoelectric conversion element 20 located in the second region a2, and the channel layer 22 covers the first insulating layer 31. The presence of the first insulating layer 31 insulates the channel layer 22 from the first region a1 of the photoelectric conversion element 20. The charge storage element 21 is disposed on the channel layer 22 in a region corresponding to the first insulating layer 31, that is, the charge storage element 21 is disposed on the channel layer 22 in a region corresponding to the first region a1 of the photoelectric conversion element 20. The lower surface of the charge storage element 21 is in contact with the upper surface of the channel layer 22, so that charge transfer between the photoelectric conversion element 20 and the charge storage element 21 can be performed through the channel layer 22. The present embodiment has an advantage in that the transfer path of the charge is shortened, which is more advantageous for the transfer of the charge.
The pixel unit of the invention also provides a third embodiment. The third embodiment is different from the first embodiment in that the overlapping area of the first transfer gate 23 and the floating diffusion region 24 is different. Specifically, referring to fig. 2, in the first embodiment, the first transfer gate 23 forms a ring structure, and the floating diffusion region 24 is located inside the ring structure, i.e., the side of the floating diffusion region 24 is completely surrounded by the first transfer gate 23. Whereas in the third embodiment the sides of the floating diffusion region 24 are not completely surrounded by the first transfer gate 23. Fig. 4 is a schematic structural diagram of a pixel unit according to a third embodiment of the invention. Referring to fig. 4, in the third embodiment, at least a partial region of the first transfer gate 23 is lower than the floating diffusion region 24, so that a partial side of the floating diffusion region 24 is not surrounded by the first transfer gate 23. Wherein the whole area of the first transfer gate 23 is lower than the floating diffusion region 24, or a partial area of the first transfer gate 23 is lower than the floating diffusion region 24. This is advantageous in that, when a voltage is applied to the second transfer gate 25, a portion of the voltage is applied to the first transfer gate 23 through the insulating wall 34, and since the overlapping area of the first transfer gate 23 and the floating diffusion region 24 is smaller than that of the first embodiment, the voltage applied to the first transfer gate can be reduced, thereby preventing the channel layer 22 from being turned on.
The invention also provides a CMOS image sensor which comprises a plurality of pixel units. And adjacent pixel units are isolated by an insulating medium.
The invention also provides a manufacturing method of the pixel unit. FIG. 5 is a schematic diagram illustrating a method for fabricating a pixel unit according to the present invention. Referring to fig. 5, the method for fabricating the pixel unit of the present invention includes the following steps: step S40, providing a substrate; step S41, forming a photoelectric conversion element in the substrate for receiving incident light to generate charges, the photoelectric conversion element including a first region and a second region; step S42, forming a charge storage element and a channel layer on the photoelectric conversion element, wherein the charge storage element corresponds to the first region, is insulated from the photoelectric conversion element, and is used for storing charges generated by the photoelectric conversion element, and the channel layer covers the surface of the photoelectric conversion element in the second region, is in contact with the charge storage element, and is used for transferring charges generated by the photoelectric conversion element from the photoelectric conversion element to the charge storage element; step S43, forming a first transfer gate and a floating diffusion region over the channel layer and the charge storage element, the first transfer gate being at least corresponding to the second region and insulated from the channel layer, the first transfer gate being used for controlling the on and off of the channel layer, the floating diffusion region corresponding to the charge storage element and being parallel to the first transfer gate, the floating diffusion region being insulated from the charge storage element and the first transfer gate, the floating diffusion region being used for storing charges stored by the charge storage element; step S44, forming a second transfer gate over the floating diffusion region, the second transfer gate being insulated from the floating diffusion region, the second transfer gate being used to control the transfer of the charges in the charge storage element to the floating diffusion region.
Fig. 6A to 6K are process flow diagrams of a method for fabricating a pixel unit according to a first embodiment of the invention.
In step S40 and fig. 6A, a substrate 500 is provided. The substrate 500 includes, but is not limited to, a semiconductor substrate.
Referring to step S41 and fig. 6B, a photoelectric conversion device 501 is formed in the substrate 500. The photoelectric conversion element 501 is used to receive incident light to generate electric charges. The photoelectric conversion element 501 includes a first region a1 and a second region a 2. The photoelectric conversion element 501 includes, but is not limited to, a photodiode. Methods for forming the photoelectric conversion element 501 are well known to those skilled in the art and will not be described herein.
In step S42, a charge storage device 502 and a channel layer 503 are formed on the photoelectric conversion device 501. Specifically, the charge storage element 502 and the channel layer 503 are formed on the surface of the photoelectric conversion element 501 opposite to the light incident surface. The charge storage element 502 corresponds to the first region a1, and is insulated from the photoelectric conversion element 501, and the channel layer 503 covers the surface of the photoelectric conversion element 501 located in the second region a2 and is in contact with the charge storage element 502. The charge storage element 502 is used to store the charge generated by the photoelectric conversion element 501, and the channel layer 503 is used to transfer the charge generated by the photoelectric conversion element 501 from the photoelectric conversion element 501 to the charge storage element 502.
Wherein the charge storage element 502 and the channel layer 503 may have two positional relationships, a first positional relationship is that the channel layer 503 covers the surface of the photoelectric conversion element 501 located in the second region a2, and the channel layer 503 covers the charge storage element 502; a second positional relationship is that the channel layer 503 is in contact with a surface of the charge storage element 502 facing the photoelectric conversion element 501, rather than covering the charge storage element 502.
In the present embodiment, a process flow of the charge storage device 502 and the channel layer 503 will be described by taking a first positional relationship as an example. That is, the channel layer 503 covers the surface of the photoelectric conversion element 501 located in the second region a2, and the channel layer 503 covers the charge storage element 502.
First, the charge storage element 502 is formed on the photoelectric conversion element 501, and the charge storage element 502 corresponds to the first region a1 and is insulated from the photoelectric conversion element 501.
Specifically, referring to fig. 6C, an insulating layer 530 and a charge storage layer 531 are sequentially formed on the photoelectric conversion element 501. The insulating layer 530 may have a single-layer structure or a multi-layer structure. For example, in the present embodiment, the insulating layer 530 is a multi-layer structure including oxide, nitride and a combination thereof. The material of the charge storage layer 531 includes, but is not limited to, a semiconductor, for example, polysilicon. Referring to fig. 6D, the charge storage layer 531 and the insulating layer 530 are patterned. In the first region a1, the charge storage layer 531 and the insulating layer 530 located below the charge storage layer 531 are left, a portion of the charge storage layer 531 left is the charge storage element 502, and a portion of the insulating layer 530 left is the first insulating layer 504 between the charge storage element 502 and the photoelectric conversion element 501; in the second region a2, the surface of the photoelectric conversion element 501 is exposed. The method for patterning the charge storage layer 531 and the insulating layer 530 includes, but is not limited to, a photolithography process that is conventional in the art.
Next, referring to fig. 6E, the channel layer 503 is formed on the surface of the photoelectric conversion element 501 located in the second region a2 and the charge storage element 502, that is, the channel layer 503 covers the surface of the photoelectric conversion element 501 located in the second region a2 and the charge storage element 502. The channel layer 503 includes, but is not limited to, a semiconductor layer having P + type doping. Methods of forming the channel layer 503 include, but are not limited to, conventional deposition processes.
In a second embodiment of the method for fabricating a pixel unit according to the present invention, a second positional relationship between the charge storage device and the channel layer is taken as an example to describe a process flow thereof. Specifically, the channel layer 503 is in contact with a surface of the charge storage element 502 facing the photoelectric conversion element 501.
First, the channel layer 503 is formed on the photoelectric conversion element 501, and the channel layer 503 covers the surfaces of the photoelectric conversion element 501 located in the first region a1 and the second region a 2.
Specifically, referring to fig. 7A, an insulating layer 530 is formed on the photoelectric conversion element 501. Referring to fig. 7B, the insulating layer 530 is patterned, and only the insulating layer in the first region a1 is remained, and the remained insulating layer serves as the first insulating layer 504. Referring to fig. 7C, a channel layer 503 is formed, the channel layer 503 covers the surface of the photoelectric conversion device 501 located in the second region a2 and the first insulating layer 504, and the channel layer 503 is a semiconductor layer with P + type doping.
Next, referring to fig. 7D, a charge storage layer is formed on the channel layer 503, and the charge storage layer is patterned, wherein the remaining portion of the charge storage layer is the charge storage element 502, and the charge storage element 502 corresponds to the first region a1 of the photoelectric conversion element 501. The method for patterning the charge storage layer includes, but is not limited to, a photolithography process.
With continuing reference to steps S43 and S44, a first transfer gate 505 and a floating diffusion 506 are formed over the channel layer 503 and the charge storage element 502; a second transfer gate 507 is formed over the floating diffusion region 506.
In the first embodiment, the specific process steps for forming the first transfer gate 505, the floating diffusion region 506 and the second transfer gate 507 are described as follows:
referring to fig. 6F, a bottom insulating layer 540, a first gate layer 541, a top insulating layer 542, and a second gate layer 543 are sequentially formed over the channel layer 503 and the charge storage element 502. Wherein the underlying insulating layer 540 insulates the first gate layer 541 from the channel layer 503 and the charge storage element 502. Specifically, in the present embodiment, since the channel layer 503 covers the charge storage element 502, the bottom insulating layer 540 is formed on the channel layer 503, the first gate layer 541 is formed on the bottom insulating layer 540, and the top insulating layer 542 is formed on the first gate layer 541. The bottom insulating layer 540 and the top insulating layer 542 may have the same or different structures, including but not limited to silicon oxide, silicon nitride, and combinations thereof. The materials of the first gate layer 541 and the second gate layer 543 include, but are not limited to, semiconductor materials such as polysilicon.
Referring to fig. 6G, the second gate layer 543, the top insulating layer 542 and the first gate layer 541 are patterned to separate the second gate layer 543, the top insulating layer 542 and the first gate layer 541 into a first portion and a second portion. Wherein the first portion corresponds to the charge storage element 502 and the second portion corresponds to at least the second region a 2. Specifically, the second gate layer 543, the top insulating layer 542 and the first gate layer 541 are patterned by a photolithography process to form a trench 544, so as to form a first portion and a second portion. In this embodiment, the bottom insulating layer 540 is not patterned, and in other embodiments of the present invention, the bottom insulating layer 540 may be patterned as well, subject to process conditions. Referring to fig. 6H, the trench 544 between the first portion and the second portion is filled with spacers to form the isolation wall 508. The material of the isolation wall 508 includes, but is not limited to, silicon oxide, silicon nitride, and combinations thereof. The first gate layer 541 located in the first portion serves as the floating diffusion 506, the first gate layer 541 located in the second portion serves as the first transfer gate 505, the second gate layer 543 located in the first portion serves as the second transfer gate 507, and the top insulating layer 542 located in the first portion serves as the insulating layer 509 between the second gate layer 543 and the floating diffusion 506. In this embodiment, due to the limitation of the process flow, the top insulating layer 542 and the second gate layer 543 in the second portion are not removed, and in other embodiments of the present invention, the top insulating layer 542 and the second gate layer 543 in the second portion may also be removed.
The first transfer gate 505 is disposed at least corresponding to the second region a2 and insulated from the channel layer 503, the first transfer gate 505 is used for controlling the on and off of the channel layer 503, the floating diffusion region 506 is corresponding to the charge storage element 502 and insulated from the charge storage element 502 and the first transfer gate 505, and the floating diffusion region 506 is used for storing the charge stored by the charge storage element 502.
Of course, in other embodiments of the present invention, the second transfer gate 507 may be formed after the first transfer gate 505 and the floating diffusion 506 are formed, and details are not repeated here.
In the present embodiment, the second gate layer 543, the top insulating layer 542 and the first gate layer 541 corresponding to the second region a2 are all remained, but in another embodiment of the present invention, in the step of forming the trench 544, portions of the second gate layer 543, the top insulating layer 542 and the first gate layer 541 corresponding to the second region a2 are also removed, so that at least a portion of the first transfer gate 505 is lower than the floating diffusion region 506. Specifically, referring to fig. 8, in the step of forming the trench 544, portions of the second gate layer 543, the top insulating layer 542 and the first gate layer 541 corresponding to the second region a2 are removed, for example, in the region B in fig. 8, the second gate layer 543, the top insulating layer 542 and the first gate layer 541 are removed. The first gate layer 541 is not completely removed due to the limitation of the process. This step makes the first transfer gate 505 of the finally formed pixel unit lower than the floating diffusion region 506 at least in a partial region so that a partial side of the floating diffusion region 506 is not surrounded by the first transfer gate 505.
Further, after the step of forming the second transfer gate 505 over the floating diffusion region 506, the method for manufacturing the pixel unit further includes the steps of:
referring to fig. 6I, an interlayer dielectric layer 510 is formed and the interlayer dielectric layer 510 is patterned. The interlayer dielectric layer 510 covers at least the first transfer gate 505 and the second transfer gate 507. The interlayer dielectric layer 510 is an insulating layer. The interlayer dielectric layer 510 is patterned to form via holes 510A exposing the floating diffusion region 506, the first transfer gate 505 and the second transfer gate 507, respectively. The via 510A may be formed by a photolithography process. In other embodiments of the present invention, since the via hole exposing the floating diffusion region 506 needs to pass through the second transfer gate 507, a via hole passing through the second transfer gate 507 and the insulating layer 509 may be formed before forming the interlayer dielectric layer 510, and a via hole passing through the interlayer dielectric layer 510 may be correspondingly formed after forming the interlayer dielectric layer 510.
Referring to fig. 6J, a conductive material is filled in the via 510A to form a connection portion. Specifically, a first conductive line 511, a second conductive line 512, and a third conductive line 513 are formed in the via hole. The first conductive line 511 is connected to the first transfer gate 505, the second conductive line 512 is connected to the second transfer gate 507, and the third conductive line 513 is connected to the floating diffusion layer 506. Since the third conductive line 513 passes through the second transfer gate 507, an insulating layer 514 may be disposed on a sidewall of the via hole to insulate the third conductive line 513 from the second transfer gate 507. The step of forming the insulating layer 514 may be performed before the step of forming the connection portion.
Referring to fig. 6K, a logic circuit layer 515 is formed on the interlayer dielectric layer 510. The first transfer gate 505, the second transfer gate 507, and the floating diffusion layer 506 are electrically coupled to the logic circuit layer 515 through the connection portion. Specifically, the first conductive line 511 electrically couples the first transfer gate 23 to the logic circuit layer 515; the second conductive line 512 electrically couples the second transfer gate 507 to the logic circuit layer 515, and the third conductive line 513 electrically couples the floating diffusion layer 506 to the logic circuit layer 515.
The pixel unit prepared by the preparation method of the pixel unit is provided with the charge storage element and the floating diffusion region in a stacking mode on the photoelectric conversion element, so that the area of the photoelectric conversion element is increased, the Full Well Capacity (FWC) of the photoelectric conversion element is improved, and the imaging quality is further improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A method for manufacturing a pixel unit is characterized by comprising the following steps:
providing a substrate;
forming a photoelectric conversion element in the substrate, wherein the photoelectric conversion element comprises a first region and a second region;
forming a charge storage element and a channel layer on the photoelectric conversion element, the charge storage element corresponding to the first region and being insulated from the photoelectric conversion element, the channel layer covering a surface of the photoelectric conversion element located in the second region and being in contact with the charge storage element;
forming a first transfer gate and a floating diffusion region over the channel layer and the charge storage element, the first transfer gate being disposed at least in correspondence with the second region and insulated from the channel layer, the floating diffusion region being in correspondence with the charge storage element and in parallel with the first transfer gate, the floating diffusion region being insulated from the charge storage element and the first transfer gate; and
forming a second transfer gate over the floating diffusion region, the second transfer gate being insulated from the floating diffusion region;
the step of forming the first transfer gate and the floating diffusion region over the channel layer and the charge storage element further comprises:
forming a first gate layer over the channel layer and the charge storage element;
forming an insulating layer on the first gate layer;
forming a second gate layer on the insulating layer;
patterning the second gate layer, the insulating layer and the first gate layer to divide the first gate layer, the insulating layer and the second gate layer into a first portion and a second portion, wherein the second portion corresponds to the charge storage element and at least corresponds to the second region;
and filling an isolator between the first part and the second part to form an isolation wall so as to insulate the first part and the second part of the gate layer, wherein the region of the first gate layer positioned in the first part is a floating diffusion region, the region of the second gate layer positioned in the first part is the second transfer gate, and the region of the first gate layer positioned in the second part is the first transfer gate.
2. The method of manufacturing a pixel unit according to claim 1, wherein the step of forming the charge storage element and the channel layer on the photoelectric conversion element further comprises the steps of:
forming the charge storage element on the photoelectric conversion element, the charge storage element corresponding to the first region and being insulated from the photoelectric conversion element;
the channel layer is formed on the surface of the photoelectric conversion element located in the second region and the charge storage element.
3. The method of manufacturing a pixel unit according to claim 1, wherein the step of forming the charge storage element and the channel layer on the photoelectric conversion element further comprises the steps of:
forming the channel layer on the photoelectric conversion element, the channel layer covering surfaces of the photoelectric conversion element located in the first region and the second region, and the channel layer being insulated from the photoelectric conversion element in the first region;
forming the charge storage element on the channel layer, the charge storage element corresponding to a first region of the photoelectric conversion element.
4. The method of claim 1, wherein in the step of patterning the second gate layer, the insulating layer and the first gate layer, portions of the second gate layer, the top insulating layer and the first gate layer corresponding to the second region are removed such that at least a portion of the first transfer gate is below the floating diffusion region.
5. The method of claim 1, wherein after the step of forming the second transfer gate over the floating diffusion region, the method further comprises the steps of:
forming an interlayer dielectric layer at least covering the first transfer gate and the second transfer gate;
patterning the interlayer dielectric layer to form via holes respectively exposing the floating diffusion region, the first transfer gate and the second transfer gate;
filling a conductive material in the via hole to form a connecting part;
forming a logic circuit layer on the interlayer dielectric layer, the first transfer gate, the second transfer gate and the floating diffusion region being electrically coupled to the logic circuit layer through the connection portion.
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Effective date of registration: 20221222 Address after: 223001 Room 318, Building 6, east of Zhenda Steel Pipe Company, south of Qianjiang Road, Huaiyin District, Huai'an City, Jiangsu Province Patentee after: Huaian Xide Industrial Design Co.,Ltd. Address before: 223300 no.599, East Changjiang Road, Huaiyin District, Huai'an City, Jiangsu Province Patentee before: HUAIAN IMAGING DEVICE MANUFACTURER Corp. |