CN110137180B - Ferroelectric device and method of manufacturing the same - Google Patents
Ferroelectric device and method of manufacturing the same Download PDFInfo
- Publication number
- CN110137180B CN110137180B CN201811365456.2A CN201811365456A CN110137180B CN 110137180 B CN110137180 B CN 110137180B CN 201811365456 A CN201811365456 A CN 201811365456A CN 110137180 B CN110137180 B CN 110137180B
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 16
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Abstract
The invention provides a ferroelectric device and a method for manufacturing the same. In a method of fabricating a ferroelectric device, a substrate is provided. A ferroelectric material film is formed over a substrate. A crystallization seed film is formed over the ferroelectric material film. The ferroelectric material film is heat-treated with a crystallization seed film to convert the ferroelectric material film into a crystalline ferroelectric film. The crystallization seed film is removed to expose the crystalline ferroelectric film. An electrode film is formed over the ferroelectric film.
Description
Cross Reference to Related Applications
The present application claims priority from korean patent application No. 10-2018-0015858 filed on 8, 2 nd month 2018, which is incorporated herein by reference in its entirety.
Technical Field
Various embodiments of the present disclosure relate generally to a semiconductor device, and more particularly, to a ferroelectric memory device and a method of manufacturing the same.
Background
In general, ferroelectric materials have spontaneous electric polarization when no external electric field is applied to the ferroelectric material. In addition, the ferroelectric material may be controlled to maintain one of two stable polarization states on the ferroelectric hysteresis curve. This feature may be used in a memory device to store logic information of "0" or "1" in a nonvolatile manner.
Recently, field effect transistor type ferroelectric memory devices have been introduced in which ferroelectric materials are applied to a gate dielectric layer. The writing operation of the field effect transistor type ferroelectric memory device can be performed by supplying a predetermined writing voltage to the gate electrode layer and writing different polarization states in the gate dielectric layer as logic information. The read operation of the ferroelectric memory device can be performed by detecting an operating current passing through the channel of the field effect transistor type ferroelectric memory device by using a characteristic that the channel resistance of the field effect transistor type ferroelectric memory device changes according to the polarization state written in the gate dielectric layer.
Disclosure of Invention
According to one aspect of the present disclosure, a method of fabricating a ferroelectric device is provided. In the method, a substrate is provided. A ferroelectric material film is formed over the substrate. A crystallization seed film is formed over the ferroelectric material film. The ferroelectric material film is heat-treated with a crystallization seed film to convert the ferroelectric material film into a crystalline ferroelectric film. Removing the crystallization seed film to expose the crystalline ferroelectric film. An electrode film is formed over the crystalline ferroelectric film.
According to another aspect of the present disclosure, a method of fabricating a ferroelectric device is provided. In the method, a substrate is provided. A crystallization seed film is formed over the substrate. A ferroelectric material film is formed over the crystallization seed film. The ferroelectric material film is heat-treated to convert the ferroelectric material film into a crystalline ferroelectric film. An electrode film is formed on the crystalline ferroelectric film.
According to another aspect of the present disclosure, a ferroelectric device is provided. The ferroelectric device includes: a substrate, an interface insulating layer disposed over the substrate, a crystallization seed layer disposed over the interface insulating layer, a ferroelectric layer disposed over the crystallization seed layer, and a gate electrode layer disposed over the ferroelectric layer. The crystallization seed layer includes a dielectric layer having a dielectric constant greater than a dielectric constant of the interfacial insulating layer.
According to another aspect of the present disclosure, a ferroelectric device is provided. The ferroelectric device includes: a substrate, a ferroelectric layer disposed over the substrate, and a gate electrode layer disposed over the ferroelectric layer. The ferroelectric layer has a thickness of 3nm to 15nm, and an average grain size of the ferroelectric layer is smaller than the thickness of the ferroelectric layer.
Drawings
Fig. 1 is a cross-sectional view schematically illustrating a ferroelectric device according to one embodiment of the present disclosure.
Fig. 2 is a flow chart schematically illustrating a method of manufacturing a ferroelectric device according to one embodiment of the present disclosure.
Fig. 3 to 8 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to one embodiment of the present disclosure.
Fig. 9 is a cross-sectional view schematically illustrating a ferroelectric device according to another embodiment of the present disclosure.
Fig. 10 is a flowchart schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
Fig. 11 to 17 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
Fig. 18 is a cross-sectional view schematically illustrating a ferroelectric device according to another embodiment of the present disclosure.
Fig. 19 is a graph schematically illustrating ferroelectric characteristics of a ferroelectric layer according to one embodiment of the present disclosure.
Fig. 20 is a diagram illustrating a crystal structure of a ferroelectric layer according to one embodiment of the present disclosure.
Fig. 21 and 22 are graphs illustrating polarization changes according to one embodiment of the present disclosure.
Fig. 23 is a flowchart schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
Fig. 24 to 26 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
Detailed Description
Various embodiments will now be described hereinafter with reference to the accompanying drawings. In the drawings, the size of layers and regions may be exaggerated for clarity of illustration. The figures are described with respect to the perspective of a viewer. If an element is referred to as being "on" another element, it can be understood that the element is directly on the other element or additional elements can be interposed between the one element and the other element. Like numbers refer to like elements throughout.
In addition, the expression singular forms of words should be understood to include the plural forms of words unless the context clearly does not so. It should be understood that the terms "comprises" or "comprising" are intended to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but are not intended to preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. In addition, when a method or a manufacturing method is performed, each process constituting the method may be performed in a different order than the prescribed order unless the specific order is explicitly described in the context. In other words, each process may be performed in the same manner as the recited order, may be performed substantially simultaneously, or may be performed in the reverse order.
Fig. 1 is a cross-sectional view schematically showing a ferroelectric device 1 according to one embodiment of the present disclosure. Referring to fig. 1, a ferroelectric device 1 may include a substrate 101, an interface insulating layer 115, a ferroelectric layer 125, and a gate electrode layer 145. In one embodiment, ferroelectric device 1 may be a transistor-type memory device in which different channel resistances are achieved depending on the polarization direction (polarization orientation) written into ferroelectric layer 125.
The ferroelectric device 1 described in the present embodiment can perform the following memory operation. In the write operation, when a predetermined write voltage is applied to the ferroelectric layer 125 via the gate electrode layer 145, polarization having a predetermined polarization direction may be written in the ferroelectric layer 125. Further, even after the write voltage is removed, the polarization having the predetermined polarization direction may remain in the ferroelectric layer 125, thereby storing data information corresponding to the polarization in a nonvolatile manner. Depending on the predetermined polarization direction, the remnant polarization (remanent polarization) can induce electrons into the channel region 105 of the substrate 101 or can emit electrons from the channel region 105. Alternatively, depending on the predetermined polarization direction, the remnant polarization may induce holes into the channel region 105, or holes may be emitted from the channel region 105.
The channel region 105 may be a region below the interface insulating layer 115 in the substrate 101, and may be a region in which conductive carriers such as electrons or holes are concentrated.
In a read operation, when a read voltage is applied to the gate electrode layer 145, a channel, which is a path of carrier conduction, may be formed in the channel region 105 between the source region 150 and the drain region 160. The resistance of the channel will be referred to as the "channel resistance".
In a read operation of the ferroelectric device 1, when a read voltage is applied to the gate electrode layer 145, charges may be induced into the channel region 105 due to an electric attraction of the remnant polarization of the ferroelectric layer 125. At this time, the channel resistance between the source region 150 and the drain region 160 may vary according to the type and amount of charges induced. For example, for a ferroelectric device having an N-type field effect transistor type, when the density of electrons induced in the channel region 105 increases due to a read voltage having a positive polarity, the channel resistance may decrease. Accordingly, the data information stored in the ferroelectric device 1 can be read by measuring the change in the channel resistance.
The substrate 101 may comprise a semiconductor material. The substrate 101 may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. In one embodiment, the substrate 101 may be doped to have conductivity. For example, the substrate 101 may be doped with a p-type dopant or an n-type dopant.
The source region 150 and the drain region 160 may be disposed in the substrate 101 at both ends or opposite sides of the gate electrode layer 145. In one embodiment, the source region 150 and the drain region 160 may be doped to have a conductivity type opposite to that of the substrate 101. For example, when the substrate 101 is doped with a p-type dopant, the source region 150 and the drain region 160 may be doped with an n-type dopant. On the other hand, when the substrate 101 is doped with an n-type dopant, the source region 150 and the drain region 160 may be doped with a p-type dopant.
An interface insulating layer 115 may be disposed on the substrate 101. An interface insulating layer 115 may be interposed between the substrate 101 and the ferroelectric layer 125 to inhibit diffusion of material between the substrate 101 and the ferroelectric layer 125 during the fabrication process. In addition, the interface insulating layer 115 can prevent direct contact between the substrate 101 and the ferroelectric layer 125 having crystal lattices of different sizes, thereby suppressing generation of crystal defects due to stress at the interface between the substrate 101 and the ferroelectric layer 125. The interface insulating layer 115 may have an amorphous structure.
The interface insulating layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. In one embodiment, when the substrate 101 is a silicon (Si) substrate, the interface insulating layer 115 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The interface insulating layer 115 may have a thickness of about 1nm to about 5 nm.
Meanwhile, in one embodiment, depending on the polarization direction, remnant polarization may induce electrons into the channel region 105 of the substrate 101, or may emit electrons from the channel region 105. When the density of electrons distributed in the channel region 105 changes due to remnant polarization, the channel resistance between the source region 150 and the drain region 160 may change in a read operation. In one embodiment, ferroelectric layer 125 may have a thickness of about 3nm to about 15 nm.
In one embodiment, ferroelectric layer 125 may comprise a crystalline metal oxide. Ferroelectric layer 125 may comprise a binary metal oxide. Ferroelectric layer 125 may include hafnium oxide, zirconium oxide, or a combination thereof. At this time, the ferroelectric layer 125 may have a quadrature crystal (orthorhombic crystal) structure.
In one embodiment, ferroelectric layer 125 may include at least one dopant. The dopant may be uniformly distributed in the ferroelectric layer 125. The dopant distributed in the ferroelectric layer 125 may stabilize the ferroelectric properties of the ferroelectric layer 125. When the ferroelectric layer 125 includes hafnium oxide, zirconium oxide, or a combination thereof, the ferroelectric layer 125 may include a dopant having a valence state of 2 to 4. For example, the dopant of the ferroelectric layer 125 may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La), or a combination thereof.
A gate electrode layer 145 may be disposed on the ferroelectric layer 125. The gate electrode layer 145 may include a conductive material. The gate electrode layer 145 may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.
As described above, a ferroelectric device according to one embodiment of the present disclosure may include a ferroelectric layer having a grain size controlled to a predetermined value. Thus, ferroelectric properties such as remnant polarization and coercive electric field can be effectively controlled by the grain size of the ferroelectric layer. As a result, the reliability of the writing operation and the reading operation of the ferroelectric device can be improved due to the properly controlled ferroelectric characteristics.
Fig. 2 is a flow chart schematically illustrating a method of manufacturing a ferroelectric device according to one embodiment of the present disclosure.
In step S110, a substrate may be prepared. The substrate may comprise a semiconductor material. For example, the substrate may be a p-type doped silicon substrate.
In step S120, an amorphous ferroelectric material film may be formed over the substrate. The ferroelectric material film may include hafnium oxide, zirconium oxide, or a combination thereof. The ferroelectric material film may further include a dopant. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or a combination thereof. In one embodiment, the ferroelectric material film may be a hafnium oxide layer doped with silicon (Si). In another embodiment, the ferroelectric material film may be an undoped hafnium oxide layer. The ferroelectric material film may be formed using a chemical vapor deposition method or an atomic layer deposition method. At this time, the amorphous ferroelectric material film may be formed by controlling process conditions such as a deposition temperature, a deposition pressure, and the like.
In step S130, a crystallization seed (crystallization seed) film may be formed on the ferroelectric material film. The crystallization seed film may have a crystalline structure. The crystallization seed film may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), or a combination thereof. The crystallization seed film may be a polysilicon film. In one embodiment, the crystallization seed film may be formed as follows. First, the grain size of the crystallization seed film and the thickness of the crystallization seed film corresponding to the grain size may be determined. Then, the crystallized seed film having a determined grain size may be deposited to have a determined thickness by controlling the film deposition process. In one embodiment, the crystallization seed film may be formed at a temperature lower than the crystallization temperature of the ferroelectric material film.
In step S140, a heat treatment may be performed on the crystalline seed film and the ferroelectric material film to form a crystalline ferroelectric film. In one embodiment, the heat treatment may be performed in a state where the crystallization seed film covers the ferroelectric material film. Thus, in the heat treatment process, crystallization of the seed film may cause crystallization of the amorphous ferroelectric material film, so that the amorphous ferroelectric material film is converted into a crystalline ferroelectric film. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) In a predetermined gas atmosphere of argon (Ar) or a combination thereof. The heat treatment may be performed at a temperature of about 500 ℃ to about 1000 ℃.
In one embodiment, the grain size of the crystalline ferroelectric film formed by the heat treatment may be substantially the same as the grain size of the crystallization seed film. In one embodiment, the crystallization seed film may be formed in step S130 by considering the grain size of the crystallization ferroelectric film, and the grain size of the crystallization ferroelectric film may be determined by heat treatment in step S140.
In step S150, the crystallization seed film disposed on the crystalline ferroelectric film may be removed to expose the crystalline ferroelectric film. In one embodiment, the crystallization seed film may be removed using an etching method or a polishing method.
In step S160, an electrode film may be formed on the crystalline ferroelectric film. The electrode film may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.
Although not shown in fig. 2, a process of patterning the electrode film and the crystalline ferroelectric film may be additionally performed. As a result, a ferroelectric layer and a gate electrode layer can be formed over the substrate. In addition, a process of selectively implanting dopants into the exposed regions of the substrate may be performed. The exposed regions of the substrate are disposed at both ends or opposite sides of the gate electrode layer. As a result, source and drain regions may be formed in the exposed region of the substrate.
In some other embodiments, before step S120, an interface insulating film may be additionally formed over the substrate such that the interface insulating film is disposed between the substrate and the ferroelectric material film. The interface insulating film may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). Then, after steps S130 to S160 are performed, the interface insulating film, the crystalline ferroelectric film, and the electrode film sequentially stacked over the substrate may be patterned to form an interface insulating layer, a ferroelectric layer, and a gate electrode layer over the substrate.
By performing the above-described process, a ferroelectric device is manufactured. In some embodiments, the crystallization seed film may have a lattice constant different from that of the ferroelectric film. For example, when the ferroelectric film includes hafnium oxide (HfO 2 ) When hafnium oxide (HfO) 2 ) Has about
Is a lattice constant of (c). At this time, the crystallization seed film may include silicon carbide (SiC), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. Silicon carbide (SiC) has a composition of about +.>
Is a lattice constant of (2); silicon (Si) has about->
Is a lattice constant of (2); germanium (Ge) has a concentration of about->
Is a lattice constant of (2); silicon germanium (SiGe) has a lattice constant between that of silicon (Si) and germanium (Ge).
In the heat treatment of step S140, lattice stress may be generated in the ferroelectric film in which crystallization is performed due to the difference in lattice constants of the crystallization seed film and the ferroelectric film. In particular, the lattice stress may create a gradient from the interface between the ferroelectric film and the crystallization seed film to the lattice stress in the ferroelectric film. The gradient may create a flexoelectric effect (flexoelectric effect) to create an electric field within the ferroelectric film. As a result, an electric field formed within the ferroelectric film can improve polarization alignment (polarization alignment) in the ferroelectric film, thereby stabilizing ferroelectric characteristics of the ferroelectric film. The ferroelectric properties may include remnant polarization properties or coercive electric field properties.
Fig. 3 to 8 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to one embodiment of the present disclosure.
Referring to fig. 3, a substrate 101 may be prepared. The substrate 101 may comprise a semiconductor material. The substrate 101 may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. In one embodiment, the substrate 101 may be doped to have conductivity. For example, the substrate 101 may be doped with a p-type or n-type dopant. In one embodiment, the substrate 101 may be a p-type doped silicon substrate.
Next, an interface insulating film 110 may be formed on the substrate 101. The interface insulating film 110 may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). The interface insulating film 110 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like. The interface insulating film 110 may be formed in an amorphous state. The interface insulating film 110 may be formed to a thickness of about 1nm to about 5 nm.
Then, the ferroelectric material film 120 may be formed on the interface insulating film 110. In one embodiment, the ferroelectric material film 120 may include a binary metal oxide. For example, the ferroelectric material film 120 may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The ferroelectric material film 120 may be deposited using chemical vapor depositionMethods, atomic layer deposition methods, and the like. The ferroelectric material film 120 may be formed to a thickness of about 3nm to about 15 nm.
In one embodiment, the ferroelectric material film 120 may include at least one dopant. The dopant may be distributed in the ferroelectric material film 120. For example, the ferroelectric material film 120 may include a dopant having a valence of 2 to 4. The dopant can stably maintain the ferroelectric property of the ferroelectric material film 120 after the ferroelectric material film 120 is crystallized. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or combinations thereof. In one embodiment, the dopant may be provided with the source chemical material of the ferroelectric material film 120 when forming the ferroelectric material film 120. In another embodiment, after formation of the ferroelectric material film 120 is completed, dopants may be provided into the ferroelectric material film 120 by an ion implantation method.
Then, a crystallization seed film 130 may be formed on the ferroelectric material film 120. The crystallization seed film 130 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC). The crystallization seed film 130 may be a polysilicon film. The crystallization seed film 130 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like. In one embodiment, the crystallization seed film 130 may be formed at a temperature lower than the crystallization temperature of the ferroelectric material film 120. In one embodiment, when the ferroelectric material film 120 is a hafnium oxide film or a zirconium oxide film, the process of forming the crystallization seed film 130 may be performed at a process temperature lower than 500 ℃.
Fig. 4A and 4B are each a cross-sectional view illustrating a process of forming a crystallization seed film according to an embodiment of the present disclosure. More specifically, fig. 4A shows that a film having a first thickness T is formed on the ferroelectric material film 120 by performing a film forming process for a first period of time 1 And fig. 4B shows a state of the crystallization seed film 130A, and a second thickness T is formed on the ferroelectric material film 120 by performing the film forming process for a second period of time longer than the first period of time 2 A state of the crystallization seed film 130B. For the purpose of For convenience of description, the substrate 101 and the interface insulating layer 110 are omitted in fig. 4A and 4B.
Referring to FIG. 4A, having a first thickness T 1 The crystallization seed film 130A of (1) may include a first width W 1 Grain G120i of the average size of (3). In contrast, referring to FIG. 4B, there is a second thickness T 2 The crystallization seed film 130B of (1) may include a film having a second width W 2 Grain G120f of average size, second width W 2 Greater than the first width W 1 . That is, as the thickness of the crystallization seed film increases, the grain size of the crystallization seed film may increase. As the grain size of the crystallization seed film increases, the number of grains per unit volume of the crystallization seed film decreases. For ease of description, FIGS. 4B and 5 illustrate a display including a display having a second width W 2 A crystallization seed film of three grains G120f of the average size.
In one embodiment, the process of forming crystallization seed film 130 may be performed as follows. First, a final grain size of the crystallization seed film 130 and a thickness of the crystallization seed film 130 corresponding to the final grain size may be determined. Next, the crystallization seed film 130 may be formed to have a certain grain size and thickness by controlling the conditions of the film deposition process. Methods of controlling the conditions of the film deposition process may include controlling process temperature, process time, process pressure, etc. For example, the final grain size of the crystallization seed film 130 may be obtained by controlling the thickness of the crystallization seed film 130.
Referring to fig. 5, the heat treatment for the ferroelectric material film 120 may be performed in a state where the crystallization seed film 130 covers the ferroelectric material film 120. That is, the crystallization seed film 130 may be in contact with the ferroelectric material film 120 during the heat treatment. Thus, crystallizing the seed film 130 during the heat treatment may cause crystallization of the amorphous ferroelectric material film 120. The heat treatment may be performed at a process temperature of about 500 ℃ to about 1000 ℃. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Performed in a gaseous atmosphere of argon (Ar), or a combination thereof.
By performing heat treatment, amorphous ferroelectric material film120 may be converted into a crystalline ferroelectric film 122. In one embodiment, the grain size of ferroelectric film 122 may be substantially the same as the grain size of crystallization seed film 130. For example, as shown in fig. 5, the average size W of the crystal grains F120F of the ferroelectric film 122 2F Can be equal to the average size W of the grains G120f of the crystallization seed film 130 2G Substantially the same.
Referring to fig. 6, the crystallization seed film 130 of fig. 5 may be removed to expose the ferroelectric film 122. In one embodiment, the crystallization seed film 130 may be removed using an etching method or a polishing method. In one particular embodiment, when crystallization seed film 130 is a polysilicon film, the polysilicon film may be oxidized to convert to a silicon oxide film, which may then be etched to expose ferroelectric film 122. For example, a wet etching method using an etching solution such as hydrofluoric acid or a buffer oxide etchant may be performed to remove the crystallization seed film 130.
Referring to fig. 7, an electrode film 140 may be formed on the ferroelectric film 122. The electrode film 140 may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The electrode film 140 may be formed using a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, or the like.
Referring to fig. 8, the electrode film 140, the ferroelectric film 122, and the interface insulating film 110 may be patterned. As a result, the interface insulating layer 115, the ferroelectric layer 125, and the gate electrode layer 145, which are sequentially stacked over the substrate 101, can be formed. In addition, dopants may be selectively implanted into regions of the substrate 101 exposed due to the patterning process. In one embodiment, ion implantation (I 2 ) The method implants dopants. As a result, the source region 150 and the drain region 160 may be formed in exposed regions of the substrate 101 at both ends or opposite sides of the gate electrode layer 145.
By performing the above-described processes described with reference to fig. 3 to 8, a ferroelectric device according to an embodiment of the present disclosure may be manufactured. In some embodiments, ferroelectric film 122 and crystallization seed film 130 shown in fig. 5 may have different lattice constants. For example, when the ferroelectric film 122 includes hafnium oxide (HfO 2 ) When hafnium oxide(HfO 2 ) Has about
Is a lattice constant of (c). At this time, the crystallization seed film 130 may include silicon carbide (SiC), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. Silicon carbide (SiC) has a composition of about +.>
Is a lattice constant of (2); silicon (Si) has about->
Is a lattice constant of (2); germanium (Ge) has about
Is a lattice constant of (2); silicon germanium (SiGe) has a lattice constant between that of silicon (Si) and germanium (Ge).
During the crystallization heat treatment for the ferroelectric material film 120, lattice stress may be generated at the interface between the ferroelectric film 122 and the crystallization seed film 130 due to the difference in lattice constant of the ferroelectric film 122 and the crystallization seed film 130. The lattice stress may create a gradient from the interface of ferroelectric film 122 and crystallization seed film 130 to the lattice stress in ferroelectric film 122. The gradient of lattice stress may create a flexoelectric effect in ferroelectric film 122, thereby creating an electric field within ferroelectric film 122. The electric field formed within the ferroelectric film 122 can improve polarization alignment in the ferroelectric film 122, thereby stabilizing ferroelectric characteristics of the ferroelectric film 122. Ferroelectric properties may include remnant polarization, coercive electric field, and the like.
Fig. 9 is a sectional view schematically showing a ferroelectric device 2 according to another embodiment of the present disclosure. Referring to fig. 9, ferroelectric device 2 may include a substrate 201, an interface insulating layer 215, a crystallization seed layer 225, a ferroelectric layer 235, and a gate electrode layer 245. In one embodiment, ferroelectric device 2 may be a transistor-type memory device that achieves different channel resistances depending on the polarization direction written into ferroelectric layer 235.
The configuration of ferroelectric device 2 may be substantially the same as the configuration of ferroelectric device 1 described above with reference to fig. 1, except that a crystallization seed layer 225 is added between interface insulating layer 215 and ferroelectric layer 235. More specifically, the substrate 201, channel region 205, interface insulating layer 215, ferroelectric layer 235, gate electrode layer 245, source region 250, and drain region 260 of ferroelectric device 2 may be substantially the same as the substrate 101, channel region 105, interface insulating layer 115, ferroelectric layer 125, gate electrode layer 145, source region 150, and drain region 160, respectively, of ferroelectric device 1. The write operation and the read operation of the ferroelectric device 2 may be substantially the same as the write operation and the read operation described above with reference to fig. 1. Therefore, the write operation and the read operation of the ferroelectric device 2 and the above components are not described in detail.
Referring to fig. 9, a crystallization seed layer 225 may be disposed on the interface insulating layer 215. The crystallization seed layer 225 may be a dielectric layer having a dielectric constant greater than that of the interfacial insulation layer 215. Unlike ferroelectric layer 235, crystallization seed layer 225 may not have ferroelectric properties. The crystallization seed layer 225 can include titanium oxide (e.g., tiO 2 ) Tantalum oxide (e.g. Ta 2 O 5 ) Aluminum oxide (e.g. Al 2 O 3 ) Strontium titanium oxide (e.g., srTiO 3 ) Barium titanium oxide (e.g. BaTiO 3 ) Yttrium titanium oxide (e.g., Y 2 Ti 2 O 7 ) Or a combination thereof.
The crystallization seed layer 225 may be formed to have a predetermined grain size. The crystallization seed layer 225 may have a thickness of about 1nm to about 10nm. The crystallization seed layer 225 may be used as a dielectric layer for a gate capacitor with the ferroelectric layer 235 and the interface insulating layer 215 between the substrate 201 and the gate electrode layer 245.
Fig. 10 is a flowchart schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
In step S210, a substrate may be prepared. The substrate may comprise a semiconductor material. For example, the substrate may be a p-type doped silicon substrate.
In step S220, a crystallization seed film may be formed over the substrate. The crystallization seed film may have a crystalline structure. The crystallization seed film may include a dielectric material. The crystallization seed film may be used as part of a gate dielectric layer in a fabricated ferroelectric device. Accordingly, in order to ensure a high dielectric constant of the gate dielectric layer, the crystallization seed film may be formed to have a sufficiently reduced thickness.
In one embodiment, the crystallization seed film may be formed as follows. First, a crystalline dielectric film having a predetermined grain size and a first thickness may be formed over a substrate. The crystalline dielectric film may then be etched or polished to reduce the first thickness to a second thickness that is less than the first thickness. As a result, the crystallization seed film may be formed as a crystallization dielectric film having a second thickness. The second thickness may be about 1nm to about 10nm.
The crystallization seed film may include titanium oxide (e.g., tiO 2 ) Tantalum oxide (e.g. Ta 2 O 5 ) Aluminum oxide (e.g. Al 2 O 3 ) Strontium titanium oxide (e.g., srTiO 3 ) Barium titanium oxide (e.g. BaTiO 3 ) Yttrium titanium oxide (e.g., Y 2 Ti 2 O 7 ) Or a combination thereof. In one embodiment, the crystallization seed film may be an aluminum oxide film.
In step S230, an amorphous ferroelectric material film may be formed on the crystallization seed film. The ferroelectric material film may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The ferroelectric material film may further include a dopant. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or a combination thereof. In one embodiment, the ferroelectric material film may be a hafnium oxide layer into which silicon (Si) is implanted as a dopant. In another embodiment, the ferroelectric material film may be an undoped hafnium oxide layer.
In step S240, a heat treatment may be performed on the ferroelectric material film and the crystallization seed film to form a crystallization ferroelectric film. In one embodiment, the heat treatment for the ferroelectric material film may be performed in a state where the crystallization seed film and the ferroelectric material film are in contact with each other. Thus, in the heat treatment process The medium crystallization seed film may cause crystallization of the amorphous ferroelectric material film. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Performed in a gaseous atmosphere of argon (Ar), or a combination thereof. The heat treatment may be performed at a temperature of about 500 ℃ to about 1000 ℃.
In one embodiment, the grain size of the crystalline ferroelectric film produced by the heat treatment may be substantially the same as the grain size of the crystallization seed film. Accordingly, a crystallization seed film may be formed in step S220 by taking into consideration the grain size of the crystalline ferroelectric film, and the grain size of the crystalline ferroelectric film may be controlled by heat treatment in step S240.
In step S250, an electrode film may be formed on the crystalline ferroelectric film. The electrode film may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.
Although not shown in fig. 10, a process of patterning the electrode film, the crystalline ferroelectric film, and the crystallization seed film may also be performed. As a result, a crystallization seed layer, a ferroelectric layer, and a gate electrode layer can be formed on the substrate. In addition, a process of selectively implanting dopants into regions of the substrate exposed due to the patterning process may be performed. As a result, the source and drain regions may be formed in the exposed regions of the substrate at both ends or opposite sides of the gate electrode layer.
In some other embodiments, before step S220, an interface insulating film may be formed on the substrate such that the interface insulating film is disposed between the substrate and the crystallization seed film. The interface insulating film may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). Subsequently, after steps S230 to S250 are performed, the interface insulating film, the crystallization seed film, the crystallization ferroelectric film, and the electrode film sequentially stacked over the substrate may be patterned to form an interface insulating layer, a crystallization seed layer, a ferroelectric layer, and a gate electrode layer.
By performing the above-described process, a ferroelectric device is manufactured. In some embodiments, the crystallization seedsThe film may have a lattice constant different from that of the ferroelectric film. For example, when the ferroelectric film has hafnium oxide (HfO 2 ) When the hafnium oxide has about
Is a lattice constant of (c). At this time, the crystallization seed film may include silicon carbide (SiC), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. Silicon carbide (SiC) has a composition of about +.>
Is a lattice constant of (2); silicon (Si) has about->
Is a lattice constant of (2); germanium (Ge) has a concentration of about->
Is a lattice constant of (2); silicon germanium (SiGe) has a lattice constant between that of silicon (Si) and germanium (Ge).
Therefore, in the crystallization heat treatment process of step S240, lattice stress may be generated in the crystalline ferroelectric film in which crystallization is performed due to the difference in lattice constants of the ferroelectric film and the crystallization seed film. In particular, the lattice stress may create a gradient from the interface between the ferroelectric film and the crystallization seed film to the lattice stress in the ferroelectric film. The gradient of lattice stress may create a flexoelectric effect in the ferroelectric film, thereby creating an electric field within the ferroelectric film. Therefore, the electric field formed within the ferroelectric film can improve polarization alignment in the ferroelectric film, thereby stabilizing the ferroelectric characteristics of the ferroelectric film. Ferroelectric properties may include remnant polarization, coercive electric field, etc.
Fig. 11 to 17 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure. Referring to fig. 11, a substrate 201 may be prepared. The substrate 201 may comprise a semiconductor material. The substrate 201 may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. In one embodiment, the substrate 201 may be doped to have conductivity. For example, the substrate 201 may be doped with a p-type or n-type dopant. In one embodiment, the substrate 201 may be a p-type doped silicon substrate.
Next, an interface insulating film 210 may be formed over the substrate 201. The interface insulating film 210 may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). The interface insulating film 210 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like. The interface insulating film 210 may be formed in an amorphous state. The interface insulating film 210 may have a thickness of about 1nm to about 5 nm.
Then, a crystalline dielectric film 220 having a predetermined grain size and a predetermined thickness may be formed on the interface insulating film 210. At this time, the grain size may represent a grain width measured in a lateral direction parallel to the top surface of the substrate 201. The dielectric film 220 may have a dielectric constant greater than that of the interface insulating film 210. Dielectric film 220 may include titanium oxide (e.g., tiO 2 ) Tantalum oxide (e.g. Ta 2 O 5 ) Aluminum oxide (e.g. Al 2 O 3 ) Strontium titanium oxide (e.g., srTiO 3 ) Barium titanium oxide (e.g. BaTiO 3 ) Yttrium titanium oxide (e.g., Y 2 Ti 2 O 7 ) Or a combination thereof. The dielectric film 220 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like.
Referring to fig. 12, the thickness of the dielectric film 220 may be reduced to form a crystallization seed film 222. The crystallization seed film 222 may have the same grain size as that of the dielectric film 220.
Fig. 13A and 13B are cross-sectional views schematically illustrating a process of forming a crystallization seed film 222 from a dielectric film 220 according to one embodiment of the present disclosure. For convenience of description, the substrate 201 is omitted in fig. 13A and 13B.
Referring to fig. 13A, a crystalline dielectric film 220 may be formed on the interface insulating film 210 and have a desired predetermined grain size. Performing formation of the crystalline dielectric film 2 in a first period of time20. The dielectric film 220 may have a grain size proportional to a thickness of the dielectric film 220. For example, FIG. 13A shows a dielectric film 220 having a first width W as a desired predetermined grain size a And has a first thickness T a 。
Referring to fig. 13B, the dielectric film 220 may be etched or ground to form a film having a thickness T greater than the first thickness T a A second smaller thickness T b Is provided, the seed film 222 is crystallized. The crystallization seed film 222 may have a thickness of about 1nm to about 10 nm. The crystallization seed film 222 may have the same width as that of the dielectric film 220. That is, the crystallization seed film 222 may have the same grain size as that of the dielectric film 220.
As shown in fig. 13A, has a first thickness T a The dielectric film 220 of (1) may include a first width W a Grain G220 of the average size of (a). As shown in fig. 13B, has a second thickness T b The crystallization seed film 222 of (1) may include a film having a first width W a Grain G222 of the average size of (a).
In one embodiment, referring to fig. 11 and 12, crystallization seed film 222 may be formed as follows. First, an initial thickness of the dielectric film 220 that can ensure a grain size of the crystallization seed film 222 can be determined. Next, by controlling the conditions of the film deposition process, the dielectric film 220 may be formed to have an initial thickness. Methods of controlling the film deposition process may include controlling process temperature, process time, process pressure, and the like. Then, the final thickness of the crystallization seed film 222 may be determined in consideration of the gate capacitance of the ferroelectric device. Subsequently, at least a portion of the dielectric film 220 may be removed to reduce the thickness, so that the crystallization seed film 222 having a final thickness may be formed. The thickness of the dielectric film 220 may be reduced using an etching method or a grinding method. The etching method may be a dry etching method, a wet etching method, or a combination thereof. The grinding method may be a chemical mechanical polishing method. As shown in fig. 12, a crystallization seed film 222 having a final thickness may be formed on the interface insulating film 210.
Referring to fig. 14, ferroelectric material may be formed on crystallization seed film 222A membrane 230. The ferroelectric material film 230 may be formed in an amorphous state. In one embodiment, the ferroelectric material film 230 may include a binary metal oxide. For example, the ferroelectric material film 230 may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The ferroelectric material film 230 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like.
In one embodiment, the ferroelectric material film 230 may include at least one dopant. The dopant may be uniformly distributed in the ferroelectric material film 230. For example, when the ferroelectric material film 230 includes hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or combinations thereof, the ferroelectric material film 230 may also include dopants having a valence of 2 to 4. After the ferroelectric material film 230 is crystallized, the dopant may function to stably maintain the ferroelectric property of the ferroelectric material film 230. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or combinations thereof. In one embodiment, the dopant may be provided with the source chemical material of the ferroelectric material film 230 when forming the ferroelectric material film 230. In another embodiment, the dopant may be implanted into the ferroelectric material film 230 by an ion implantation method after the formation of the ferroelectric material film 230 is completed.
Referring to fig. 15, the heat treatment may be performed in a state where the ferroelectric material film 230 covers the crystallization seed film 222. Crystallization of the seed film 222 may cause crystallization of the amorphous ferroelectric material film 230 during the heat treatment process. For example, the heat treatment may be performed at a process temperature of about 500 ℃ to about 1000 ℃. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Performed in a gaseous atmosphere of argon (Ar), or a combination thereof.
By performing heat treatment, the amorphous ferroelectric material film 230 can be converted into a crystalline ferroelectric film 232. In one embodiment, the grain size of ferroelectric film 232 after heat treatment may be substantially the same as the grain size of crystallization seed film 222.
Referring to fig. 16, an electrode film 240 may be formed on the ferroelectric film 232. The electrode film 240 may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The electrode film 240 may be formed using a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, or the like.
Referring to fig. 17, the electrode film 240, the ferroelectric film 232, the crystallization seed film 222, and the interface insulating film 210 may be patterned. As a result, the interface insulating layer 215, the crystallization seed layer 225, the ferroelectric layer 235, and the gate electrode layer 245, which are stacked over the substrate 201, can be formed. Thereafter, dopants may be selectively implanted into the regions of the substrate 101 exposed due to the patterning process. In one embodiment, ion implantation (I 2 ) The method implants dopants. As a result, the source region 250 and the drain region 260 may be formed in exposed regions of the substrate 201 at both ends or opposite sides of the gate electrode layer 245.
By performing the above-described process, a ferroelectric device according to an embodiment of the present disclosure can be manufactured. In some embodiments, the crystallization seed film 222 and the ferroelectric film 232 shown in fig. 15 may have different lattice constants. For example, when the ferroelectric film 232 includes hafnium oxide (HfO 2 ) When hafnium oxide (HfO) 2 ) Has about
Is a lattice constant of (c). At this time, the crystallization seed film 222 may include silicon carbide (SiC), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. Silicon carbide (SiC) has a composition of about +.>
Is a lattice constant of (2); silicon (Si) has about->
Is a lattice constant of (2); germanium (Ge) has a concentration of about->
Is a lattice constant of (2); silicon germanium (SiGe) has a crystal between the lattice constant of silicon (Si) and that of germanium (Ge)Lattice constant.
Accordingly, during the heat treatment for the ferroelectric material film 230, lattice stress may be generated at the interface between the crystallized ferroelectric film 232 and the crystallization seed film 222 due to the difference in lattice constants of the ferroelectric film 232 and the crystallization seed film 222. The lattice stress may create a gradient from the interface of ferroelectric film 232 and crystallization seed film 222 to the lattice stress in ferroelectric film 232. The gradient of lattice stress may create a flexoelectric effect in ferroelectric film 232, thereby creating an electric field within ferroelectric film 232. The electric field formed within the ferroelectric film 232 may improve polarization alignment in the ferroelectric film 232, thereby stabilizing ferroelectric characteristics of the ferroelectric film 232. Ferroelectric properties may include remnant polarization, coercive electric field, etc.
Fig. 18 is a sectional view schematically showing a ferroelectric device 3 according to another embodiment of the present disclosure. Referring to fig. 18, the ferroelectric device 3 may include a substrate 301, an interface insulating layer 315, a ferroelectric layer 325, and a gate electrode layer 345. In one embodiment, ferroelectric device 3 may be a transistor-type memory device that achieves different channel resistances depending on the polarization direction written into ferroelectric layer 325.
The configuration of ferroelectric device 3 may be substantially the same as the configuration of ferroelectric device 1 described above with reference to fig. 1, except for the configuration of ferroelectric layer 325. More specifically, the substrate 301, channel region 305, interface insulating layer 315, gate electrode layer 345, source region 350, and drain region 360 of the ferroelectric device 3 may be substantially the same as the substrate 101, channel region 105, interface insulating layer 115, gate electrode layer 145, source region 150, and drain region 160, respectively, of the ferroelectric device 1. The write operation and the read operation of the ferroelectric device 3 may be substantially the same as the write operation and the read operation of the ferroelectric device 1 described above with reference to fig. 1. Therefore, the write operation and the read operation of the ferroelectric device 3 and the above components are not described in detail.
Referring to fig. 18, the ferroelectric layer 325 may include nano-sized grains. In ferroelectric layer 325 containing nano-sized grains, the average size of the grains is smaller than the thickness of ferroelectric layer 325. For example, the ferroelectric layer 325 may have a thickness of about 3nm to about 15nm, and the average grain size of the ferroelectric layer 325 may be smaller than the thickness of the ferroelectric layer 325.
Fig. 19 is a graph schematically illustrating ferroelectric characteristics of a ferroelectric layer according to grain sizes according to one embodiment of the present disclosure. More specifically, the first curve 1810 and the second curve 1820 are hysteresis curves showing polarization characteristics of the first ferroelectric layer and the second ferroelectric layer having different grain sizes, respectively. The grain size of the second ferroelectric layer corresponding to the second curve 1820 is smaller than the grain size of the first ferroelectric layer corresponding to the first curve 1810.
Referring to FIG. 19, the coercive electric field E of the second curve 1820 c2 and-E c2 The magnitudes of (a) are respectively smaller than the coercive electric field E of the first curve 1810 c1 and-E c1 Is a function of the amplitude of (a). When an external electric field is applied to the ferroelectric layer, the magnitude of the coercive electric field formed in the ferroelectric layer may be proportional to the ability to resist polarization conversion (polarization switching). Thus, when an external electric field of the same magnitude is applied to the first ferroelectric layer and the second ferroelectric layer, the coercive electric field E is smaller than that of the first ferroelectric layer c2 and-E c2 May have a faster driving speed for polarization conversion than the first ferroelectric layer. In addition, polarization conversion can be performed in a relatively low electric field. As a result, by employing the ferroelectric layer 325 including nano-sized grains, the polarization conversion speed of the ferroelectric device can be increased. As a result, the writing operation speed of the ferroelectric element can be improved.
According to one embodiment of the present disclosure, nano-sized grains may be obtained by controlling the concentration of dopants doped in the ferroelectric layer 325 or by controlling the conditions of the heat treatment for the ferroelectric layer 325. In one embodiment, ferroelectric layer 325 may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or combinations thereof.
Fig. 20 is a diagram illustrating a crystal structure of a ferroelectric layer according to a dopant concentration and a subsequent heat treatment in one embodiment of the present disclosure. Specifically, in the present embodiment, titanium nitride with a thickness of 10nm is usedA (TiN) layer as a lower electrode; hafnium oxide doped with amorphous silicon having a thickness of 8nm (Si: hfO) 2 ) The layer is used as a ferroelectric material layer; and a titanium nitride (TiN) layer of 10nm thickness was used as the upper electrode. Titanium nitride (TiN) layer, amorphous silicon doped hafnium oxide (Si: hfO) 2 ) The layer and titanium nitride (TiN) layer are laminated and then under nitrogen (N) 2 ) A post-annealing process is performed on the laminated layers in an atmosphere. The degree of crystallization of the hafnium oxide layer was measured by varying the content of silicon doped in the hafnium oxide layer and the annealing temperature.
Referring to fig. 20, based on reference line R f The presence of a crystalline hafnium oxide layer at reference line R is observed f An amorphous hafnium oxide layer is present on the reference line R f Below. In this embodiment, conditions exist near the reference line Rf to produce a hafnium oxide layer with nano-sized grains less than 8 nm. That is, as shown in fig. 20, at the boundary between the crystalline hafnium oxide layer and the amorphous hafnium oxide layer, a hafnium oxide layer having nano-sized grains is formed by controlling the silicon dopant content and the post-annealing temperature.
Fig. 21 and 22 are graphs showing polarization changes according to an electric field application time according to an embodiment of the present disclosure.
Fig. 21 shows the test results of the laminated structure of a 10nm thick titanium nitride layer, an 8nm thick silicon-doped hafnium oxide layer, and a 10nm thick titanium nitride layer formed under the conditions of a silicon (Si) dopant content of 4.2mol% and a post heat treatment temperature of 600 c, corresponding to the point a in fig. 20.
Fig. 22 shows the test results of the laminated structure of a 10 nm-thick titanium nitride layer, a 10 nm-thick silicon-doped hafnium oxide layer, and a 10 nm-thick titanium nitride layer formed under the conditions of a silicon (Si) dopant content of 5.7mol% and a post heat treatment temperature of 600 c, corresponding to the point B in fig. 20.
More specifically, when the applied electric field is fixed, a polarization change Δp according to the application time t is observed. In fig. 21 and 22, the Y-axis represents the polarization change Δp divided by twice the saturated polarization Ps, so that the polarization change Δp is represented as a ratio with respect to the maximum variable amount, and the X-axis represents the logarithmic value of time.
Referring to fig. 21 and 22, in each graph, it can be seen that as the magnitude (MV/cm) of the applied electric field increases, the polarization change Δp increases at a certain time. It can also be seen that the time required for polarization switching to reach saturation becomes faster as the magnitude (MV/cm) of the applied electric field increases.
However, when comparing fig. 22 with fig. 21, when the hafnium oxide layer has the B-point condition, it can be determined that the polarization change Δp is relatively large at the initial application time of the electric field as shown in fig. 22. That is, it can be determined that the polarization conversion speed is fast. As a result of practical observation of the structure, the B-site condition satisfies the requirement for the ferroelectric layer having nano-sized grains more reliably than the a-site condition.
In one embodiment of the present disclosure, the ferroelectric layer 325 of fig. 18 may have a thickness of about 3nm to about 15 nm. Ferroelectric layer 325 may include about 4mol% to about 6mol% dopant. In addition, the ferroelectric layer 325 may be deposited as an amorphous ferroelectric material layer and then crystallized to have nano-sized grains by performing a heat treatment at about 500 ℃ to about 1000 ℃.
Fig. 23 is a flowchart schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure.
In step S310, a substrate may be prepared. The substrate may comprise a semiconductor material. For example, the substrate may be a p-type doped silicon substrate.
In step S320, a ferroelectric material film doped with a dopant may be formed on the substrate. The ferroelectric material film may have an amorphous structure. The ferroelectric material film may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The ferroelectric material film may further include a dopant. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), lanthanum (La), or combinations thereof. The ferroelectric material film may be formed using a chemical vapor deposition method or an atomic layer deposition method.
In step S330, an electrode film may be formed on the ferroelectric material film. The electrode film may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.
In step S340, a heat treatment may be performed on the ferroelectric material film to form a ferroelectric film including nano-sized grains. In one embodiment, the heat treatment may be performed in a state where the electrode film covers the ferroelectric material film. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Performed in a gaseous atmosphere of argon (Ar), or a combination thereof. The heat treatment may be performed at a temperature of about 500 ℃ to about 1000 ℃.
Although not shown in fig. 23, after performing the heat treatment, a process of patterning the electrode film and the ferroelectric film may be further performed. As a result, a ferroelectric layer and a gate electrode layer can be formed on the substrate. In addition, a process of selectively implanting dopants into the regions of the substrate exposed due to the patterning process may be further performed. As a result, the source and drain regions may be formed in the exposed regions of the substrate at both ends or opposite sides of the gate electrode layer.
In some other embodiments, before step S320, an interface insulating film may be formed on the substrate before forming the ferroelectric material film. The interface insulating film may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). Then, after steps S330 and S340 are performed, the interface insulating film, the ferroelectric film, and the electrode film sequentially stacked on the substrate may be patterned to form an interface insulating layer, a ferroelectric layer, and a gate electrode layer. By performing the above-described process, a ferroelectric device according to an embodiment of the present disclosure is manufactured.
Fig. 24 to 26 are sectional views schematically illustrating a method of manufacturing a ferroelectric device according to another embodiment of the present disclosure. Referring to fig. 24, a substrate 301 may be prepared. The substrate 301 may comprise a semiconductor material. The substrate 301 may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. The substrate 301 may be doped to have conductivity. For example, the substrate 301 may be doped with a p-type or n-type dopant. In one embodiment, substrate 301 may be a p-type doped silicon substrate.
Next, an interface insulating film 310 may be formed over the substrate 301. The interface insulating film 310 may include silicon oxide (e.g., siO 2 ) Silicon nitride (e.g., si 3 N 4 ) Silicon oxynitride (e.g., siON) or aluminum oxide (e.g., al 2 O 3 ). The interface insulating film 310 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like. The interface insulating film 310 may be formed in an amorphous state. The interface insulating film 310 may have a thickness of about 1nm to about 5 nm.
Then, a ferroelectric material film 320 may be formed on the interface insulating film 310. The ferroelectric material film 320 may be formed in an amorphous state. In one embodiment, ferroelectric material film 320 may comprise a binary metal oxide. For example, ferroelectric material film 320 may include hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or a combination thereof. The ferroelectric material film 320 may be formed using a chemical vapor deposition method, an atomic layer deposition method, or the like. The ferroelectric material film 320 may have a thickness of about 3nm to about 15 nm.
In one embodiment, the ferroelectric material film 320 may include at least one dopant. The dopant may be uniformly distributed in the ferroelectric material film 320. For example, when the ferroelectric material film 320 includes hafnium oxide (e.g., hfO 2 ) Zirconium oxide (e.g. ZrO 2 ) Or combinations thereof, the ferroelectric material film 320 may also include dopants having a valence of 2 to 4. After the ferroelectric material film 320 is crystallized, the dopant may function to stably maintain the ferroelectric property of the ferroelectric material film 320. The dopant may include carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), or combinations thereof. In one embodiment, the dopant may be provided with the source chemical material of the ferroelectric material film 320 when forming the ferroelectric material film 320. In another embodiment, the dopant may be implanted into the ferroelectric material film 320 by an ion implantation method after the formation of the ferroelectric material film 320 is completed. Dopants may be implanted into the ferroelectric material film 320 in an amount of about 4mol% to about 6 mol%.
Subsequently, an electrode film 340 may be formed on the ferroelectric material film 320. The electrode film 340 may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. The electrode film 340 may be formed using a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, or the like.
Referring to fig. 25, a heat treatment may be performed on the ferroelectric material film 320 to form a ferroelectric film 322 including nano-sized grains. In one embodiment, the heat treatment for the ferroelectric material film 320 may be performed in a state where the electrode film 340 covers the ferroelectric material film 320. The heat treatment may be performed in a system containing nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Performed in a gaseous atmosphere of argon (Ar), or a combination thereof. The heat treatment may be performed at a temperature of about 500 ℃ to about 1000 ℃.
Referring to fig. 26, the electrode film 340, the ferroelectric film 322, and the interface insulating film 310 may be patterned. As a result, the interface insulating layer 315, the ferroelectric layer 325, and the gate electrode layer 345, which are sequentially stacked over the substrate 301, can be formed. Thereafter, dopants may be selectively implanted into regions of the substrate 301 exposed due to the patterning process. In one embodiment, the dopant implantation process may be performed by ion implantation (I 2 ) The method is performed. As a result, the source region 350 and the drain region 360 may be formed in exposed regions of the substrate 301 at both ends or opposite sides of the gate electrode layer 345. By performing the above-described process, a ferroelectric device according to an embodiment of the present disclosure can be manufactured. According to this embodiment, by employing the ferroelectric layer including nano-sized grains, the polarization conversion speed of the ferroelectric device can be improved. As a result, the writing operation speed of the ferroelectric device can be improved.
The foregoing description of embodiments of the inventive concept has been presented for the purpose of illustration. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concepts disclosed in the accompanying claims.
Claims (16)
1. A method of fabricating a ferroelectric device, the method comprising:
providing a substrate;
forming a film of amorphous ferroelectric material over the substrate;
forming a crystallization seed film having a crystallization structure over the amorphous ferroelectric material film;
heat-treating the amorphous ferroelectric material film to convert the amorphous ferroelectric material film into a crystalline ferroelectric film;
removing the crystallization seed film to expose the crystalline ferroelectric film; and
An electrode film is formed over the crystalline ferroelectric film,
wherein forming the crystallization seed film comprises:
determining that the grain size of the crystallized seed film is substantially the same as the grain size of the crystallized ferroelectric film after the heat treatment;
determining a thickness of the crystallization seed film corresponding to the determined grain size of the crystallization seed film; and
a film deposition process is performed to form the crystallized seed film having the determined grain size and thickness.
2. The method of claim 1, wherein the ferroelectric material film comprises hafnium oxide, zirconium oxide, or a combination thereof.
3. The method of claim 2, wherein the ferroelectric material film further comprises a dopant, and
the dopant includes one of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Ga), lanthanum (La), and combinations thereof.
4. The method of claim 1, wherein the crystallization seed film comprises one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), and combinations thereof.
5. The method of claim 1, wherein the crystallization seed film has a lattice constant that is different from a lattice constant of the crystalline ferroelectric film.
6. The method of claim 1, wherein the crystallization seed film is formed at a temperature lower than a crystallization temperature of the ferroelectric material film.
7. The method of claim 1, wherein the crystallization seed film is formed at a process temperature less than 500 ℃.
8. The method of claim 1, wherein the heat treatment of the ferroelectric material film is performed at a process temperature of 500 ℃ to 1000 ℃.
9. The method of claim 1, further comprising:
an interface insulating layer is formed between the substrate and the ferroelectric material film.
10. The method of claim 1, further comprising:
patterning the electrode film and the crystalline ferroelectric film to form a gate electrode layer and a ferroelectric layer over the substrate; and
dopants are selectively implanted into regions of the substrate exposed on opposite sides of the gate electrode layer relative to the gate electrode layer, thereby forming source and drain regions in the substrate.
11. A method of fabricating a ferroelectric device, the method comprising:
providing a substrate;
forming a crystallization seed film having a crystallization structure over the substrate;
forming an amorphous ferroelectric material film over the crystallization seed film;
Heat-treating the amorphous ferroelectric material film to convert the amorphous ferroelectric material film into a crystalline ferroelectric film; and
an electrode film is formed over the crystalline ferroelectric film,
wherein forming the crystallization seed film comprises:
determining that the grain size of the crystallized seed film is substantially the same as the grain size of the crystallized ferroelectric film after the heat treatment;
determining a thickness of the crystallization seed film corresponding to the determined grain size of the crystallization seed film; and
a film deposition process is performed to form the crystallized seed film having the determined grain size and thickness.
12. The method of claim 11, wherein forming the crystallization seed film comprises:
forming a dielectric film having a predetermined grain size and a first thickness over the substrate; and
at least a portion of the dielectric film is removed to reduce the first thickness of the dielectric film to a second thickness that is less than the first thickness.
13. The method of claim 12, wherein the second thickness of the dielectric film is 1nm to 10nm.
14. The method of claim 12, wherein the crystallization seed film comprises one of titanium oxide, tantalum oxide, aluminum oxide, strontium titanium oxide, barium titanium oxide, yttrium titanium oxide, and combinations thereof.
15. The method of claim 11, further comprising:
an interfacial insulating layer is formed between the substrate and the crystallization seed film.
16. The method of claim 11, further comprising:
patterning the electrode film, the crystalline ferroelectric film, and the crystallization seed film to form a gate electrode layer, a ferroelectric layer, and a crystallization seed layer over the substrate; and
dopants are selectively implanted into regions of the substrate exposed on opposite sides of the gate electrode layer relative to the gate electrode layer, thereby forming source and drain regions in the substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP6887307B2 (en) * | 2017-05-19 | 2021-06-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor devices |
| TWI780167B (en) * | 2018-06-26 | 2022-10-11 | 晶元光電股份有限公司 | Semiconductor substrate and semiconductor device |
| KR102597980B1 (en) * | 2018-07-26 | 2023-11-02 | 도쿄엘렉트론가부시키가이샤 | Method for forming ferroelectric hafnium zirconium-based film for semiconductor devices |
| US11177284B2 (en) | 2018-12-20 | 2021-11-16 | Sandisk Technologies Llc | Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same |
| US10700093B1 (en) | 2018-12-20 | 2020-06-30 | Sandisk Technologies Llc | Ferroelectric memory devices employing conductivity modulation of a thin semiconductor material or a two-dimensional charge carrier gas and methods of operating the same |
| US11107901B2 (en) * | 2019-04-03 | 2021-08-31 | Sandisk Technologies Llc | Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same |
| KR102247789B1 (en) | 2019-11-12 | 2021-05-03 | 울산과학기술원 | Dielectric layer, and memcapacitor manufactured comprising the same |
| KR102259923B1 (en) | 2019-11-15 | 2021-06-02 | 광주과학기술원 | Dielectric layer, memcapacitor manufactured comprising the same, cell array comprising the same, and manufacturing method of the same |
| CN110890272A (en) * | 2019-11-22 | 2020-03-17 | 中国科学院微电子研究所 | Preparation method of hafnium oxide based ferroelectric film |
| KR20210075727A (en) * | 2019-12-13 | 2021-06-23 | 삼성전자주식회사 | Film structure comprising Hafnium Oxide, Electronic device including the same and Method of manufacturing the same |
| US11107516B1 (en) | 2020-02-24 | 2021-08-31 | Sandisk Technologies Llc | Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same |
| US11171219B2 (en) * | 2020-03-20 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices |
| US11758737B2 (en) * | 2020-05-28 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ferroelectric memory device and method of forming the same |
| US11569382B2 (en) | 2020-06-15 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of fabricating the same |
| US11302529B2 (en) * | 2020-07-09 | 2022-04-12 | Taiwan Semiconductor Manufacturing Company Ltd. | Seed layer for ferroelectric memory device and manufacturing method thereof |
| US11706928B2 (en) * | 2020-10-30 | 2023-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device and method for fabricating the same |
| US11335702B1 (en) * | 2020-11-13 | 2022-05-17 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006216584A (en) * | 2005-02-01 | 2006-08-17 | Seiko Epson Corp | Manufacturing method of ferroelectric thin film, piezoelectric element, and ferroelectric memory |
| US20130323534A1 (en) * | 2012-06-04 | 2013-12-05 | Sae Magnetics (H.K.) Ltd. | Ferroelectric crystal film, electronic component, manufacturing method of ferroelectric crystal film, and manufacturing apparatus therefor |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100275726B1 (en) | 1997-12-31 | 2000-12-15 | 윤종용 | Ferroelectric memory device and fabrication method thereof |
| JP2002198496A (en) * | 2000-12-26 | 2002-07-12 | Seiko Epson Corp | Ferroelectric capacitor, manufacturing method therefor and ferroelectric memory device |
| JP4205565B2 (en) * | 2003-12-03 | 2009-01-07 | 株式会社アルバック | Thin film manufacturing method |
| KR100682934B1 (en) * | 2005-02-17 | 2007-02-15 | 삼성전자주식회사 | Information recording media using ferroelectric layer and method of manufacturing the same |
| US7816217B2 (en) * | 2005-12-22 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-step epitaxial process for depositing Si/SiGe |
| TWI354334B (en) * | 2006-09-29 | 2011-12-11 | Hynix Semiconductor Inc | Semiconductor device with bulb-type recessed chann |
| US8304823B2 (en) * | 2008-04-21 | 2012-11-06 | Namlab Ggmbh | Integrated circuit including a ferroelectric memory cell and method of manufacturing the same |
| JP2014053568A (en) * | 2012-09-10 | 2014-03-20 | Toshiba Corp | Ferroelectric memory and method of manufacturing the same |
| US9391162B2 (en) * | 2014-04-04 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel MOSFET with ferroelectric gate stack |
| JP6814915B2 (en) * | 2015-09-18 | 2021-01-20 | アドバンストマテリアルテクノロジーズ株式会社 | Ferroelectric memory and its manufacturing method, ferroelectric film and its manufacturing method |
| US10153155B2 (en) | 2015-10-09 | 2018-12-11 | University Of Florida Research Foundation, Incorporated | Doped ferroelectric hafnium oxide film devices |
| DE102015015854B4 (en) | 2015-12-03 | 2021-01-28 | Namlab Ggmbh | Integrated circuit with a ferroelectric memory cell and use of the integrated circuit |
| US20170345831A1 (en) * | 2016-05-25 | 2017-11-30 | Micron Technology, Inc. | Ferroelectric Devices and Methods of Forming Ferroelectric Devices |
| US10515857B2 (en) * | 2017-09-28 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor devices |
-
2018
- 2018-02-08 KR KR1020180015858A patent/KR102433290B1/en active IP Right Grant
- 2018-10-23 US US16/168,687 patent/US10804294B2/en active Active
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006216584A (en) * | 2005-02-01 | 2006-08-17 | Seiko Epson Corp | Manufacturing method of ferroelectric thin film, piezoelectric element, and ferroelectric memory |
| US20130323534A1 (en) * | 2012-06-04 | 2013-12-05 | Sae Magnetics (H.K.) Ltd. | Ferroelectric crystal film, electronic component, manufacturing method of ferroelectric crystal film, and manufacturing apparatus therefor |
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