CN110136765B - High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof - Google Patents
High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof Download PDFInfo
- Publication number
- CN110136765B CN110136765B CN201910411627.9A CN201910411627A CN110136765B CN 110136765 B CN110136765 B CN 110136765B CN 201910411627 A CN201910411627 A CN 201910411627A CN 110136765 B CN110136765 B CN 110136765B
- Authority
- CN
- China
- Prior art keywords
- channel mos
- mos transistor
- read
- circuit module
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
Abstract
An EEPROM sensitive reading and discharging circuit with high efficiency and low power consumption comprises a reading and discharging current source Is _ rd, a reading data signal enb _ rd, a BL bit line and an output end, and further comprises a common gate circuit module and a transmission gate circuit module; the common-gate circuit module comprises two common-source single-stage amplifiers connected in parallel: an N-channel MOS transistor NM1 and a P-channel MOS transistor PM 8; the transmission gate circuit module comprises a P-channel MOS transistor PM9 and an N-channel MOS transistor NM0 which are connected in series on a reading current path. The invention considers from the aspects of power consumption, chip area and data reading speed, greatly improves the product performance of the EEPROM without using complex circuits such as band gap reference, voltage comparator and the like, optimizes the product, reduces the power consumption, correspondingly saves the area, reduces the cost and obviously improves the competitiveness of the product in the market.
Description
Technical Field
The invention discloses an efficient low-power-consumption EEPROM sensitive read-discharge circuit and a working method thereof, belonging to the technical field of memory data reading.
Background
Most of traditional EEPROM sensitive reading and discharging circuits use a voltage comparator or a current comparator to detect the voltage or the current of a memory CELL, see the attached drawings 1, 2, 3 and 4, however, the two methods are accompanied by stable current and voltage generating circuits such as a current source, a band gap reference and the like, and further bring larger power consumption and larger area to a chip, raise the cost of the chip and reduce the product competitiveness.
In this regard, the art has developed a technical improvement over the two methods described above, and reference is made to the circuit shown in fig. 5, which is simpler than the first two methods: the whole circuit uses a reading current, a common grid single-stage amplifying circuit and a turnover threshold value of an inverter as a comparison voltage, but the defects of the improved circuit are obvious, namely, because a parasitic capacitor exists on a path from an EEPROM memory CELL to a reading and discharging current source, when the CELL state is cut off, namely, data 1 is read, a reading current source firstly charges the parasitic capacitor, when the charging voltage of the parasitic capacitor reaches the turnover threshold value (VDD/2 is adjustable) of the inverter, the reading and discharging circuit outputs the data 1, the charging time of the reading and discharging current to the parasitic capacitor obviously limits the reading time of the EEPROM, and along with the increase of the capacity of the EEPROM, the parasitic capacitor of the memory CELL can correspondingly increase, the speed of reading the data 1 is slower, and the data reading frequency can also obviously reduce; another disadvantage is that as the operating voltage of the EEPROM increases, the turn threshold VDD/2 of the sense inverter also increases, so that when reading data "1", the time to charge to the turn threshold increases, and the read time increases, and importantly, when the charging voltage reaches the VDD/2 turn threshold, a punch-through current is formed in the sense inverter, which increases the power consumption of the EEPROM and causes unnecessary energy waste, which are all problems that need to be avoided as much as possible in the design.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses an EEPROM sensitive read-discharge circuit with high efficiency and low power consumption. The read-discharge circuit simplifies the circuit structure and solves the problems of power consumption, module area and read-discharge speed of a chip read-discharge module.
The invention also discloses a working method of the reading and discharging circuit.
The technical scheme of the invention is as follows:
an EEPROM sensitive reading and discharging circuit with high efficiency and low power consumption comprises a reading and discharging current source Is _ rd, a reading data signal enb _ rd, a BL bit line and an output end, and Is characterized by further comprising a common gate circuit module and a transmission gate circuit module; the common-gate circuit module comprises two common-source single-stage amplifiers connected in parallel: an N-channel MOS transistor NM1 and a P-channel MOS transistor PM 8; the transmission gate circuit module comprises a P-channel MOS transistor PM9 and an N-channel MOS transistor NM0 which are connected in series on a reading current path. According to the invention, the common-gate structure circuit is introduced into the read-discharge circuit, so that the bit line voltage flip threshold is reduced, and the threshold flip voltage of the common-gate circuit module can be ensured to be stable even if the power supply VDD fluctuates. In order to prevent punch-through current from being formed at the switching threshold of NM1 and PM8, a transmission gate formed by PM9 and NM0 is added to a read current path of a CELL, the grid electrode of a P-channel MOS tube PM9 is not connected with VSS, and is connected with the grid electrode of a P-channel MOS tube PM6, so that the resistance of a P-channel MOS tube PM9 is increased, namely when reading data 1, the grid voltage of the P-channel MOS tube PM8 is increased firstly, after the P-channel MOS tube PM8 is cut off, the grid voltage of an N-channel MOS tube NM1 reaches the switching threshold to turn on the NM1 tube, and therefore the situation that the PM8 and NM1 are turned on simultaneously to form the punch-through current and increase power consumption.
According to the invention, a voltage stabilizing circuit module is preferably arranged on a path of a read discharge current source of the read discharge circuit so as to reduce the discharge time of the read current to the parasitic capacitor of the CELL. This technique has the advantage of significantly improving the read data speed of the EEPROM.
According to a preferred embodiment of the present invention, the voltage regulating circuit module includes two diode-connected series N-channel MOS transistors NM3 and NM 4. When the EEPROM reads data 1, the drain ends of NM3 and NM4 have a stable voltage, the discharge time of read current to CELL parasitic capacitance is reduced, and the data reading speed of the EEPROM is obviously improved.
According to a preferred embodiment of the present invention, the read/discharge circuit further includes a switching circuit module including: a P-channel MOS transistor PM0, a P-channel MOS transistor PM1, a P-channel MOS transistor PM2 and a P-channel MOS transistor PM3 which are arranged in series between a read discharge current source Is _ rd and a power supply VDD; the P-channel MOS transistor PM0 is connected with a switch S2 in parallel, the P-channel MOS transistor PM1 is connected with a switch S1 in parallel, and the P-channel MOS transistor PM2 is connected with a switch S0 in parallel. The design has the advantages that the read discharge current source Is _ rd Is a read discharge current source provided for the whole read discharge circuit, the PM0, the PM1, the PM2 and the PM3 are mirror tubes for adjusting read discharge current, and proper current values of the PM6 and the PM7 can be obtained by adjusting the on-off of S0, S1 and S2 switching tubes, namely the most proper read discharge current parameters are determined, so that the optimal read discharge performance Is achieved with the minimum power consumption.
According to a preferred embodiment of the present invention, the switch circuit module is further connected to a filter circuit module. The design has the advantages that the resistor res and the capacitor cap are preferably selected to form a filter circuit, the grid voltage of the mirror tube is stabilized, and a better mirror matching effect is achieved. The capacitor cap in the circuit of the invention also has the function of starting the circuit, so that the reading and the amplifying can enter the working state more quickly.
According to the present invention, preferably, a register circuit module is further disposed at an output end of the read/discharge circuit, and the read/discharge data of the EEPROM at the address at that time is stored according to the read clock signal. When each read clock rdck arrives, the register stores read data of the EEPROM at the address until the next read clock arrives, and the design leaves sufficient time for data acquisition, thereby facilitating the design of the digital processing section.
The working method of the read-discharge circuit comprises the following steps: when the read discharge circuit starts to read data, a read data signal enb _ rd Is at a high level, a P-channel MOS transistor PM4 and a P-channel MOS transistor PM5 are turned on, an N-channel MOS transistor NM2 Is turned off, then the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 are turned on, and a read discharge current source Is _ rd Is mirrored to two paths of the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 through a P-channel MOS transistor PM3 in proportion, at this time, the read discharge circuit Is turned on: it is characterized in that the preparation method is characterized in that,
1) if the EEPROM CELL pointed by the read address is in the on state, the voltage on the BL bit line is close to 0, that is, the gate voltages of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are low, the P-channel MOS transistor PM8 is on, the input terminal of the inverter inv2 is at a high level, the D input terminal of the register DFF is at a low level, and when the read clock rdck changes to a high level, the register DFF outputs a low level, that is, reads out data "0"; until the next read clock rdck becomes high level, the output of the register DFF changes according to the data change of the input terminal, and the register DFF outputs data to hold one period of the read clock rdck;
2) if the memory CELL is in an off state, the parasitic capacitance of the memory CELL is charged by the read current on the BL bit line until the voltage on the BL bit line reaches a high level, and since the NM3 and NM4 transistors function as voltage stabilizing diodes, the charging time on the BL bit line is not prolonged due to the large storage capacity and the large parasitic capacitance, the charging time is fast, the gates of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are at a high level, the N-channel MOS transistor NM1 is turned on, the input end of the inverter inv2 is at a low level, the D input end of the register DFF is at a high level, and when the read clock rdck becomes at a high level, the register DFF outputs a high level, namely, the read data "1".
The technical advantages of the invention are as follows:
1. the invention considers from the aspects of power consumption, chip area and data reading speed, greatly improves the product performance of the EEPROM without using complex circuits such as band gap reference, voltage comparator and the like, optimizes the product, reduces the power consumption, correspondingly saves the area, reduces the cost and obviously improves the competitiveness of the product in the market.
2. The invention does not need functional modules such as a band gap reference, a current source, a voltage comparator, a current comparator and the like, obviously reduces the power consumption of the reading and discharging module by utilizing a cascode structure, a transmission gate and a diode circuit on the basis of a simple reading and discharging circuit as shown in figure 5, improves the reading and discharging speed, avoids the formation of through current, and also improves the market competitiveness of products.
3. The invention adds switches S0, S1 and S2, and can be replaced by mos tubes, so as to effectively adjust the size of read discharge current, and when the invention is applied specifically: in the manufacturing process of the chip, when process deviation occurs, various parameters (voltage, current, parasitic capacitance and resistance) in the circuit are deviated, and at the moment, the most suitable read-discharge current parameters can be determined by adjusting switches S0, S1 and S2, so that the optimal read-discharge performance is achieved with the minimum power consumption. The grid voltage of the mirror tube is stabilized by the filter circuit, a better mirror matching effect is achieved, and the capacitor cap also has the function of a starting circuit, so that reading and amplifying can enter a working state more quickly.
4. In order to collect read and play data conveniently, a register is added at the output end, when each read clock rdck arrives, the register can store the read and play data of the EEPROM at the address at the moment until the next read clock arrives, and the design leaves sufficient time for data collection, so that the design of a digital processing part is convenient.
Drawings
FIG. 1: a circuit schematic diagram of a read-discharge circuit using a voltage comparator in the prior art;
FIG. 2: the read discharge voltage comparator in the prior art;
FIG. 3: the read-and-discharge topology of current comparators in the prior art;
FIG. 4: differential current comparator structures in the prior art;
FIG. 5: a conventional read-discharge circuit schematic in the prior art;
FIG. 6: is a circuit schematic diagram of the read-discharge circuit of the invention.
Detailed Description
The invention is described in detail below with reference to the following examples and the accompanying drawings of the specification, but is not limited thereto.
Examples 1,
As shown in fig. 6.
An EEPROM sensitive reading and discharging circuit with high efficiency and low power consumption comprises a reading and discharging current source Is _ rd, a reading data signal enb _ rd, a BL bit line and an output end, and further comprises a common gate circuit module and a transmission gate circuit module; the common-gate circuit module comprises two common-source single-stage amplifiers connected in parallel: an N-channel MOS transistor NM1 and a P-channel MOS transistor PM 8; the transmission gate circuit module comprises a P-channel MOS transistor PM9 and an N-channel MOS transistor NM0 which are connected in series on a reading current path.
And a voltage stabilizing circuit module is arranged on a path of a read discharge current source of the read discharge circuit so as to reduce the discharge time of the read current to the parasitic capacitor of the memory CELL.
The voltage stabilizing circuit module comprises two diode-connected series-connection N-channel MOS tubes NM3 and NM 4.
The read-discharge circuit further comprises a switch circuit module, comprising: a P-channel MOS transistor PM0, a P-channel MOS transistor PM1, a P-channel MOS transistor PM2 and a P-channel MOS transistor PM3 which are arranged in series between a read discharge current source Is _ rd and a power supply VDD; the P-channel MOS transistor PM0 is connected with a switch S2 in parallel, the P-channel MOS transistor PM1 is connected with a switch S1 in parallel, and the P-channel MOS transistor PM2 is connected with a switch S0 in parallel.
The switch circuit module is also connected with a filter circuit module. Preferably, the resistor res and the capacitor cap form a filter circuit to stabilize the gate voltage of the mirror tube, so as to achieve a better mirror matching effect. The capacitor cap also has the function of a starting circuit, so that the reading and the amplifying can enter a working state more quickly.
And the output end of the read-discharge circuit is also provided with a register circuit module which stores read-discharge data of the EEPROM under the address at the moment according to the read clock signal. When the read clock rdck arrives, the register stores read data of the EEPROM at the address until the next read clock arrives.
The whole circuit of the invention has no complex voltage comparator, current comparator and the like, thus obviously reducing the power consumption and chip area of the EEPROM, reducing the cost and improving the product competitiveness; the circuit adopts two common-source single-stage amplifiers connected in parallel, namely NM1 and PM8 connected in parallel, namely the circuit principle of comparison by using an inverter threshold as a reference voltage as shown in figure 5. In addition, the NM1 and the PM8 are connected in parallel to utilize a common gate cascode structure, so that the bit line voltage flip threshold is reduced, and even if the power supply VDD fluctuates, the threshold flip voltages of the NM1 and the PM8 are stable; NM3, NM4, as the voltage regulator circuit, namely when EEPROM reads data "1", said drain terminal of NM3, NM4 will have a stable voltage, reduce the discharge time of the parasitic capacitance of CELL of the read current, improve the read data speed of EEPROM apparently; in order to prevent punch-through current from being formed at the switching threshold of NM1 and PM8, a transmission gate formed by PM9 and NM0 is added to a read current path of a CELL, the gate of the PM9 is not connected with VSS and is connected with the gate of PM6 so as to increase the resistance of PM9, namely when reading data 1, the gate voltage of PM8 is firstly increased, after PM8 is cut off, the gate voltage of NM1 reaches the switching threshold to turn on the NM1 tube, and therefore the situation that the punch-through current is formed when PM8 and NM1 are simultaneously turned on to increase power consumption is avoided.
Examples 2,
The method of operating a read discharge circuit as described in embodiment 1, comprising: when the read discharge circuit starts to read data, a read data signal enb _ rd Is at a high level, a P-channel MOS transistor PM4 and a P-channel MOS transistor PM5 are turned on, an N-channel MOS transistor NM2 Is turned off, then the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 are turned on, and a read discharge current source Is _ rd Is mirrored to two paths of the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 through a P-channel MOS transistor PM3 in proportion, at this time, the read discharge circuit Is turned on:
1) if the EEPROM CELL pointed by the read address is in the on state, the voltage on the BL bit line is close to 0, that is, the gate voltages of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are low, the P-channel MOS transistor PM8 is on, the input terminal of the inverter inv2 is at a high level, the D input terminal of the register DFF is at a low level, and when the read clock rdck changes to a high level, the register DFF outputs a low level, that is, reads out data "0"; until the next read clock rdck becomes high level, the output of the register DFF changes according to the data change of the input terminal, and the register DFF outputs data to hold one period of the read clock rdck;
2) if the memory CELL is in an off state, the parasitic capacitance of the memory CELL is charged by the read current on the BL bit line until the voltage on the BL bit line reaches a high level, and since the NM3 and NM4 transistors function as voltage stabilizing diodes, the charging time on the BL bit line is not prolonged due to the large storage capacity and the large parasitic capacitance, the charging time is fast, the gates of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are at a high level, the N-channel MOS transistor NM1 is turned on, the input end of the inverter inv2 is at a low level, the D input end of the register DFF is at a high level, and when the read clock rdck becomes at a high level, the register DFF outputs a high level, namely, the read data "1".
Although the present invention has been described with reference to specific examples, the description of the examples does not limit the scope of the present invention. Various modifications and combinations of the embodiments will be readily apparent to those skilled in the art, by reference to the description of the invention, without departing from the spirit and scope of the invention.
Claims (2)
1. An EEPROM sensitive reading and discharging circuit with high efficiency and low power consumption comprises a reading and discharging current source Is _ rd, a reading data signal enb _ rd, a BL bit line and an output end, and Is characterized by further comprising a common gate circuit module and a transmission gate circuit module; the common-gate circuit module comprises two common-source single-stage amplifiers connected in parallel: an N-channel MOS transistor NM1 and a P-channel MOS transistor PM 8; the transmission gate circuit module comprises a P-channel MOS transistor PM9 and an N-channel MOS transistor NM0 which are connected in series on a reading current path;
a voltage stabilizing circuit module is arranged on a path of a read discharge current source of the read discharge circuit to reduce the discharge time of read current to a storage CELL parasitic capacitor;
the voltage stabilizing circuit module comprises two diode-connected series N-channel MOS (metal oxide semiconductor) transistors NM3 and NM 4;
the read-discharge circuit further comprises a switch circuit module, comprising: a P-channel MOS transistor PM0, a P-channel MOS transistor PM1, a P-channel MOS transistor PM2 and a P-channel MOS transistor PM3 which are arranged in series between a read discharge current source Is _ rd and a power supply VDD; a switch S2 is connected in parallel to the P-channel MOS transistor PM0, a switch S1 is connected in parallel to the P-channel MOS transistor PM1, and a switch S0 is connected in parallel to the P-channel MOS transistor PM 2;
the switch circuit module is also connected with a filter circuit module;
and the output end of the read-discharge circuit is also provided with a register circuit module which stores read-discharge data of the EEPROM under the address at the moment according to the read clock signal.
2. The method of operating an EEPROM sensitive read-discharge circuit with high efficiency and low power consumption as claimed in claim 1, comprising: when the read discharge circuit starts to read data, a read data signal enb _ rd Is at a high level, a P-channel MOS transistor PM4 and a P-channel MOS transistor PM5 are turned on, an N-channel MOS transistor NM2 Is turned off, then the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 are turned on, and a read discharge current source Is _ rd Is mirrored to two paths of the P-channel MOS transistor PM6 and the P-channel MOS transistor PM7 through a P-channel MOS transistor PM3 in proportion, at this time, the read discharge circuit Is turned on: it is characterized in that the preparation method is characterized in that,
1) if the EEPROM CELL pointed by the read address is in the on state, the voltage on the BL bit line is close to 0, that is, the gate voltages of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are low, the P-channel MOS transistor PM8 is on, the input terminal of the inverter inv2 is at a high level, the D input terminal of the register DFF is at a low level, and when the read clock rdck changes to a high level, the register DFF outputs a low level, that is, reads out data "0"; until the next read clock rdck becomes high level, the output of the register DFF changes according to the data change of the input terminal, and the register DFF outputs data to hold one period of the read clock rdck;
2) if the memory CELL is in an off state, the parasitic capacitor of the memory CELL is charged by the read current on the BL bit line until the voltage on the BL bit line reaches a high level, the gates of the N-channel MOS transistor NM1 and the P-channel MOS transistor PM8 are at a high level, the N-channel MOS transistor NM1 is turned on, the input end of the inverter inv2 is at a low level, the D input end of the register DFF is at a high level, and when the read clock rdck changes to a high level, the register DFF outputs a high level, that is, reads out data "1".
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411627.9A CN110136765B (en) | 2019-05-17 | 2019-05-17 | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411627.9A CN110136765B (en) | 2019-05-17 | 2019-05-17 | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110136765A CN110136765A (en) | 2019-08-16 |
| CN110136765B true CN110136765B (en) | 2020-11-06 |
Family
ID=67574909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910411627.9A Active CN110136765B (en) | 2019-05-17 | 2019-05-17 | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110136765B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112489712B (en) * | 2020-12-21 | 2023-07-18 | 中国电子科技集团公司第四十七研究所 | EEPROM programming cycle control circuit |
| CN113053442B (en) * | 2021-03-18 | 2024-04-02 | 华南师范大学 | Low-power-consumption EEPROM memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1207561A (en) * | 1997-08-05 | 1999-02-10 | 冲电气工业株式会社 | Semiconductor memory device having constant voltage circuit |
| US6438051B1 (en) * | 2001-05-31 | 2002-08-20 | International Business Machines Corporation | Stabilized direct sensing memory architecture |
| CN102354520A (en) * | 2011-11-02 | 2012-02-15 | 上海宏力半导体制造有限公司 | Read amplifier with low power consumption |
| CN104795093A (en) * | 2015-04-21 | 2015-07-22 | 福州大学 | Low-power-consumption readout circuit based on folding comparator and control method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0936621B1 (en) * | 1998-02-13 | 2006-04-26 | STMicroelectronics S.r.l. | Improved sense amplifier for a non volatile memory with extended supply voltage range |
| JP2002109900A (en) * | 2000-09-28 | 2002-04-12 | Mitsubishi Electric Corp | Semiconductor device and testing method for semiconductor storage device |
| US7813167B2 (en) * | 2008-03-21 | 2010-10-12 | Micron Technology, Inc. | Memory cell |
| JP2009230798A (en) * | 2008-03-21 | 2009-10-08 | Toshiba Corp | Magnetic storage device |
-
2019
- 2019-05-17 CN CN201910411627.9A patent/CN110136765B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1207561A (en) * | 1997-08-05 | 1999-02-10 | 冲电气工业株式会社 | Semiconductor memory device having constant voltage circuit |
| US6438051B1 (en) * | 2001-05-31 | 2002-08-20 | International Business Machines Corporation | Stabilized direct sensing memory architecture |
| CN102354520A (en) * | 2011-11-02 | 2012-02-15 | 上海宏力半导体制造有限公司 | Read amplifier with low power consumption |
| CN104795093A (en) * | 2015-04-21 | 2015-07-22 | 福州大学 | Low-power-consumption readout circuit based on folding comparator and control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110136765A (en) | 2019-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110136765B (en) | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof | |
| US6373315B2 (en) | Signal potential conversion circuit | |
| EP0315385A2 (en) | Delay circuits for integrated circuits | |
| CN103066962B (en) | delay circuit | |
| KR20040106341A (en) | Single-ended current sense amplifier | |
| CN111934657B (en) | Low-power-consumption power-on reset and power-off reset circuit | |
| US8896277B2 (en) | Voltage regulator | |
| US9659607B2 (en) | Sense amplifier circuit and semiconductor memory device | |
| CN114441842A (en) | Zero-crossing detection circuit for peak current mode control Buck converter | |
| CN111181544A (en) | Input receiver circuit, method for intelligent optimization and semiconductor memory | |
| TWI262649B (en) | Low voltage differential amplifier circuit for wide voltage range operation | |
| CN102811041B (en) | A kind of Long-time-delay circuit | |
| US6707703B2 (en) | Negative voltage generating circuit | |
| CN102044299B (en) | Nonvolatile memory and reading circuit thereof | |
| CN109660236B (en) | Hysteresis circuit and power-on reset structure formed by same | |
| CN111404526A (en) | Programmable high-precision dynamic GaN driving circuit and application thereof | |
| CN208971484U (en) | Delay circuit | |
| CN109257024B (en) | Sensitive amplifier circuit | |
| CN113922662B (en) | Dual-hysteresis control charge pump energy collector based on maximum power point tracking | |
| JP4266364B2 (en) | Oscillator circuit | |
| CN217770032U (en) | Oscillator circuit applied to battery management chip | |
| CN102547529A (en) | Pop noise suppression circuit and system | |
| JP3047828B2 (en) | Comparator circuit | |
| CN113110684B (en) | Power supply voltage output integrated circuit for magnetic sensing | |
| JPH05234380A (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: An EEPROM sensitive reading and amplifier circuit with high efficiency and low power consumption and its working method Effective date of registration: 20230301 Granted publication date: 20201106 Pledgee: Bank of China Limited Jinan high tech sub branch Pledgor: SHANDONG HUAYI MICRO-ELECTRONICS Co.,Ltd. Registration number: Y2023370000046 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |