CN110136765A - A kind of sensitive sense amplifier circuit of EEPROM and its working method of efficient low-power consumption - Google Patents
A kind of sensitive sense amplifier circuit of EEPROM and its working method of efficient low-power consumption Download PDFInfo
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- CN110136765A CN110136765A CN201910411627.9A CN201910411627A CN110136765A CN 110136765 A CN110136765 A CN 110136765A CN 201910411627 A CN201910411627 A CN 201910411627A CN 110136765 A CN110136765 A CN 110136765A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
A kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption, including discharge stream source Is_rd, reading data signal enb_rd, BL bit line and output end are read, it further include common gate circuit module and transmission gate circuit module；The common gate circuit module includes two common source one-stage amplifiers in parallel: N-channel MOS pipe NM1 and P-channel metal-oxide-semiconductor PM8；The transmission gate circuit module includes the concatenated P-channel metal-oxide-semiconductor PM9 and N-channel MOS pipe NM0 on read current access.The present invention considers in all directions from power consumption, chip area, reading data speed, in the case where the complicated circuits such as band-gap reference, voltage comparator, the properties of product of EEPROM are greatly improved, and product can be optimized, reduce power consumption, it is corresponding to save area, cost is reduced, product competitiveness in the market is significantly improved.
Description
Technical field
The present invention discloses the sensitive sense amplifier circuit of EEPROM and its working method of a kind of efficient low-power consumption, belongs to memory number
According to the technical field of reading.
Background technique
The sensitive sense amplifier circuit of traditional EEPROM detects storage CELL using voltage comparator or current comparator mostly
Voltage or size of current, referring to attached drawing 1,2,3,4, however to be accompanied with current source, band-gap reference etc. steady for above two method
Fixed electric current, voltage generation circuit, and then bigger power consumption and bigger area can be come to chip belt, the cost of chip is raised,
Reduce product competitiveness.
In this regard, the art has carried out technological improvement to above two method, referring to attached circuit shown in fig. 5, phase
Simpler to the first two method: entire circuit is with a read current, a common gate single-stage amplifying circuit, a reverse phase
The turn threshold of device is as comparison voltage, but the shortcomings that improvement circuit is also obvious, i.e., since EEPROM storage CELL is arrived
It reads on the access in discharge stream source there are parasitic capacitance, so when data " 1 " is read in the cut-off of CELL state, read current source is first had to pair
Parasitic capacitance charging, when the charging voltage of parasitic capacitance reaches turn threshold (VDD/2 is adjustable) of phase inverter, sense amplifier circuit is
Meeting output data " 1 " reads discharge stream and clearly limits the reading data time of EEPROM to the charging time of parasitic capacitance, and
As the capacity of EEPROM increases, the parasitic capacitance for storing CELL can also be increased accordingly, and the speed for reading data " 1 " can be slower, number
It can also be significantly reduced according to read frequency；It has another disadvantage that as the operating voltage of EEPROM increases, reads the overturning of phase inverter
Threshold value VDD/2 also will increase, in this way, the time for being charged to turn threshold can increase when reading data " 1 ", read time increases,
And the important point, when charging voltage reaches VDD/2 turn threshold, reading will form punchthrough current on phase inverter, increase
The power consumption of EEPROM, causes unnecessary energy waste, and these problems require to avoid as far as possible when design.
Summary of the invention
In view of the deficiencies of the prior art, the present invention discloses a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption.This hair
The bright sense amplifier circuit solves that chip reads amplification module power consumption, speed is put in module area, reading while simplifying circuit structure
Problem.
The invention also discloses the working methods of above-mentioned sense amplifier circuit.
Technical scheme is as follows:
A kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption, including read discharge stream source Is_rd, reading data signal enb_
Rd, BL bit line and output end, which is characterized in that further include common gate circuit module and transmission gate circuit module；The common gate circuit
Module includes two common source one-stage amplifiers in parallel: N-channel MOS pipe NM1 and P-channel metal-oxide-semiconductor PM8；The transmission gate electricity
Road module includes the concatenated P-channel metal-oxide-semiconductor PM9 and N-channel MOS pipe NM0 on read current access.The present invention discharges in the reading
Common gate structure circuit is introduced in road, reduces bit-line voltage turn threshold, even if power vd D has fluctuation, also can guarantee the grid altogether
The threshold value turnover voltage of circuit module is stablized.Punchthrough current is formed in the turn threshold of NM1, PM8 in order to prevent, in the reading of CELL
Increase a transmission gate formed by PM9, NM0 on current path, the grid of P-channel metal-oxide-semiconductor PM9 does not meet VSS, meets P-channel MOS
The grid of pipe PM6, in order that increasing the resistance of P-channel metal-oxide-semiconductor PM9, i.e., when reading data " 1 ", the grid of P-channel metal-oxide-semiconductor PM8
Voltage first increases, and after P-channel metal-oxide-semiconductor PM8 cut-off, the grid voltage of N-channel MOS pipe NM1, which just reaches turn threshold, leads NM1 pipe
It is logical, it simultaneously turns on to form the case where punchthrough current increases power consumption so as to avoid PM8, NM1.
It is preferred according to the present invention, it is provided with voltage stabilizing circuit module on the access in the reading discharge stream source of sense amplifier circuit, with
Reduce read current to the discharge time of storage CELL parasitic capacitance.This technology is a little, significantly improves the reading data of EEPROM
Speed.
Preferred according to the present invention, the voltage stabilizing circuit module includes the series connection N-channel MOS pipe of two diode connection
NM3 and N-channel MOS pipe NM4.When EEPROM reads data " 1 ", the end drain of NM3, NM4 have a burning voltage, reduce
Read current significantly improves the reading data speed of EEPROM to the discharge time of CELL parasitic capacitance.
Preferred according to the present invention, the sense amplifier circuit further includes on-off circuit module, comprising: is reading discharge stream source Is_
P-channel metal-oxide-semiconductor PM0, P-channel metal-oxide-semiconductor PM1, the P-channel metal-oxide-semiconductor PM2, P-channel metal-oxide-semiconductor being arranged in series between rd and power vd D
PM3；It is parallel with switch S2 on the P-channel metal-oxide-semiconductor PM0, is parallel with switch S1, the P-channel on the P-channel metal-oxide-semiconductor PM1
Switch S0 is parallel on metal-oxide-semiconductor PM2.The advantages of designing herein is that reading discharge stream source Is_rd is provided for entire sense amplifier circuit
Reading discharge stream source, PM0, PM1, PM2, PM3 are to adjust the mirror image pipe for reading discharge stream, pass through and adjust the logical of S0, S1, S2 switching tube
Disconnected, the available suitable current value of PM6, PM7 determines most suitable reading discharge stream parameter, to reach with the smallest power consumption
Performance is put to optimal reading.
Preferred according to the present invention, the on-off circuit module is also connected with filter circuit module.The advantages of this design, exists
In preferably resistance res, capacitor cap form filter circuit in the present invention, stablize the grid voltage of mirror image pipe, reach better mirror
As matching effect.Capacitor cap also plays the role of start-up circuit in circuit in the present invention, makes to read to put faster to enter work shape
State.
It is preferred according to the present invention, it is additionally provided with register circuit module in the output end of the sense amplifier circuit, according to reading
Data are put in the reading that clock signal stores the EEPROM under address at this time.Each read clock rdck to when, register will
Data are put in the reading for storing the EEPROM under address at this time, and until next reading clock arrives, this design leaves data acquisition for fill
The abundant time, to realize the design for facilitating digital processing part.
The working method of above-mentioned sense amplifier circuit, comprising: when the sense amplifier circuit starts to read data, reading data signal enb_
Rd is high level, and P-channel metal-oxide-semiconductor PM4, P-channel metal-oxide-semiconductor PM5 are connected, N-channel MOS pipe NM2 cut-off, then P-channel metal-oxide-semiconductor
PM6, P-channel metal-oxide-semiconductor PM7 conducting, and there is reading discharge stream source Is_rd to pass through P-channel metal-oxide-semiconductor PM3 in proportion and be mirrored to P-channel
Metal-oxide-semiconductor PM6, P-channel metal-oxide-semiconductor PM7 two accesses on, at this point, the sense amplifier circuit function open: it is characterized in that,
1) if the EEPROM storage CELL pointed by read address belongs on state, then the voltage on BL bit line is close to
0, i.e. N-channel MOS pipe NM1, P-channel metal-oxide-semiconductor PM8 grid voltage be it is low, P-channel metal-oxide-semiconductor PM8 conducting, phase inverter inv2's
Input terminal is high level, and the D input terminal of register DFF is low level, when reading clock rdck becomes high level, register DFF
Low level is exported, i.e. reading data " 0 "；Until next reading clock rdck becomes high level, the output ability of register DFF according to
The data variation of input terminal and change, register DFF output data save read clock rdck a cycle；
If 2) storage CELL belongs to off state, then the read current on BL bit line fills the parasitic capacitance of storage CELL
Electricity, until the voltage on BL bit line reaches high level, since NM3, NM4 pipe play the role of zener diode, so BL bit line
On charging time will not be big because of memory capacity, parasitic capacitance is big and extends the time, and the charging time can quickly, N-channel MOS pipe
NM1, P-channel metal-oxide-semiconductor PM8 grid be high level, N-channel MOS pipe NM1 pipe conducting, phase inverter inv2 input terminal be low level,
The D input terminal of register DFF is high level, and when reading clock rdck becomes high level, register DFF exports high level, that is, is read
Data " 1 " out.
The technical advantages of the present invention are that:
1, the present invention considers in all directions from power consumption, chip area, reading data speed, compares without using band-gap reference, voltage
In the case where the complicated circuits such as device, the properties of product of EEPROM are greatly improved, and product can be optimized, reduce power consumption, it is corresponding to save
Area reduces cost, significantly improves product competitiveness in the market.
2, the present invention is without functional modules such as band-gap reference, current source, voltage comparator, current comparators, simple
Sense amplifier circuit is substantially reduced reading using cascode structure, transmission gate, diode circuit and puts mould on the basis of as shown in Fig. 5
Block power consumption is promoted and reads to put speed, and prevents punch-through the formation of electric current, is equally to improve product competitiveness in the market.
3, S0, S1, S2 switch are increased in the present invention, it is also possible to mos pipe substitution effectively adjusts and reads discharge stream size,
In specific application: in chip manufacturing proces, when technique deviates, cause in circuit parameters (voltage, electric current,
Parasitic capacitance, resistance) deviation, it can be switched at this time by adjusting S0, S1, S2, determine most suitable reading discharge stream parameter, thus
With the smallest power consumption, it is optimal reading and puts performance.The grid voltage for stablizing mirror image pipe using filter circuit, reaches better mirror image
Matching effect, and the capacitor cap also plays the role of start-up circuit, makes to read to put faster to enter working condition.
4, acquisition reads to put data for convenience, and the present invention increases register in output end, each is read clock rdck and arrives
When, data are put in the reading that register will store the EEPROM under address at this time, and until next reading clock arrives, this is designed
Data acquisition is left for plenty of time, to realize the design for facilitating digital processing part.
Detailed description of the invention
Fig. 1: the circuit diagram of the sense amplifier circuit in the prior art using voltage comparator；
Fig. 2: voltage comparator is put in the reading in the prior art；
Fig. 3: topological structure is put in the reading of current comparator in the prior art；
Fig. 4: difference current comparator configuration in the prior art；
Fig. 5: traditional sense amplifier circuit schematic diagram in the prior art；
Fig. 6: for the circuit diagram of sense amplifier circuit of the present invention.
Specific embodiment
The present invention is described in detail below with reference to embodiment and Figure of description, but not limited to this.
Embodiment 1,
As shown in Fig. 6.
A kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption, including read discharge stream source Is_rd, reading data signal enb_
Rd, BL bit line and output end further include common gate circuit module and transmission gate circuit module；The common gate circuit module includes two
Common source one-stage amplifier in parallel: N-channel MOS pipe NM1 and P-channel metal-oxide-semiconductor PM8；The transmission gate circuit module is included in
Concatenated P-channel metal-oxide-semiconductor PM9 and N-channel MOS pipe NM0 on read current access.
It is provided with voltage stabilizing circuit module on the access in the reading discharge stream source of sense amplifier circuit, to reduce read current to storage
The discharge time of CELL parasitic capacitance.
The voltage stabilizing circuit module includes the series connection N-channel MOS pipe NM3 and N-channel MOS pipe NM4 of two diode connection.
The sense amplifier circuit further includes on-off circuit module, comprising: is reading to go here and there between discharge stream source Is_rd and power vd D
Join P-channel metal-oxide-semiconductor PM0, the P-channel metal-oxide-semiconductor PM1, P-channel metal-oxide-semiconductor PM2, P-channel metal-oxide-semiconductor PM3 of setting；The P-channel MOS
It is parallel with switch S2 on pipe PM0, switch S1 is parallel on the P-channel metal-oxide-semiconductor PM1, is parallel on the P-channel metal-oxide-semiconductor PM2
Switch S0.
The on-off circuit module is also connected with filter circuit module.It is preferred that resistance res, capacitor cap form filter circuit,
The grid voltage for stablizing mirror image pipe, reaches better mirror image matching effect.Wherein capacitor cap also plays the role of start-up circuit, makes
Reading, which is put, faster enters working condition.
It is additionally provided with register circuit module in the output end of the sense amplifier circuit, at this time according to read clock signal storage
Data are put in the reading of EEPROM under location.Each read clock rdck to when, register will store under address at this time
Data are put in the reading of EEPROM, until next reading clock arrives.
There is no complicated voltage comparator, current comparator etc. in entire circuit of the present invention, significantly reduces EEPROM
Power consumption and chip area, reduce cost, promote product competitiveness；It is in parallel using two common source one-stage amplifiers in circuit,
That is NM1 and PM8 is in parallel, that is to say the circuit theory as compared using phase inverter threshold value as reference voltage in attached drawing 5.And
NM1 and PM8 parallel connection reduces bit-line voltage turn threshold using grid cascode structure altogether, even if power vd D has a fluctuation, NM1,
The threshold value turnover voltage of PM8 is also very stable；Increase by two two poles on storage CELL to the access for reading discharge stream source simultaneously
The series connection metal-oxide-semiconductor of pipe connection: NM3, NM4, as voltage regulator circuit, i.e., when EEPROM reads data " 1 ", the leakage of described NM3, NM4
The pole end drain has a burning voltage, reduces read current to the discharge time of CELL parasitic capacitance, significantly improves EEPROM's
Read data speed；Punchthrough current is formed in the turn threshold of NM1, PM8 in order to prevent, increases by one on the read current access of CELL
A transmission gate formed by PM9, NM0, the grid of the PM9 do not meet VSS, connect the grid of PM6, in order that increasing the resistance of PM9,
I.e. when reading data " 1 ", the grid voltage of PM8 is first increased, and after PM8 cut-off, the grid voltage of NM1 just reaches turn threshold and makes
The conducting of NM1 pipe avoids PM8, NM1 in this way and simultaneously turns on to form the case where punchthrough current increases power consumption.
Embodiment 2,
The working method of sense amplifier circuit as described in Example 1, comprising: when the sense amplifier circuit starts to read data, read
Data-signal enb_rd is high level, and P-channel metal-oxide-semiconductor PM4, P-channel metal-oxide-semiconductor PM5 are connected, N-channel MOS pipe NM2 cut-off, then
P-channel metal-oxide-semiconductor PM6, P-channel metal-oxide-semiconductor PM7 conducting, and there is reading discharge stream source Is_rd to pass through P-channel metal-oxide-semiconductor PM3 mirror in proportion
As to P-channel metal-oxide-semiconductor PM6, P-channel metal-oxide-semiconductor PM7 two accesses on, at this point, the sense amplifier circuit function open:
1) if the EEPROM storage CELL pointed by read address belongs on state, then the voltage on BL bit line is close to
0, i.e. N-channel MOS pipe NM1, P-channel metal-oxide-semiconductor PM8 grid voltage be it is low, P-channel metal-oxide-semiconductor PM8 conducting, phase inverter inv2's
Input terminal is high level, and the D input terminal of register DFF is low level, when reading clock rdck becomes high level, register DFF
Low level is exported, i.e. reading data " 0 "；Until next reading clock rdck becomes high level, the output ability of register DFF according to
The data variation of input terminal and change, register DFF output data save read clock rdck a cycle；
If 2) storage CELL belongs to off state, then the read current on BL bit line fills the parasitic capacitance of storage CELL
Electricity, until the voltage on BL bit line reaches high level, since NM3, NM4 pipe play the role of zener diode, so BL bit line
On charging time will not be big because of memory capacity, parasitic capacitance is big and extends the time, and the charging time can quickly, N-channel MOS pipe
NM1, P-channel metal-oxide-semiconductor PM8 grid be high level, N-channel MOS pipe NM1 pipe conducting, phase inverter inv2 input terminal be low level,
The D input terminal of register DFF is high level, and when reading clock rdck becomes high level, register DFF exports high level, that is, is read
Data " 1 " out.
Although the present invention is illustrated using specific embodiment, the explanation of embodiment is not intended to limit of the invention
Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, it is easy to carry out various modifications or embodiment can be combined.
Claims (7)
1. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption, including read discharge stream source Is_rd, reading data signal enb_
Rd, BL bit line and output end, which is characterized in that further include common gate circuit module and transmission gate circuit module；The common gate circuit
Module includes two common source one-stage amplifiers in parallel: N-channel MOS pipe NM1 and P-channel metal-oxide-semiconductor PM8；The transmission gate electricity
Road module includes the concatenated P-channel metal-oxide-semiconductor PM9 and N-channel MOS pipe NM0 on read current access.
2. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption according to claim 1, which is characterized in that reading to put
It is provided with voltage stabilizing circuit module on the access in the reading discharge stream source of circuit, is put with reducing read current to storage CELL parasitic capacitance
The electric time.
3. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption according to claim 1, which is characterized in that described steady
Volt circuit module includes the series connection N-channel MOS pipe NM3 and N-channel MOS pipe NM4 of two diode connection.
4. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption according to claim 2, which is characterized in that the reading
Electric discharge road further includes on-off circuit module, comprising: in the P-channel for reading to be arranged in series between discharge stream source Is_rd and power vd D
Metal-oxide-semiconductor PM0, P-channel metal-oxide-semiconductor PM1, P-channel metal-oxide-semiconductor PM2, P-channel metal-oxide-semiconductor PM3；It is parallel on the P-channel metal-oxide-semiconductor PM0
It is parallel with switch S1 on switch S2, the P-channel metal-oxide-semiconductor PM1, is parallel with switch S0 on the P-channel metal-oxide-semiconductor PM2.
5. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption according to claim 4, which is characterized in that described to open
It closes circuit module and is also connected with filter circuit module.
6. a kind of sensitive sense amplifier circuit of EEPROM of efficient low-power consumption according to claim 4, which is characterized in that described
The output end of sense amplifier circuit is additionally provided with register circuit module, according to the EEPROM's under read clock signal storage at this time address
Data are put in reading.
7. the working method of the sensitive sense amplifier circuit of EEPROM of efficient low-power consumption as claimed in any one of claims 1 to 6, packet
Include: when the sense amplifier circuit starts to read data, reading data signal enb_rd is high level, P-channel metal-oxide-semiconductor PM4, P-channel MOS
Pipe PM5 conducting, N-channel MOS pipe NM2 cut-off, then P-channel metal-oxide-semiconductor PM6, P-channel metal-oxide-semiconductor PM7 are connected, and have reading discharge stream
Source Is_rd passes through P-channel metal-oxide-semiconductor PM3 in proportion and is mirrored on two accesses of P-channel metal-oxide-semiconductor PM6, P-channel metal-oxide-semiconductor PM7,
At this point, the sense amplifier circuit function is opened: it is characterized in that,
1) if the EEPROM storage CELL pointed by read address belongs on state, then the voltage on BL bit line is close to 0, i.e.,
N-channel MOS pipe NM1, P-channel metal-oxide-semiconductor PM8 grid voltage be it is low, P-channel metal-oxide-semiconductor PM8 conducting, the input of phase inverter inv2
End is high level, and the D input terminal of register DFF is low level, when reading clock rdck becomes high level, register DFF output
Low level, i.e. reading data " 0 "；Until next reading clock rdck becomes high level, the output of register DFF is just according to input
The data variation at end and change, register DFF output data save read clock rdck a cycle；
If 2) storage CELL belongs to off state, then the read current on BL bit line charges to the parasitic capacitance of storage CELL, directly
Voltage on to BL bit line reaches high level, N-channel MOS pipe NM1, P-channel metal-oxide-semiconductor PM8 grid be high level, N-channel MOS
The conducting of pipe NM1 pipe, phase inverter inv2 input terminal are low level, and the D input terminal of register DFF is high level, as reading clock rdck
When becoming high level, register DFF exports high level, i.e. reading data " 1 ".
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411627.9A CN110136765B (en) | 2019-05-17 | 2019-05-17 | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof |
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|---|---|---|---|
| CN201910411627.9A CN110136765B (en) | 2019-05-17 | 2019-05-17 | High-efficiency low-power-consumption EEPROM sensitive read-discharge circuit and working method thereof |
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| CN110136765B CN110136765B (en) | 2020-11-06 |
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| CN112489712A (en) * | 2020-12-21 | 2021-03-12 | 中国电子科技集团公司第四十七研究所 | EEPROM programming period control circuit |
| CN113053442A (en) * | 2021-03-18 | 2021-06-29 | 华南师范大学 | Low-power consumption EEPROM memory |
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| Publication number | Publication date |
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| CN110136765B (en) | 2020-11-06 |
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Denomination of invention: An EEPROM sensitive reading and amplifier circuit with high efficiency and low power consumption and its working method Effective date of registration: 20230301 Granted publication date: 20201106 Pledgee: Bank of China Limited Jinan high tech sub branch Pledgor: SHANDONG HUAYI MICRO-ELECTRONICS Co.,Ltd. Registration number: Y2023370000046 |
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