CN110120816B - Current steering DAC switch array driving circuit - Google Patents
Current steering DAC switch array driving circuit Download PDFInfo
- Publication number
- CN110120816B CN110120816B CN201810109273.8A CN201810109273A CN110120816B CN 110120816 B CN110120816 B CN 110120816B CN 201810109273 A CN201810109273 A CN 201810109273A CN 110120816 B CN110120816 B CN 110120816B
- Authority
- CN
- China
- Prior art keywords
- tube
- driver
- power switch
- voltage
- pmos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 claims abstract description 13
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 claims abstract description 13
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a current steering DAC switch array driving circuit which comprises a driver 1, a driver 2, a driver 3, a driver 4, a driving voltage Vg1, a driving voltage Vg2, a driving voltage Vg3, a driving voltage Vg4, a power switch tube MP1, a power switch tube MP2, a power switch tube MP3, a power switch tube MP4, a PMOS tube Md1, an NMOS tube Md2, a PMOS tube Md3, a PMOS tube Md4, a voltage source VDD1, a voltage source VDD2, a voltage Vcom, an input signal Din and an input signal Vin. The invention has the beneficial effects that: the new driver architecture can output a low voltage that is not zero. The switching tubes MP 1-MP 4 are enabled to work in a saturation region when being conducted; the use of the LDO power supply isolates noise, improves the high voltage of the output signal of the driver, and effectively turns off the switching tubes MP 1-MP 4; the output impedance of the current pump DAC is improved, and the high-frequency dynamic performance is improved.
Description
Technical Field
The invention relates to the field of high-speed high-precision digital-to-analog converter design, in particular to a current steering DAC switch array driving circuit.
Background
Most of the signals present in nature are continuous analog signals, not discrete digital signals. Thus, a medium is needed to bridge the signal transfer between analog and digital, and digital-to-analog converters (DACs) are an essential interface circuit to convert digital signals to analog signals. The high-speed development of Digital Signal Processing (DSP) circuits also places higher demands on the performance of the converter circuits. In many typical applications, such as wired or wireless communication, video signal processing, direct digital signal synthesis, etc., the performance of a high-speed and high-precision converter largely determines the overall system performance, and especially in the high-speed communication field, the performance of the converter may even become a bottleneck for the overall system performance. Therefore, research into converter performance has been a hotspot, both in academia and industry.
Among the many types of DACs, the structure of the current steering DAC determines its inherent high speed and high accuracy characteristics. It is usually composed of a set of current sources and corresponding current switches, which, like a steering engine, direct current to either the positive or negative output depending on the input signal. Because the current steering DAC outputs a current signal, the load can be directly driven without adding a voltage buffer, and meanwhile, the load can be converted into a voltage output by the on-chip load. In addition, the DAC of the current steering structure can be produced by adopting a standard CMOS (complementary metal oxide semiconductor) process, and is easy to integrate with a digital circuit, so that the cost of the system is reduced.
The prior art has the following defects: since conventional drivers typically output levels of power supply voltage (Vdd) to ground voltage (0), the threshold voltage of MOS transistors is less than 1V due to the shrinking process size. And at 0V, the switching tubes MP1 to MP4 are turned on. In this case, for the switching tube (e.g., MP 1), it is necessary to satisfy the following conditions for operating in the saturation region:
Vcom-Vg1-|V TH1 |＜Vcom-Va
i.e. |V TH1 |＞Va-Vg1
|V TH1 | > Va, when v1=0
When the output swing is 1V Vp, va is 1V at maximum. At this time due to |V TH1 The saturation region condition described above is not satisfied by < 1. Therefore, when the switching tube is in an on state and Va and Vb reach the vicinity of the maximum swing, the switching tube is in a linear region; the output impedance of the switching tube in the linear region is much lower than that in the saturated region, and for a high-speed current steering DAC, the dynamic performance (such as SFDR) at high frequency mainly contributes to limited output impedance, and the larger the output impedance is, the better the performance is, so that the switching tube working in the linear region reduces the output impedance of the current steering DAC, and the high-frequency dynamic performance is deteriorated; in addition, as the process size decreases, the low voltage VDD2 decreases, and at this time, the switch PMOS may be turned off incompletely, which affects the switching characteristics and decreases the performance.
For the problems in the related art, no effective solution has been proposed at present.
Disclosure of Invention
Aiming at the problems in the related art, the invention provides a current steering DAC switch array driving circuit to overcome the technical problems in the prior art.
The technical scheme of the invention is realized as follows:
according to one aspect of the invention, a current steering DAC switch array driving circuit is provided, which comprises a driver 1, a driver 2, a driver 3, a driver 4, a driving voltage Vg1, a driving voltage Vg2, a driving voltage Vg3, a driving voltage Vg4, a power switch tube MP1, a power switch tube MP2, a power switch tube MP3, a power switch tube MP4, a PMOS tube Md1, an NMOS tube Md2, a PMOS tube Md3, a PMOS tube Md4, a voltage source VDD1, a voltage source VDD2, a voltage Vcom, an input signal Din and an input signal Vin, wherein the voltage source VDD1 forms the voltage Vcom through a current source, the voltage source VDD1 is respectively connected with the power switch tube MP1, the power switch tube MP2, the power switch tube MP3 and the power switch tube MP4, the input signal Din passes through the driver 1, the driver 2, the driver 3 and the driver 4 respectively form the driving voltage Vg1, the voltage source VDD and the power switch tube MP4, the voltage source VDD is connected with the power switch tube MP2, the power switch tube MP3 and the power switch MP4, and the drain tube MP4 are connected with the power switch tube MP1, and the drain tube MP4 is connected with the drain tube MP4.
The input signal Vin is respectively connected with the gate ends of the PMOS transistor Md1, the NMOS transistor Md2 and the PMOS transistor Md4, the drain end of the PMOS transistor Md1 is respectively connected with the drain end of the NMOS transistor Md2 and the gate end of the PMOS transistor Md3, the source end of the NMOS transistor Md2 is grounded, the drain end of the PMOS transistor Md3 is connected with the source end of the PMOS transistor Md4, the source end of the PMOS transistor Md3 is connected with the driving power supply LDO, and the drain end of the PMOS transistor Md4 is grounded.
Further, the PMOS tube Md1 is connected to a voltage source VDD 2.
Further, vg0 is connected to the gate end of the PMOS transistor Md3, and the input signal Vin is connected to the gate end of the PMOS transistor Md 4.
Further, the frequency of the voltage Vcom is 50-60Hz.
The invention has the beneficial effects that:
1. the new driver architecture can output a low voltage that is not zero. The switching tubes MP1 to MP4 are operated in a saturation region when being conducted.
2. The use of the LDO power supply isolates noise, improves the high voltage of the output signal of the driver, and effectively turns off the switching tubes MP 1-MP 4.
3. The output impedance of the current pump DAC is improved, and the high-frequency dynamic performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a current steering DAC switch array driver circuit according to an embodiment of the invention;
fig. 2 is a schematic diagram of a current steering DAC switch array driver circuit according to the prior art.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
According to an embodiment of the present invention, there is provided a current steering DAC switch array driver circuit.
As shown in fig. 1-2, a current steering DAC switch array driving circuit according to an embodiment of the present invention includes a driver 1, a driver 2, a driver 3, a driver 4, a driving voltage Vg1, a driving voltage Vg2, a driving voltage Vg3, a driving voltage Vg4, a power switch tube MP1, a power switch tube MP2, a power switch tube MP3, a power switch tube MP4, a PMOS tube Md1, an NMOS tube Md2, a PMOS tube Md3, a PMOS tube Md4, a voltage source VDD1, a voltage source VDD2, a voltage Vcom, an input signal Din and an input signal Vin, wherein the voltage source VDD1 forms the voltage Vcom through a current source, the voltage source VDD1 is respectively connected with the power switch tube MP1, the power switch tube MP2, the power switch tube MP3, the power switch tube MP4, the input signal Din passes through the driver 1, the driver 2, the driver 3, the driver 4 respectively corresponds to form the driving voltage 1, the voltage source VDD2, the driver 4, the power switch tube MP2 is connected with the power switch MP4, and the drain tube MP4 is connected with the drain terminal of the power switch tube MP1, and the drain terminal of the power switch MP4 is connected with the drain terminal of the power switch MP4.
The input signal Vin is respectively connected with the gate ends of the PMOS transistor Md1, the NMOS transistor Md2 and the PMOS transistor Md4, the drain end of the PMOS transistor Md1 is respectively connected with the drain end of the NMOS transistor Md2 and the gate end of the PMOS transistor Md3, the source end of the NMOS transistor Md2 is grounded, the drain end of the PMOS transistor Md3 is connected with the source end of the PMOS transistor Md4, the source end of the PMOS transistor Md3 is connected with the driving power supply LDO, and the drain end of the PMOS transistor Md4 is grounded.
In one embodiment, the PMOS transistor Md1 is connected to the voltage source VDD 2.
In one embodiment, the Vg0 is connected to the gate end of the PMOS transistor Md3, and the input signal Vin is connected to the gate end of the PMOS transistor Md 4.
In one embodiment, the voltage Vcom has a frequency of 50-60Hz.
Additionally, in one embodiment, as in FIG. 1: in the novel driving circuit, the first-stage inverter reversely generates a signal Vg0 from the input signal Vin, wherein Vg0 is added to the gate end of the PMOS tube Md3 above the second-stage circuit, and the input signal Vin is added to the gate end of the PMOS tube Md4 below the second stage. When the input signal Vin changes from low to high, vg3 changes from high to low, the PMOS transistor Md3 is turned on, and the PMOS transistor Md4 is turned off, and the output Vg voltage is VLDO. When the input signal Vin changes from high to low, vg3 changes from low to high, the PMOS transistor Md4 is gradually turned on, vg starts to decrease, and as Vg decreases more and more, the voltage decreases to a certain level so that the PMOS transistor Md4 enters a subthreshold region, at this time, the gain of the PMOS transistor Md4 decreases rapidly, and the Vg decreases slowly. When Vg is reduced to a certain voltage VL, the PMOS tube Md4 finally enters an interception area. At this time, vg no longer decreases, tending to stabilize to VL. The new driver architecture outputs high and low voltages VLDO and VL, respectively. Meanwhile, the phenomenon that the PMOS tube is closed continuously and works in a linear region is avoided. The low level of Vg depends on the size ratio of the PMOS transistor Md3 to the PMOS transistor Md 4. The proper ratio can provide the most reasonable driving voltage range for the switching tube, and the dynamic performance of the DAC is improved maximally. The new driver structure can output low voltage which is not zero, so that the switching tubes MP 1-MP 4 work in a saturation region when being conducted; the use of the LDO power supply isolates noise, improves the high voltage of the output signal of the driver, and effectively turns off the switching tubes MP 1-MP 4. The output impedance of the current pump DAC is improved, and the high-frequency dynamic performance is improved.
In summary, by means of the above technical solution of the present invention, through the driver 1, the driver 2, the driver 3, the driver 4, the driving voltage Vg1, the driving voltage Vg2, the driving voltage Vg3, the driving voltage Vg4, the power switch tube MP1, the power switch tube MP2, the power switch tube MP3, the power switch tube MP4, the PMOS tube Md1, the NMOS tube Md2, the PMOS tube Md3, the PMOS tube Md4, the voltage source VDD1, the voltage source VDD2, the voltage Vcom, the input signal Din and the input signal Vin, the voltage source VDD1 forms the voltage Vcom through a current source, the voltage source VDD1 is respectively connected with the power switch tube MP1, the power switch tube MP2, the power switch tube MP3, the power switch tube MP4, the input signal Din passes through the driver 1, the driver 2, the driver 3, the driver 4 respectively and correspondingly forms the driving voltage mn 1, the driving voltage mn 3, the voltage mn 4, the power switch tube MP1 is connected with the power switch MP2, the power switch MP4 is connected with the power switch tube MP2, the drain terminal Vg4 is connected with the power switch MP2, and the drain terminal Vg4 is connected with the power switch MP 2.
The input signal Vin is respectively connected with the gate ends of the PMOS transistor Md1, the NMOS transistor Md2 and the PMOS transistor Md4, the drain end of the PMOS transistor Md1 is respectively connected with the drain end of the NMOS transistor Md2 and the gate end of the PMOS transistor Md3, the source end of the NMOS transistor Md2 is grounded, the drain end of the PMOS transistor Md3 is connected with the source end of the PMOS transistor Md4, the source end of the PMOS transistor Md3 is connected with the driving power supply LDO, and the drain end of the PMOS transistor Md4 is grounded.
The invention has the beneficial effects that: the new driver architecture can output a low voltage that is not zero. The switching tubes MP 1-MP 4 are enabled to work in a saturation region when being conducted; the use of the LDO power supply isolates noise, improves the high voltage of the output signal of the driver, and effectively turns off the switching tubes MP 1-MP 4; the output impedance of the current pump DAC is improved, and the high-frequency dynamic performance is improved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (4)
1. The current steering DAC switch array driving circuit is characterized by comprising a driver 1, a driver 2, a driver 3, a driver 4, a driving voltage Vg1, a driving voltage Vg2, a driving voltage Vg3, a driving voltage Vg4, a power switch tube MP1, a power switch tube MP2, a power switch tube MP3, a power switch tube MP4, a PMOS tube Md1, an NMOS tube Md2, a PMOS tube Md3, a PMOS tube Md4, a voltage source VDD1, a voltage source VDD2, a voltage Vcom, an input signal Din and an input signal Vin, wherein the voltage source VDD1 forms the voltage Vcom through a current source, the voltage source VDD1 is respectively connected with the power switch tube MP1, the power switch tube MP2, the power switch tube MP3 and the power switch tube MP4, the input signal Din passes through the driver 1, the driver 2, the driver 3 and the driver 4 respectively correspondingly form the driving voltage Vg1, the driving voltage 2, the driver 3 and the voltage source VDD 4, the power switch tube MP1 is connected with a power switch tube MP2, the power switch tube MP4 is connected with a drain tube MP2, the drain tube MP4 is connected with a drain tube MP2, and the drain tube MP2 is connected with a drain tube MP 2;
the input signal Vin is respectively connected with the gate ends of the PMOS transistor Md1, the NMOS transistor Md2 and the PMOS transistor Md4, the drain end of the PMOS transistor Md1 is respectively connected with the drain end of the NMOS transistor Md2 and the gate end of the PMOS transistor Md3, the source end of the NMOS transistor Md2 is grounded, the drain end of the PMOS transistor Md3 is connected with the source end of the PMOS transistor Md4, the source end of the PMOS transistor Md3 is connected with the driving power supply LDO, and the drain end of the PMOS transistor Md4 is grounded.
2. The current steering DAC switch array driver circuit of claim 1, wherein the PMOS transistor Md1 is connected to a voltage source VDD 2.
3. The current steering DAC switch array driver circuit of claim 1, wherein Vg0 is coupled to the gate terminal of the PMOS transistor Md3 and the input signal Vin is coupled to the gate terminal of the PMOS transistor Md 4.
4. A current steering DAC switch array driver circuit according to claim 1, wherein the voltage Vcom has a frequency of 50-60Hz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810109273.8A CN110120816B (en) | 2018-02-05 | 2018-02-05 | Current steering DAC switch array driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810109273.8A CN110120816B (en) | 2018-02-05 | 2018-02-05 | Current steering DAC switch array driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110120816A CN110120816A (en) | 2019-08-13 |
| CN110120816B true CN110120816B (en) | 2024-02-27 |
Family
ID=67519117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810109273.8A Active CN110120816B (en) | 2018-02-05 | 2018-02-05 | Current steering DAC switch array driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110120816B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7663422B1 (en) * | 2008-09-02 | 2010-02-16 | Himax Technologies Limted | Source driving circuit for preventing gamma coupling |
| CN102571097A (en) * | 2010-12-31 | 2012-07-11 | 国民技术股份有限公司 | Voltage amplitude limiting circuit for controlling current supply switch of current steering analog-to-digital converter |
| CN104467861A (en) * | 2013-09-12 | 2015-03-25 | 富士通半导体股份有限公司 | Circuitry and methods for use in mixed-signal circuitry |
| CN106294262A (en) * | 2016-08-22 | 2017-01-04 | 上海集成电路研发中心有限公司 | A kind of LVDS drive circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8089323B2 (en) * | 2006-08-05 | 2012-01-03 | Min Ming Tarng | Green technology: green circuit and device designs of green chip |
| TWI305339B (en) * | 2005-04-28 | 2009-01-11 | Novatek Microelectronics Corp | Source driver and structure of adjusting voltage with speed |
-
2018
- 2018-02-05 CN CN201810109273.8A patent/CN110120816B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7663422B1 (en) * | 2008-09-02 | 2010-02-16 | Himax Technologies Limted | Source driving circuit for preventing gamma coupling |
| CN102571097A (en) * | 2010-12-31 | 2012-07-11 | 国民技术股份有限公司 | Voltage amplitude limiting circuit for controlling current supply switch of current steering analog-to-digital converter |
| CN104467861A (en) * | 2013-09-12 | 2015-03-25 | 富士通半导体股份有限公司 | Circuitry and methods for use in mixed-signal circuitry |
| CN106294262A (en) * | 2016-08-22 | 2017-01-04 | 上海集成电路研发中心有限公司 | A kind of LVDS drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110120816A (en) | 2019-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100353295B1 (en) | Amplifier with dynamic compensation and method | |
| CN110729995B (en) | Level conversion circuit and level conversion method | |
| US7271630B2 (en) | Push-pull buffer amplifier and source driver | |
| US7834791B2 (en) | Current steering DAC and voltage booster of same | |
| US7733182B2 (en) | Hybrid class AB super follower | |
| CN112953503B (en) | High-linearity grid voltage bootstrap switch circuit | |
| CN109194330B (en) | Buffer circuit and buffer | |
| KR101413200B1 (en) | Power amplifier | |
| US7671655B2 (en) | Level conversion circuit for a semiconductor circuit | |
| TWI591968B (en) | Level shifter circuit applied to display apparatus | |
| KR20120067684A (en) | Current switch driving circuit and digital to analog converter | |
| US9436023B2 (en) | Operational amplifier | |
| US20060114061A1 (en) | Class AB CMOS output circuit equiped with CMOS circuit operating by predetermined operating current | |
| CN110120816B (en) | Current steering DAC switch array driving circuit | |
| US6653961B1 (en) | Multiplying digital-to-analog converter structures that reduce signal distortion | |
| CN112965567B (en) | Low-noise voltage driving buffer | |
| JP2012114610A (en) | Electronic circuit | |
| CN111721986B (en) | Wide input common mode voltage range current detection amplifier circuit | |
| CN111030613B (en) | Radio frequency signal processing circuit and radio frequency front end unit | |
| CN103684299A (en) | Low-voltage low-power consumption bulk-driven operational amplifier | |
| JP2006157649A (en) | Pulse polarity modulation circuit | |
| CN110224699B (en) | Analog-to-digital converter | |
| CN107204772B (en) | High-linearity high-speed signal buffer circuit | |
| CN207782776U (en) | A kind of current steering DAC switching matrix drive circuits | |
| CN111506144A (en) | Low-power consumption method applied to L DO |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |