CN110112213A - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
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- CN110112213A CN110112213A CN201910437976.8A CN201910437976A CN110112213A CN 110112213 A CN110112213 A CN 110112213A CN 201910437976 A CN201910437976 A CN 201910437976A CN 110112213 A CN110112213 A CN 110112213A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 19
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000000284 extract Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a kind of insulated gate bipolar transistors, including the base area N-, the base area P+, N+ emitter region, emitter, gate oxide, gate electrode, N-type buffer layer, the collector area P+, thin silicon dioxide layer, N-type polycrystalline silicon area and metal collector, it is characterised in that: the N-type buffer layer is stacked gradually with the collector area P+ to far from the base area N- direction；The thin silicon dioxide layer and N-type polycrystalline silicon area stacks gradually from the collector area P+ to separate N-type buffer layer direction and forms a polysilicon emitter polar region, and the collector area P+ is not completely covered for this polysilicon emitter polar region.N-type buffer layer, the collector area P+ and polysilicon emitter polar region constitute one can be with the polysilicon emitter NPN type triode of high-speed switch, when so that device turning off, the express passway that nonequilibrium carrier extracts is formed, insulated gate bipolar transistor is helped to realize switch rapidly.
Description
Technical field
The present invention relates to semiconductor power device technology fields, more particularly, to a kind of insulated gate bipolar transistor.
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviation IGBT) is a kind of
It quickly grows, widely used semiconductor power device.It can be regarded as by metal oxide semiconductor field effect tube
(MOSFET) and bipolar junction transistor (BJT) composition compound full-control type semiconductor power device.Both there is power MOSFET
Voltage control, the advantage that input impedance is high, driving circuit is simple, and possess that BJT conducting resistance is small, current density is big, blocks
The multiple advantages such as voltage height.It suffers from the fields such as household electrical appliance, generation of electricity by new energy, smart grid, power traction and answers extensively
With.
It is well known that the collector at the device back side can be infused to the base area N- in insulated gate bipolar transistor forward conduction
Enter a large amount of nonequilibrium carrier, and the concentration of nonequilibrium carrier can be considerably beyond the original equilbrium carrier in the base area N-
Concentration to form conductivity modulation effect strongly in the base area N-, therefore can greatly reduce the conducting pressure of device
Drop.But device shutdown when, a large amount of nonequilibrium carrier due to cannot it is compound in time or from collector extract out, will lead to
Device has biggish current tail, keeps device turn-off speed slack-off, and turn-off power loss increases, and the working frequency of device is caused to drop
It is low.
For the turn-off speed for increasing device, shutdown power consumption, document P.A.Gough, M.R.Simpson, and are reduced
V.Rumenik, " Fast switching lateral insulated gate transistor " (transverse direction of high-speed switch is absolutely
Edge gate transistor), IEEE IEDM Tech.Dig., 1986, pp.218-221, the device architecture of anode in short circuit is proposed, is applied
On to insulated gate bipolar transistor as shown in Figure 1.Compared with traditional insulated gate bipolar transistor structure, it is maximum not
It is both to increase the collector area N+ 11 on the collector area P+ 12 overleaf again.When the insulated gate bipolar of anode in short circuit is brilliant
When body pipe turns off, the nonequilibrium carrier of the base area N- can quickly be exited from the collector area N+, and device is rapidly switched off.
But on the other hand, due to the presence of the collector area N+, so that device is in forward conduction, the non-equilibrium current-carrying of P+ collector
The injection efficiency of son decreases, this causes the non-equilibrium load note subnumber amount into the base area N- that can be reduced, this leads to device
Conductance modulation act on and reducing, the conduction voltage drop of device increased compared with conventional insulator grid bipolar junction transistor.Thus it sees
Out, there is contradiction between conduction voltage drop and turn-off time the two device parameter performances, need to trade off consideration.It is double in insulated gate
In bipolar transistor, conduction voltage drop largely needed to determine by the injection efficiency for adjusting collector with the turn-off time,
Lower anode injection efficiency can of course lead to lower turn-off time and lesser turn-off power loss, but conduction voltage drop is but wanted
Rise, the loss of conducting is thus caused to increase.
Summary of the invention
Existing conventional insulator grid bipolar junction transistor conduction voltage drop is low but switch time is long in order to overcome by the present invention, and positive
Although pole short circuit type insulated gate bipolar transistor switching speed is fast, the high problem of conduction voltage drop provides a kind of high-speed switch
Insulated gate bipolar transistor, have in conduction voltage drop and on switch time good compromise.
In order to achieve the above purpose, the present invention provides a kind of insulated gate bipolar transistors of high-speed switch, it is wrapped
Include the base area N-, the base area P+, N+ emitter region, emitter, gate oxide, gate electrode, N-type buffer layer, the collector area P+, thin dioxy
SiClx floor, N-type polycrystalline silicon area and metal collector, it is characterised in that: the base area P+, N+ emitter region, emitter, gate oxide with
Side of the gate electrode in the base area N-；The N+ emitter region is in side of the collector area P+ far from the base area N-；The emitter
It is covered on the base area P+ and N+ emitter region, and far from the base area N-；The gate oxide be covered on the base area N-, the base area P+ with
On N+ emitter region, do not contacted with emitter；N-type buffer layer, the collector area P+, thin silicon dioxide layer, N-type polycrystalline silicon area
With metal collector the base area N- the other side；The N-type buffer layer and the collector area P+ to far from the base area N- direction successively
Stacking；The thin silicon dioxide layer and N-type polycrystalline silicon area stacks gradually group from the collector area P+ to far from N-type buffer layer direction
At a polysilicon emitter polar region, and the collector area P+ is not completely covered for this polysilicon emitter polar region；The N-type buffer layer with
The doping type in N-type polycrystalline silicon area is n-type doping, and the collector area P+ is p-type doping；N-type buffer layer, the collector area P+ and N
The doping concentration of type multi-crystal silicon area successively increases；The metal collector be covered on N-type polycrystalline silicon area and the collector area P+ it
On.
The base area N- is the region of low doping concentration, and thickness and doping concentration are determined by forward break down voltage, just
It is positively correlated to breakdown voltage and thickness, with doping concentration negative correlation.Insulated gate bipolar if forward break down voltage is 1200V is brilliant
Body pipe, the thickness of the base area N- is between 80~120 μm, and doping concentration is 5 × 1013cm-3~1 × 1014cm-3Between.
For the N-type buffer layer between the base area N- and the collector area P+, doping concentration is low, is unfavorable in device forward direction
When blocking, reversed electric field ends in this N-type buffer layer, reduces so as to cause device forward break down voltage, but doped in concentrations profiled concentration
Too high, then the nonequilibrium carrier that collector can be made to inject is unfavorable for the conductivity modulation effect of the base area N-, therefore by a large amount of compound
The doping concentration of N-type buffer layer is preferably 1 × 1014cm-3~1 × 1018cm-3Between, the thickness of N-type buffer layer is too thick, can make to lead
Logical pressure drop increases, too thin then cannot to be ended on N-type buffer layer by space-charge region, lead in device forward blocking
Device forward break down voltage is caused to reduce, therefore the thickness of N-type buffer layer is preferably 1~6 μm.
The collector area P+ is determined in the other side of the N-type buffer layer far from the base area N-, doping concentration and thickness
Device exists, and the doping concentration and thickness of the collector area P+ are higher, then injects the nonequilibrium carrier of the base area N- just when positive work
More, such conductivity modulation effect is better, and break-over of device pressure drop can reduce, but required extraction is non-in device shutdown
Equilbrium carrier can be more, and the device turn-off time is caused to rise, thus the doping concentration of the collector area P+ be preferably 5 ×
1016cm-3~1 × 1019cm-3Between, the thickness of the collector area P+ is preferably 0.5~2 μm.
The thin silicon dioxide layer is grown between the collector area P+ and N-type polycrystalline silicon area, thin silicon dioxide layer with
Its N-type highly doped polysilicon deposited over is formed together a polysilicon emissioning area, becomes by N-type buffer layer, P+ collector
One NPN triode emitter in area and polysilicon emissioning area composition, the presence of thin silicon dioxide layer can improve NPN triode
Current gain.The thickness of the thin silicon dioxide layer is preferably
The doping concentration in the N-type polycrystalline silicon area necessarily is greater than the doping concentration of the collector area P+, the concentration of both
Than the being positively correlated property of current gain of the NPN triode with composition.Therefore the doping concentration in the N-type polycrystalline silicon area is preferably
1×1019cm-3~1 × 1021cm-3Between, the thickness in the N-type polycrystalline silicon area is preferably
The thin silicon dioxide layer and N-type polycrystalline silicon district's groups at polysilicon emitter polar region do not cover all P+ collection
Electrode district, the size that the window area reserved accounts for the sum of window area and polysilicon emitter polar region area determine device in forward direction
When conducting, nonequilibrium carrier inject the base area N- number.If the window reserved reduces, when this can promote the shutdown of device
Between, but lesser window breathe out I obtain the collector area P+ injection the base area N- nonequilibrium carrier quantity can decline, this can make device
Conductivity modulation effect decline, to make the conduction voltage drop of device increase, therefore the collector area P+ occupied area is preferably 20%
Between~80%.
N-type buffer layer, the collector area P+ and the doping concentration in N-type polycrystalline silicon area successively increases, N-type buffer layer, P
+ collector area and polysilicon emitter constitute a NPN type triode.In device turn off process, this has polysilicon
The NPN type triode of emitter can become the express passway of nonequilibrium carrier, can the nonequilibrium carrier of the base area N- is fast
It extracts out fastly, so that device can turn off rapidly.
Detailed description of the invention
Fig. 1 show the schematic diagram of the section structure of anode in short circuit type insulated gate bipolar transistor；
Fig. 2 show a kind of cross-section structure signal of the insulated gate bipolar transistor of high-speed switch provided by the invention
Figure；
Fig. 3 show a kind of insulated gate bipolar transistor of high-speed switch provided by the invention and anode in short circuit type insulate
The conduction voltage drop of grid bipolar junction transistor simulation result diagram compared with the compromise of turn-off time.
Specific embodiment
As shown in Fig. 2, insulated gate bipolar transistor provided in this embodiment, comprising: the base area N- 24, the base area P+ 29, N+
Emitter region 27, emitter 28, gate oxide 25, gate electrode 26, N-type buffer layer 23, the collector area P+ 22, thin silicon dioxide layer
21, N-type polycrystalline silicon area 20 and metal collector 30, it is characterised in that: the base area P+ 29, N+ emitter region 27, emitter 28, grid oxygen
Change layer 25 and gate electrode 26 in the side of the base area N-, N-type buffer layer 23, the collector area P+ 22, thin silicon dioxide layer 21, N-type are more
The other side of crystal silicon area 20 and metal collector 30 in the base area N- 24；The collector area N-type buffer layer 23 and P+ 22 is to remote
It is stacked gradually from 24 direction of the base area N-；The thin silicon dioxide layer 21 and N-type polycrystalline silicon area 20 are from the collector area P+ 22 to remote
One polysilicon emitter polar region of composition is stacked gradually from 23 direction of N-type buffer layer, and P is not completely covered for this polysilicon emitter polar region
+ collector area 22；The doping type of the N-type buffer layer 23 and N-type polycrystalline silicon area 20 is n-type doping, the collector area P+
22 adulterate for p-type；N-type buffer layer 23, the collector area P+ 22 and the doping concentration in N-type polycrystalline silicon area 20 successively increase；Described
Metal collector 30 is covered on N-type polycrystalline silicon area 20 and the collector area P+ 22.
In the present embodiment, brilliant with the insulated gate bipolar with triode auxiliary shutdown of forward break down voltage 1200V
For body pipe, the base area N- 24 with a thickness of 85 μm, doping concentration is 7.5 × 1013cm-3, can also be according to requiring 5.0 × 1013~
2.0×1014cm-3Between adjust.
In the present embodiment, the base area P+ 29, N+ emitter region 27, emitter 28, gate oxide 25 and gate electrode 26 are in N-
The side of base area 24 forms traditional planar gate type metal oxide semiconductor structure (may be simply referred to as MOS structure), the base area P+ 29
With a thickness of 3 μm, doping concentration is 2 × 1017cm-3, N+ emitter region with a thickness of 0.5 μm, doping concentration is 5 × 1019cm-3；Its
On emitter by survey the metallic aluminium penetrated covering, aluminium with a thickness of 4 μm；Gate oxide 25 with a thickness ofGate electrode 26
Material is phosphorous doped polysilicon, is 5 × 10 to adjust the concentration of threshold voltage p-doped19cm-3, with a thickness of
In the present embodiment, N-type buffer layer 23 forms the other side of MOS structure, doping concentration 5.0 in the base area N- 24
×1015cm-3, with a thickness of 3 μm；The collector area P+ 22 is in side of the N-type buffer layer 23 far from the base area N- 24, doping concentration 1.0
×1018, with a thickness of 1.5 μm.
In the present embodiment, thin silicon dioxide layer 21 and N-type polycrystalline silicon area 20 are buffered by the collector area P+ 22 far from N-type
23 direction of layer stack gradually one polysilicon emitter polar region of composition.Thin silicon dioxide layer 21 with a thickness ofN-type polycrystalline silicon
Area 20 is doped using phosphorus, and the doping concentration of phosphorus is 1 × 1020cm-3, N-type polycrystalline silicon area with a thickness of
In the present embodiment, it covers completely the polysilicon emitter polar region that thin silicon dioxide layer 21 and N-type polycrystalline silicon area 20 form
The collector area P+ 22 is covered, the window area reserved accounts for the 50% of the sum of window area and polysilicon emitter polar region area.
In the present embodiment, it is covered on the metal collector 30 of the collector area P+ 22 Yu N-type polycrystalline silicon area 20, using multilayer
The structure of metal, the metal successively deposited are Al, Ti, Ni, Ag, and thickness is respectively:
With
According to the insulated gate bipolar transistor done with above example manufacturing process, due to N-type buffer layer 23,
The collector area P+ 22 and the doping concentration in N-type polycrystalline silicon area 20 successively increase, thus N-type buffer layer 23, the collector area P+ 22 with
Polysilicon emissioning area constitutes the triode that a NPN type has polysilicon emitter, it is well known that has polysilicon emitter
Triode have quick switch performance can form a pumping in the turn off process of this insulated gate bipolar transistor
The express passway of negated equilbrium carrier is quickly drawn out nonequilibrium carrier from the base area N- 24, so that insulated gate bipolar
Transistor npn npn can turn off rapidly.
According to the setting of each parameter in the present embodiment, insulated gate bipolar transistor provided in this embodiment is closed
The device simulation of disconnected time and conduction voltage drop, in 100A/cm-2Collector Current Density under conduction voltage drop be 1.78V, close
The disconnected time is 0.18 μ s.With the anode in short circuit type bipolar transistor of the parameter of identical Facad structure and the back side collector area P+ parameter
Pipe under different nonequilibrium carrier lifetimes conduction voltage drop compared with the compromise simulation result of turn-off time as shown in figure 3, can be with
Find out, the insulated gate bipolar transistor of the present embodiment has the compromise of better conduction voltage drop and turn-off time.It is pressed in conducting
Drop in identical situation, the turn-off time at least can fast 40% or more, it is shorter in minority carrier life time, when conduction voltage drop is higher, when shutdown
Between even can it is fast again more than.
Although the present invention has preferred embodiment as it appears from the above, however, it is not intended to limit the invention, for this field skill
Art personnel people says, in the case where this patent design and specific embodiment inspire, can directly associate from this patent disclosure and common sense
To some deformations, those of ordinary skill in the art, which also will recognize that, can be used other modes, or normal well-known technique in the prior art
The equivalent change or modification of substitution and feature, the unsubstantialities change such as mutually different combination between feature, can equally be answered
With, can realize this patent description device effect.Therefore, protection scope of the present invention guarantor required by view claims
It protects subject to range.
Claims (6)
1. a kind of insulated gate bipolar transistor characterized by comprising
It is the base area N-, the base area P+, N+ emitter region, emitter, gate oxide, gate electrode, N-type buffer layer, the collector area P+, thin by two
Silicon oxide layer, N-type polycrystalline silicon area and metal collector, it is characterised in that: the base area P+, N+ emitter region, emitter, gate oxide
With gate electrode the base area N- side；The N+ emitter region is in side of the collector area P+ far from the base area N-；The transmitting
Pole is covered on the base area P+ and N+ emitter region, and far from the base area N-；The gate oxide is covered on the base area N-, the base area P+
On N+ emitter region, do not contacted with emitter；N-type buffer layer, the collector area P+, thin silicon dioxide layer, N-type polycrystalline silicon
The other side of area and metal collector in the base area N-；The N-type buffer layer and the collector area P+ to far from the base area N- direction according to
Secondary stacking；The thin silicon dioxide layer is stacked gradually with N-type polycrystalline silicon area from the collector area P+ to far from N-type buffer layer direction
A polysilicon emitter polar region is formed, and the collector area P+ is not completely covered for this polysilicon emitter polar region；The N-type buffer layer
Doping type with N-type polycrystalline silicon area is n-type doping, and the collector area P+ is p-type doping；N-type buffer layer, the collector area P+ with
The doping concentration in N-type polycrystalline silicon area successively increases；The metal collector be covered on N-type polycrystalline silicon area and the collector area P+ it
On.
2. insulated gate bipolar transistor according to claim 1, which is characterized in that the doping of the N-type buffer layer is dense
Degree is 1 × 1014cm-3~1 × 1018cm-3Between, the thickness of the N-type buffer layer is between 1~6 μm.
3. insulated gate bipolar transistor according to claim 1, it is characterised in that: the doping of the collector area P+
Concentration is 5 × 1016cm-3~1 × 1019cm-3Between, the thickness of the collector area P+ is between 0.5~2 μm.
4. insulated gate bipolar transistor according to claim 1, it is characterised in that: the thickness of the thin silicon dioxide layer
Degree existsBetween.
5. insulated gate bipolar transistor according to claims 1 to 2, it is characterised in that: the doping in N-type polycrystalline silicon area is dense
Degree is 1 × 1019cm-3~1 × 1021cm-3Between, the thickness in the N-type polycrystalline silicon area existsBetween.
6. insulated gate bipolar transistor according to claims 1 to 6, it is characterised in that: the thin silicon dioxide layer
With N-type polycrystalline silicon district's groups at polysilicon emitter polar region do not cover all the collector area P+, the window area reserved accounts for window
Between the 20~80% of the sum of open area and polysilicon emitter polar region area.
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|---|---|---|---|
| CN201910437976.8A CN110112213A (en) | 2019-05-24 | 2019-05-24 | Insulated gate bipolar transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910437976.8A CN110112213A (en) | 2019-05-24 | 2019-05-24 | Insulated gate bipolar transistor |
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| CN110112213A true CN110112213A (en) | 2019-08-09 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012037836A1 (en) * | 2010-09-25 | 2012-03-29 | 浙江大学 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
| CN104779277A (en) * | 2014-06-28 | 2015-07-15 | 上海合俊驰半导体科技有限公司 | IGBT with heterojunction field resistance structure and preparation method of IGBT |
| CN105514148A (en) * | 2015-10-22 | 2016-04-20 | 温州墨熵微电子有限公司 | Insulated gate bipolar transistor |
-
2019
- 2019-05-24 CN CN201910437976.8A patent/CN110112213A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012037836A1 (en) * | 2010-09-25 | 2012-03-29 | 浙江大学 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
| CN104779277A (en) * | 2014-06-28 | 2015-07-15 | 上海合俊驰半导体科技有限公司 | IGBT with heterojunction field resistance structure and preparation method of IGBT |
| CN105514148A (en) * | 2015-10-22 | 2016-04-20 | 温州墨熵微电子有限公司 | Insulated gate bipolar transistor |
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