CN110098859B

CN110098859B - Satellite communication system architecture for enhanced partial processing

Info

Publication number: CN110098859B
Application number: CN201811462528.5A
Authority: CN
Inventors: 马修·M·埃弗里特
Original assignee: Boeing Co
Current assignee: Boeing Co
Priority date: 2018-01-30
Filing date: 2018-11-30
Publication date: 2022-09-27
Anticipated expiration: 2038-11-30
Also published as: CA3020783C; CA3020783A1; RU2018135895A; JP2019134406A; CN110098859A; US20190238265A1; MX2018014620A; RU2018135895A3; EP3518436A1; US10419034B2; EP3518436B1

Abstract

The present invention relates to a satellite communication system architecture for enhanced partial processing. Systems, methods, and apparatus for enhanced partial processing of satellite user data are disclosed. In one or more embodiments, a disclosed method for processing satellite data includes: encoding with an outer encoder in the transmitting terminal, modulation with a transmitting modulator in the transmitting terminal, demodulation with a satellite demodulator in the satellite, encoding with an inner encoder in the satellite, modulation with a satellite modulator in the satellite, demodulation with a receiving demodulator in the receiving terminal, decoding with an inner decoder in the receiving terminal, and decoding with an outer decoder in the receiving terminal. In one or more embodiments, the outer encoder and/or the inner encoder are operable to perform Forward Error Correction (FEC) encoding. In at least one embodiment, the outer decoder and/or inner decoder is operable to perform FEC decoding.

Description

Satellite communication system architecture for enhanced partial processing

Technical Field

The present disclosure relates to processing of satellite user data. In particular, it relates to enhanced partial processing of satellite user data.

Background

Modern communication systems use Forward Error Correction (FEC) coding to achieve extremely low error rates. In a single-hop system (e.g., transmitting data directly from a transmitting terminal to a receiving terminal), an FEC encoder in the transmitting terminal encodes an input stream of user data at a given data rate (i.e., user data rate) to produce an encoded data stream that includes additional bits. The FEC encoder outputs a coded data stream at a higher data rate (i.e., the coded data rate). The ratio of the user data rate to the coded data rate is called the code rate. The encoded data stream is then modulated in the transmitting terminal and transmitted to the receiving terminal, where it is demodulated. The FEC decoder in the receiving terminal then uses the extra bits generated by the FEC encoder to correct the errors introduced by the communication channel.

Satellite communication systems also employ FEC coding to achieve low error rates, but the fact that there are two hops (e.g., data transmission from a transmitting terminal to a satellite and then from the satellite to a receiving terminal) increases the number of building options. Each option involves a different arrangement of modulator, demodulator, FEC encoder and FEC decoder. Better performance can be achieved by performing more processing on the satellite at the expense of increased cost and complexity. This trade-off favors simpler satellites, given the options studied so far, because the complexity required to achieve significantly better performance is too costly.

Accordingly, there is a need for an improved satellite communication system architecture that provides better performance than a simple repeater architecture without adding significant cost and complexity to the satellite.

Disclosure of Invention

The present disclosure relates to methods, systems, and apparatus for enhancing partial processing of satellite user data. In one or more embodiments, a method for processing data includes encoding data with an outer encoder in a transmitting terminal to generate an outer code. The method also includes modulating the outer code, the interleaved outer code, and the framed outer code with a Transmit (TX) modulator in the transmitting terminal to generate a modulated outer code. Also, the method includes demodulating the modulated outer code with a satellite demodulator in the satellite to generate a demodulated outer code. In addition, the method includes encoding the demodulated outer code with an inner encoder in the satellite to generate an inner code. In addition, the method includes modulating the inner code, the interleaved inner code, and the framed inner code with a satellite modulator in the satellite to generate a modulated inner code. Also, the method includes demodulating the modulated inner code by a demodulator using Reception (RX) in the receiving terminal to generate a demodulated inner code. In addition, the method includes decoding the demodulated inner code, the deframed inner code, and the deinterleaved inner code with an inner decoder in the receiving terminal to generate a recovered outer code. Further, the method includes decoding the recovered outer code, the deframed outer code, and the deinterleaved outer code with an outer decoder in the receiving terminal to generate recovered data.

In one or more embodiments, the method further comprises: interleaving, by an outer interleaver in the transmitting terminal, the outer code to generate an interleaved outer code before modulation by the transmit modulator; and/or frame processing the outer code and the interleaved outer code by a transmit frame processor in the transmitting terminal to generate a framed outer code prior to modulation by the transmit modulator.

In at least one embodiment, the method further comprises: interleaving, by a satellite interleaver in the satellite, the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; and/or processing the inner code and the interleaved inner code by a satellite frame processor frame in the satellite to generate a framed inner code prior to modulation by the satellite modulator.

In one or more embodiments, the method further comprises: frame-processing the demodulated inner code by a first reception frame processor in the reception terminal to generate a deframed inner code before decoding by the inner decoder; and/or deinterleaving the demodulated inner code and the deframed inner code by an inner deinterleaver in the receiving terminal to generate a deinterleaved inner code before decoding by the inner decoder.

In at least one embodiment, the method further comprises: frame processing the recovered outer code by a second receive frame processor in the receiving terminal to produce a deframed outer code before decoding by the outer decoder; and/or deinterleaving, by an outer deinterleaver in the receiving terminal, the recovered outer code and the deframed outer code to generate a deinterleaved outer code before decoding by the outer decoder.

In one or more embodiments, the data is communication data, command data, and/or user data. In at least one embodiment, the outer encoder and/or the inner encoder perform Forward Error Correction (FEC) encoding. The FEC code may have its own inner and outer codes, which are different from the inner and outer codes defined in this disclosure. In some embodiments, the outer decoder and/or inner decoder performs FEC decoding.

In at least one embodiment, the outer decoder corresponds to an outer encoder and the inner decoder corresponds to an inner encoder. In some embodiments, the transmitting terminal and the receiving terminal are both ground stations, mobile devices, or vehicles.

In one or more embodiments, a system for processing data includes an outer encoder in a transmitting terminal to encode data to generate an outer code. The system also includes a transmit modulator in the transmitting terminal to modulate the outer code, the interleaved outer code, and the framed outer code to generate a modulated outer code. Further, the system includes a satellite demodulator in the satellite to demodulate the modulated outer code to generate a demodulated outer code. In addition, the system includes an inner encoder in the satellite to encode the demodulated outer code to generate an inner code. In addition, the system includes a satellite modulator in the satellite to modulate the inner code, the interleaved inner code, and the framed inner code to generate a modulated inner code. Also, the system includes a reception demodulator in the reception terminal to demodulate the modulated inner code to generate a demodulated inner code. In addition, the system includes an inner decoder in the receiving terminal to decode the demodulated inner code, the deframed inner code and the deinterleaved inner code to generate a recovered outer code. Further, the system includes an outer decoder in the receiving terminal to decode the recovered outer code, the deframed outer code and the deinterleaved outer code to generate recovered data.

In at least one embodiment, the system further comprises an outer interleaver in the transmitting terminal for interleaving the outer code to generate an interleaved outer code prior to modulation by the transmit modulator; and/or a transmit frame processor in the transmitting terminal for frame processing the outer code and the interleaved outer code to generate a framed outer code prior to modulation by the transmit modulator.

In one or more embodiments, the system further includes a satellite interleaver in the satellite for interleaving the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; and/or a satellite frame processor in the satellite for frame processing the internal code and the interleaved internal code to generate a framed internal code prior to modulation by the satellite modulator.

In at least one embodiment, the system further comprises a first receive frame processor in the receiving terminal for frame processing the demodulated inner code to generate a deframed inner code prior to decoding by the inner decoder; and/or an inner deinterleaver in the receiving terminal for deinterleaving the demodulated inner code and the deframed inner code to generate a deinterleaved inner code before decoding by the inner decoder.

In one or more embodiments, the system further includes a second reception frame processor in the reception terminal for frame-processing the restored outer code to generate a decoded outer code before decoding by the outer decoder; and/or an outer deinterleaver in the receiving terminal for deinterleaving the recovered outer code and the deframed outer code to generate a deinterleaved outer code before decoding by the outer decoder.

In at least one embodiment, the outer encoder and/or the inner encoder are operable to perform Forward Error Correction (FEC) encoding. The FEC code may have its own inner and outer codes, which are different from the inner and outer codes defined in the present disclosure. In some embodiments, the outer decoder and/or inner decoder is operable to perform FEC decoding.

The features, functions, and advantages can be achieved independently in various embodiments of the present disclosure or may be combined in yet other embodiments.

Drawings

These and other features, aspects, and advantages of the present disclosure will become better understood with regard to the following description, appended claims, and accompanying drawings where:

fig. 1 is a schematic diagram illustrating an exemplary satellite system for enhanced portion processing of satellite user data of the disclosed system in accordance with at least one embodiment of the present disclosure.

Fig. 2 is a block diagram illustrating an exemplary satellite system for enhanced portion processing of satellite user data of the disclosed system in accordance with at least one embodiment of the present disclosure.

Fig. 3 is a block diagram depicting a conventional repeater transponder satellite system architecture.

Fig. 4 is a block diagram illustrating a conventional partial processing satellite system architecture.

FIG. 5 is a block diagram depicting a conventional full processing satellite system architecture.

Fig. 6 is a block diagram illustrating a disclosed enhanced portion processing satellite architecture, according to at least one embodiment of the present disclosure.

Fig. 7A and 7B together are a flow chart illustrating the disclosed method for enhanced portion processing of satellite user data in accordance with at least one embodiment of the present disclosure.

Fig. 8 is a schematic diagram illustrating an exemplary Forward Error Correction (FEC) concatenated code for an outer code and an exemplary FEC concatenated code for an inner code processed by an enhanced portion of satellite user data by the disclosed system, in accordance with at least one embodiment of the present disclosure.

Detailed Description

The methods and apparatus disclosed herein provide an operating system for enhanced partial processing of satellite user data. In one or more embodiments, the system of the present disclosure provides a satellite architecture (see fig. 6) that allows for significant performance improvements relative to conventionally used transponders and partially processed satellite architectures (e.g., see fig. 3 and 4, respectively) without the complexity of a fully processed satellite architecture (e.g., see fig. 5). The disclosed satellite architecture (see fig. 6) preserves the encoder on the satellite, but eliminates the decoder, which is very complex and expensive. It is noted that although modern FEC decoders are complex and iterative, the corresponding encoders are very simple and achieve low cost at very high data rates.

Currently, three main satellite communication system architectures are commonly used. These are: (1) a transponder satellite system architecture (e.g., see fig. 3), (2) a partially processed satellite system architecture (e.g., see fig. 4), and (3) a fully processed satellite system architecture (e.g., see fig. 5). Each of these architectures has its own particular advantages and disadvantages.

In transponder satellite system architectures, the satellite retransmits the received signal without any significant processing, such as demodulation or decoding. An advantage of this architecture is that it can ease the burden on satellite design. However, it has the significant disadvantage that the FEC decoder needs to correct for noise from both the uplink and downlink signals. For this system, when the uplink signal is operating near the minimum required signal-to-noise ratio (SNR), the downlink signal must operate at a very high SNR in order to shut down the link, and vice versa.

In a partial processing satellite system architecture, the satellite demodulates and then remodulates the received signal. In most cases, the architecture does not have any performance improvement over the transponder satellite system architecture. The main reason is that modern FEC codes significantly depend on the confidence value of each demodulated bit provided by the demodulator, which is called "soft decision information". By introducing a demodulator on the satellite, the soft decision information of the uplink signal is lost. For uplink signal limited systems, this loss of information may result in an increase of two (2) to four (4) decibels (dB) in decoder implementation loss. It is difficult to overcome this 2-4dB loss, but this architecture is still useful in some cases. For example, when a terminal needs to communicate with a satellite and other terminals, the satellite needs a demodulator to process messages from the terminal. The architecture also supports system functions such as space-based dynamic switching and space-based dynamic resource allocation.

In a full-processing satellite system architecture, the satellite first demodulates and decodes the received signal, and then re-encodes and re-modulates the resulting signal. The architecture has the best performance of three satellite communication system architectures. Both uplink and downlink signals can operate near the theoretical limit with near error-free performance. A significant disadvantage of this architecture is that the satellite requires not only a demodulator, but also a decoder, and such a decoder needs to operate at the maximum data rate of the system. The satellite burden is considerable since modern FEC decoders work in an iterative manner, meaning that they slowly converge to the correct answer.

Another disadvantage of full-processing satellite system architectures is that the system cannot take advantage of advances in forward error correction techniques. Although FEC is implemented entirely outside of the transponder and the satellite in the partial processing architecture, it is embedded in the satellite design of the full processing satellite system architecture. To achieve performance at maximum system data rates, algorithms need to be implemented in non-reprogrammable Application Specific Integrated Circuits (ASICs). If newer code is developed, the system cannot be updated to take advantage of them.

The disclosed system for performing enhanced partial processing includes a novel architecture for satellite communication systems that provides significant performance improvements for repeaters and partial processing satellite system architectures without the complexity of a full processing satellite system architecture. A key insight for developing the system is that although modern FEC decoders are complex and iterative, the corresponding encoders are very simple to implement at very high data rates. Thus, the disclosed enhanced partial processing architecture preserves the encoder on the satellite (which is referred to as the inner encoder), but eliminates the decoder. In addition, the disclosed architecture uses an encoder (referred to as an outer encoder) in the transmitting terminal. An encoder on the satellite (i.e., an inner encoder) is used to generate the inner code and an encoder in the transmitting terminal (i.e., an outer encoder) is used to generate the outer code. The encoded data (i.e., the outer code) from the transmitting terminal is simply viewed as the input data stream to the encoder on the satellite, and in some embodiments, the two codes are effectively concatenated. Two sets of decoders in series (i.e., an inner decoder and an outer decoder) are implemented in the receiving terminal to decode the inner code and the outer code.

In the disclosed enhanced portion processing satellite system architecture, the downlink signal is completely independent of the uplink signal performance, and the system can operate near the theoretical limit, independent of the uplink signal. By not implementing the decoder on the satellite, the outer code suffers a loss of 2-4dB from losing soft decision information relative to the full processing satellite system architecture. This loss only applies to the uplink signal and may preferably provide additional 2-4dB performance on the uplink signal by other means (e.g., by providing higher uplink gain-noise temperature (G/T)) rather than adding a decoder on the satellite. The performance advantage in terms of the downlink signal power required to use a transponder or partially process a satellite system architecture depends on the specifics of the uplink and downlink signal performance and can be significant, especially where the uplink signal is limited.

The disclosed enhanced portion processing satellite system architecture is significantly different from existing architectures, with distinctive features: (1) an encoder on the satellite, but no decoder, and (2) two sets of decoders in the receiving terminal to decode the inner code generated by the inner encoder on the satellite and the outer code generated by the outer encoder in the transmitting terminal. The disclosed enhanced partial processing satellite system architecture provides measurable performance improvements for transponders and partial processing satellite system architectures, and significant improvements in satellite complexity for full processing satellite system architectures.

In particular, the disclosed satellite system architecture (see fig. 6) employs two encoders, namely one encoder in the transmitting terminal (referred to as the outer encoder) and one encoder in the satellite (referred to as the inner encoder), and two concatenated decoders in the receiving terminal (referred to as the inner decoder and the outer decoder). During operation of the disclosed system for enhanced partial processing of satellite user data, an encoder in the transmitting terminal (i.e., an inner encoder) encodes the user data to produce an inner code, and an encoder in the satellite (i.e., an outer encoder) encodes the inner code to produce an outer code. A first decoder (i.e., an inner decoder) in the receiving terminal decodes the outer code to generate an inner code, and a second decoder (i.e., an outer decoder) in the receiving terminal decodes the inner code to recover the user data.

In the following description, numerous details are set forth in order to provide a more thorough description of the system. It will be apparent, however, to one skilled in the art that the disclosed system may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to unnecessarily obscure the present system.

Embodiments of the present disclosure may be described herein in terms of functional and/or logical components and various processing steps. It should be appreciated that these components may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, embodiments of the present disclosure may employ various integrated circuit components (e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like), which may carry out a variety of functions under the control of one or more processors, microprocessors, or other control devices. In addition, those skilled in the art will appreciate that embodiments of the present disclosure may be practiced in conjunction with other components, and that the system described herein is merely one example embodiment of the disclosure.

For simplicity, conventional techniques and components related to satellite communication systems, as well as other functional aspects of the systems (and the various operational components of the systems) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the disclosure.

Fig. 1 is a schematic diagram illustrating an exemplary satellite system 100 for enhanced portion processing of satellite user data of the disclosed system in accordance with at least one embodiment of the present disclosure. In particular, as shown in fig. 1, in various embodiments, the disclosed enhanced portion processing satellite system architecture may be implemented by a transmitting terminal 120, a satellite 130, and a receiving terminal 140. In one or more embodiments of the present disclosure, the satellites 130 may employ a variety of different types of satellites, including, but not limited to, Low Earth Orbit (LEO) satellites, Medium Earth Orbit (MEO) satellites, and Geostationary Earth Orbit (GEO) satellites. In addition, in one or more embodiments, a variety of different types of terminals may be used for the transmitting terminal 120 and the receiving terminal 140, including but not limited to ground stations, mobile devices, and vehicles. A variety of different types of mobile devices may be employed for the mobile device including, but not limited to, satellite phones, wearable communication devices, tablet computers, and laptop computers. Further, a variety of different types of vehicles may be employed for the vehicle, including, but not limited to, aerial vehicles (e.g., airplanes, Unmanned Aerial Vehicles (UAVs), or other satellites), land vehicles (e.g., automobiles or tanks), and marine vehicles (e.g., ships or boats).

In fig. 1, a transmitting antenna 125 of a transmitting terminal 120 on the earth 160 is shown transmitting an uplink signal 110 toward a satellite antenna 135 on a satellite 130. Also, a satellite antenna 135 on the satellite 130 is shown transmitting a downlink signal 150 toward a receive antenna 145 on a receive terminal 140 on the earth 160. Also, in one or more embodiments, the satellite antenna 135 used to receive the uplink signal 110 may be different from the satellite antenna 135 used to transmit the downlink signal 150 (i.e., there may be more than one satellite antenna 135 on the satellite 130 to transmit the signal). Additionally, in one or more embodiments, a variety of different types of antennas may be used for the transmit antenna 125, the satellite antenna 135, and the receive antenna 145, including but not limited to reflector antennas, antenna arrays, direct radiating horn antennas, cup dipole antennas, and/or patch antennas. Also, in one or more embodiments, the uplink signals 110 and the downlink signals 150 are electromagnetic signals. Various different types of electromagnetic signals may be used for uplink signals 110 and downlink signals, including but not limited to Radio Frequency (RF) signals of various different frequency bands.

Fig. 2 is a block diagram illustrating an exemplary satellite system 200 for enhanced portion processing of satellite user data of the disclosed system in accordance with at least one embodiment of the present disclosure. In this figure, a transmitting terminal 120 is shown transmitting an uplink channel (i.e., uplink signal) 110 to a satellite 130. The satellite 130 is then shown transmitting a downlink channel (i.e., downlink signal) 150 to the receiving terminal 140. Optionally, the receiving terminal 140 may send feedback 210 to the sending terminal 120. In one or more embodiments, feedback 210 may be related to adaptive coding and modulation (e.g., to transmit more bits and/or to transmit at higher power) to improve Bit Error Rate (BER). It is noted that in one or more embodiments, the transmitting terminal 120 may be the same terminal as the receiving terminal 140, e.g., for testing purposes.

Fig. 3 is a block diagram depicting a conventional repeater transponder satellite system architecture 300. In this figure, the transmitting terminal 320 is shown to include an encoder 315 and the receiving terminal 340 is shown to include a decoder 395. Satellite 330 includes an amplifier 355 for amplifying (e.g., repeating) uplink signal 310 on downlink signal 350.

During operation of the system of fig. 3, an encoder 315 in a transmitting terminal 320 encodes (e.g., using an error correction code such as Forward Error Correction (FEC)) data 305 (e.g., user data, communication data, and/or command data) to generate an encoded code. An optional interleaver 325 in the transmitting terminal 320 may then interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the encoded code to generate an interleaved encoded code. An optional Transmit (TX) frame processor 335 in transmitting terminal 320 may frame process (e.g., insert a header into) the code and interleaved code to generate framed code. The modulator 345 in the transmitting terminal 320 then modulates the code, the interleaved code, and the framed code to generate a modulated code.

The modulated code is then transmitted via uplink signal 310 from a transmitting antenna (not shown) at transmitting terminal 320 to a satellite antenna (not shown) on satellite 330. The amplifier 355 on the satellite 330 then amplifies the modulated code to generate an amplified modulated code. The amplified modulation code is transmitted from a satellite antenna (not shown) to a receiving antenna (not shown) in the receiving terminal 340 via a downlink signal 350.

Then, the demodulator 365 in the receiving terminal 340 demodulates the amplified modulation code to generate a demodulated code. An optional Receive (RX) frame processor 375 in the receive terminal 340 may frame process the demodulated code (e.g., remove a previously inserted header) to generate a deframed code. In addition, an optional deinterleaver 385 in the receiving terminal 340 can deinterleave (e.g., undo a previously used interleaver) the demodulated coded code and the deframed coded code to generate a deinterleaved coded code. Then, the decoder 395 in the receiving terminal 340 decodes the demodulated coded code, the deframed coded code and the deinterleaved coded code to generate decoded data (i.e., recovered data) 360. Note that the decoder 395 corresponds to the encoder 315 in the transmitting terminal 320 (e.g., using the same encoding algorithm).

Fig. 4 is a block diagram illustrating a conventional partial processing satellite system architecture 400. In this figure, the transmitting terminal 420 is shown as including an encoder 415 and the receiving terminal 440 is shown as including a decoder 495. Satellite 430 includes a satellite demodulator 470 for demodulating uplink signal 410 and includes a satellite modulator 480 for modulating the demodulated uplink signal, which is then transmitted on downlink signal 450.

During operation of the system of fig. 4, an encoder 415 in a transmitting terminal 420 encodes (e.g., using an error correction code such as Forward Error Correction (FEC)) data 405 (e.g., user data, communication data, and/or command data) to generate an encoded code. An optional interleaver 425 in the transmitting terminal 420 may then interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the code to generate an interleaved code. An optional TX frame processor 435 in the transmitting terminal 420 may frame process the code and interleaved code (e.g., insert a header into the code) to generate a framed code. The TX modulator 445 in the transmitting terminal 420 then modulates the code, the interleaved code, and the framed code to generate a first modulated code.

The first modulated code is then transmitted via uplink signal 410 from a transmitting antenna (not shown) at transmitting terminal 420 to a satellite antenna (not shown) on satellite 430. A satellite demodulator 470 in satellite 430 then demodulates the first modulated code to generate a first demodulated code. Then, the satellite modulator 480 in the satellite 430 modulates the first demodulated code to generate a second modulated code. The second modulated code is transmitted via downlink signal 450 from a satellite antenna (not shown) to a receiving antenna (not shown) in receiving terminal 440.

Then, the RX demodulator 465 in the reception terminal 440 demodulates the second modulated code to generate a second demodulated code. An optional RX frame processor 475 in the receiving terminal 440 may frame process the second demodulated code (e.g., remove a previously inserted header) to generate a deframed code. In addition, an optional deinterleaver 485 in the receiving terminal 440 may deinterleave (e.g., undo the previously used interleaver) the second demodulated encoded code and the deframed encoded code to generate a deinterleaved encoded code. The decoder 495 in the receiving terminal 440 then decodes the second demodulated encoded code, the deframed encoded code, and the deinterleaved encoded code to generate decoded data (i.e., recovered data) 460. Note that the decoder 495 corresponds to the encoder 415 in the transmitting terminal 420 (e.g., using the same encoding algorithm).

Fig. 5 is a block diagram depicting a conventional all-processing satellite system architecture 500. In this figure, a transmitting terminal 520 is shown as including a TX encoder 515; satellite 530 is shown to include a satellite encoder 574 and a satellite decoder 573; and receiving terminal 540 is shown to include an RX decoder 595.

During operation of the system of fig. 5, TX encoder 515 in transmitting terminal 520 encodes (e.g., uses an error correction code such as Forward Error Correction (FEC)) data 505 (e.g., user data, communication data, and/or command data) to generate a first encoding code. An optional TX interleaver 425 in the transmitting terminal 520 may then interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the first coded code to generate a first interleaved coded code. An optional TX frame processor 535 in transmitting terminal 520 may frame (e.g., insert a header into) the first encoding code and the first interleaved encoding code to generate a first framed encoding code. Then, the TX modulator 545 in the transmitting terminal 520 modulates the first coding code, the first interleaved coding code, and the first framed coding code to generate a first modulated coding code.

The first modulated encoded code is then transmitted via uplink signal 510 from a transmitting antenna (not shown) at transmitting terminal 520 to a satellite antenna (not shown) on satellite 530. The satellite demodulator 570 in the satellite 530 then demodulates the first modulated code to generate a first demodulated code.

An optional first satellite frame processor 571 in the satellite 530 may then frame process (e.g., insert a header into the code) the first demodulated encoded code to generate a first deframed encoded code. An optional satellite deinterleaver 572 in the satellite 530 may deinterleave (e.g., undo the previously used interleaver) the first demodulated encoded code and the first deframed encoded code to generate a first deinterleaved encoded code.

Then, the satellite decoder 573 in the satellite 530 decodes the first demodulated encoded code, the first deframed encoded code, and the first deinterleaved encoded code to generate a first decoded code. Note that the satellite decoder 573 corresponds to the TX encoder 515 in the transmitting terminal 520 (e.g., using the same encoding algorithm). The first decoded code is then encoded (e.g., using an error correction code such as Forward Error Correction (FEC)) by satellite encoder 574 in satellite 530 to generate a second encoded code.

An optional satellite interleaver 576 in satellite 530 may interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the second encoded code to generate a second interleaved encoded code. Also, an optional second satellite frame processor 577 in the satellite 530 may frame the second encoded code and the second interleaved encoded code (e.g., insert a header into the code) to generate a second framed encoded code. The satellite modulator 580 in the satellite 530 then encodes the second code, the second interleaved code, and the second framed code to generate a second modulated code. The second modulated code is transmitted via downlink signal 550 from a satellite antenna (not shown) to a receiving antenna (not shown) in receiving terminal 540.

RX demodulator 565 in receiving terminal 540 then demodulates the second modulated code to generate a second demodulated code. An optional RX frame processor 575 in the receiving terminal 540 may frame process the second demodulated code (e.g., remove the previously inserted header) to generate a second deframed code. Additionally, an optional RX deinterleaver 485 in the receiving terminal 540 may deinterleave (e.g., undo a previously used interleaver) the second demodulated encoded code and the second deframed encoded code to generate a second deinterleaved encoded code. The RX decoder 595 in the receiving terminal 540 then decodes the second demodulated encoded code, the second de-framed encoded code, and the second de-interleaved encoded code to generate decoded data (i.e., recovered data) 560. Note that RX decoder 595 corresponds to (e.g., uses the same encoding algorithm as) satellite encoder 574 in satellite 530.

Fig. 6 is a block diagram illustrating a disclosed enhanced portion processing satellite architecture 600, in accordance with at least one embodiment of the present disclosure. In this figure, transmitting terminal 120 is shown to include outer encoder 615, and receiving terminal 140 is shown to include inner decoder 695 and outer decoder 698. The satellite 130 includes an inner encoder 671 and does not have any decoder.

During operation of the system of fig. 6, outer encoder 615 in transmitting terminal 120 encodes (e.g., using an error correction code such as Forward Error Correction (FEC)) data 605 (e.g., user data, communication data, and/or command data) to generate outer code 601. It is noted that outer encoder 615 may use a variety of different types of error correction codes, including but not limited to FEC codes, such as concatenated FEC codes (e.g., see fig. 8). These FEC codes may have their own inner and outer codes (not shown) that are different from the inner and outer codes defined in this disclosure.

An optional outer interleaver 625 in the transmitting terminal 120 may then interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the outer code 601 to generate an interleaved outer code 602. An optional Transmit (TX) frame processor 635 in the transmitting terminal 120 may frame (e.g., insert a header into the code) the outer code 601 and the interleaved outer code 602 to generate a framed outer code 603. It is noted that TX frame processor 635 is referred to as a TX frame processor because it is a frame processor located within transmitting terminal 120.

Then, the TX modulator 645 in the transmitting terminal 120 modulates the external code 601, the interleaved external code 602, and the framed external code 603 to generate a modulated external code 604. TX modulator 645 may employ a variety of different modulation schemes including, but not limited to, modulation schemes that vary frequency, amplitude, and/or phase. Similar to

TX frame processors

635, 645 are referred to as TX modulators because they are modulators located within transmitting terminal 120.

The modulated outer code 604 is then transmitted via the uplink signal 110 from the transmit antenna (see 125 in fig. 1) at the transmitting terminal 120 to the satellite antenna (see 135 in fig. 1) on the satellite 130. The satellite demodulator 670 in the satellite 130 then demodulates the modulated outer code 604 to generate the demodulated outer code 617. Satellite demodulator 670 corresponds to TX modulator 645 in transmitting terminal 120 (e.g., using the same modulation scheme).

An inner encoder 671 in the satellite 130 then encodes (e.g., using an error correction code such as Forward Error Correction (FEC)) the demodulated outer code 617 to generate the inner code 606. Inner encoder 671 may use a variety of different types of error correction codes, including but not limited to FEC codes, such as concatenated FEC codes (e.g., see fig. 8). These FEC codes may have their own inner and outer codes (not shown) that are different from the inner and outer codes defined in this disclosure.

An optional inner interleaver 672 in the satellite 130 may interleave (e.g., using an interleaver such as a rectangular interleaver, a convolutional interleaver, a random interleaver, and/or an S-random interleaver) the inner code 606 to generate an interleaved inner code 607. Also, an optional satellite frame processor 673 in the satellite 130 may frame the inner code 606 and the interleaved inner code 607 (e.g., insert a header into the code) to generate the framed inner code 608. The internal code 606, the interleaved internal code 607, and the framed internal code 608 are then modulated by a satellite modulator 680 in the satellite 130 to generate a modulated internal code 609. It is noted that the satellite modulator 680 may employ a variety of different modulation schemes, including but not limited to modulation schemes that vary frequency, amplitude, and/or phase.

The modulated inner code 609 is transmitted from a satellite antenna (refer to 135 in fig. 1) to a receiving antenna (refer to 145 in fig. 1) in the receiving terminal 140 via the downlink signal 150. Then, a Reception (RX) demodulator 665 in the reception terminal 140 demodulates the modulated inner code 609 to generate a demodulated inner code 610. It is noted that RX demodulator 665 is referred to as a RX demodulator because it is a modulator located within receive terminal 140. RX demodulator 665 corresponds to satellite modulator 680 in satellite 130 (e.g., using the same modulation scheme as satellite modulator 680 in satellite 130).

An optional first RX frame processor 675 in the receiving terminal 140 can frame the demodulated inner code 610 (e.g., undo the previously used header) to generate a deframed inner code 611. The first RX frame processor 675 is referred to as the first RX frame processor because it is a frame processor located within the receiving terminal 140. In addition, an optional inner deinterleaver 685 in the receiving terminal 140 can deinterleave (e.g., remove the previously inserted interleaver) the demodulated inner code 610 and the deframed inner code 611 to generate a deinterleaved inner code 612.

The inner decoder 695 in the receiving terminal 140 then decodes the demodulated inner code 610, the deframed inner code 611, and the deinterleaved inner code 612 to generate the recovered outer code 613. Note that inner decoder 695 corresponds to (e.g., uses the same encoding algorithm) inner encoder 671 in satellite 130.

An optional second RX frame processor 696 in the receiving terminal 140 may then frame process the recovered outer code 613 (e.g., insert a header into the code) to generate a deframed outer code 614. Similar to the first RX frame processor 675, the second RX frame processor 696 is referred to as the second RX frame processor 696 because it is a frame processor located within the receiving terminal 140.

An optional outer deinterleaver 697 in the receiving terminal 140 may deinterleave (e.g., undo the previously used interleaver) the recovered outer code 613 and the deframed outer code 614 to generate a deinterleaved outer code 616. The outer decoder 698 in the receiving terminal 140 then decodes the recovered outer code 613, the deframed outer code 614 and the deinterleaved outer code 616 to generate recovered data 660. Note that the outer decoder 698 corresponds to the outer encoder 615 in the transmitting terminal 120 (e.g., using the same encoding algorithm).

Fig. 7A and 7B together are a flow chart illustrating the disclosed method for enhanced portion processing of satellite user data in accordance with at least one embodiment of the present disclosure. At the start 705 of the method, an outer encoder in the transmitting terminal encodes the data to generate an outer code 710. An optional transmit interleaver in the transmitting terminal may interleave the outer code to generate an interleaved outer code 715. Also, an optional transmit frame processor in the transmitting terminal may frame the outer code and the interleaved outer code to generate framed outer code 720. The transmit modulator in the transmitting terminal then modulates the outer code, the interleaved outer code, and the framed outer code to generate a modulated outer code 725.

The satellite demodulator in the satellite then demodulates the modulated outer code to generate a demodulated outer code 730. An inner encoder in the satellite then encodes the demodulated outer code to generate an inner code 735. An optional satellite interleaver in the satellite may interleave the inner code to generate interleaved inner code 740. An optional satellite frame processor in the satellite may frame process the inner code and the interleaved inner code to generate a framed inner code 745. The satellite modulator in the satellite then modulates the internal code, the interleaved internal code, and the framed internal code to generate a modulated internal code 750.

The receive demodulator in the receiving terminal then demodulates the modulated inner code to generate a demodulated inner code 755. An optional first receive frame processor in the receiving terminal may then frame process the demodulated inner code to generate a deframed inner code 760. An optional inner deinterleaver in the receiving terminal may deinterleave the demodulated inner codes and the deframed inner codes to generate deinterleaved inner codes 765. Then, the inner decoder in the receiving terminal decodes the demodulated inner code, the deframed inner code, and the deinterleaved inner code to generate a recovered outer code 770. An optional second receive frame processor in the receiving terminal may frame process the recovered outer code to produce a deframed outer code 775. An optional outer deinterleaver in the receiving terminal may deinterleave the recovered outer code and the outer code of the deframed to generate a deinterleaved outer code 780. An outer decoder in the receiving terminal decodes the recovered outer code, the deframed outer code, and the deinterleaved outer code to generate recovered data 785. The method then ends 790.

Fig. 8 is a schematic diagram illustrating an exemplary Forward Error Correction (FEC) concatenated code of the outer code 601 of fig. 6 and an exemplary FEC concatenated code of the inner code 606 of fig. 6 used by the disclosed system for enhanced portion processing of satellite user data, in accordance with at least one embodiment of the present disclosure. In one or more embodiments, during operation of the disclosed system, data (e.g., user data) 605 (see also fig. 6) is encoded by outer encoder 615 (see fig. 6) using an FEC concatenated coding scheme to generate outer code 601. In this figure, the generated outer code 601 is shown to contain (1) a Header (HDR), which contains header information, followed by (2) the original user data, followed by (3) parity, which includes a sequence of parity bits. Also during operation of the disclosed system, the outer code 601 (e.g., in the form of demodulated outer code 617) is encoded by an inner encoder 671 (see fig. 6) utilizing an FEC concatenated coding scheme to generate the inner code 606. In this figure, the generated inner code 606 is shown to contain (1) a Header (HDR) in the outer code 601 (which contains header information), followed by (2) a subsequent Header (HDR) containing additional header information, followed by (3) the original user data, followed by (4) the parity in the outer code 601 (which includes the sequence of parity bits), followed by (5) the additional parity (which includes the sequence of parity bits).

Furthermore, the present disclosure includes embodiments according to:

item 1: a method for processing data, the method comprising: encoding data with an outer encoder in a transmitting terminal to generate an outer code; modulating one of the external code, the interleaved external code, and the framed external code with a transmit modulator in the transmitting terminal to generate a modulated external code; demodulating the modulated outer code with a satellite demodulator in the satellite to generate a demodulated outer code; encoding the demodulated outer code with an inner encoder in the satellite to generate an inner code; modulating one of the inner code, the interleaved inner code, and the framed inner code with a satellite modulator in the satellite to generate a modulated inner code; demodulating the modulated inner code with a reception demodulator in the receiving terminal to generate a demodulated inner code; decoding one of the demodulated inner code, the deframed inner code and the deinterleaved inner code with an inner decoder in the receiving terminal to generate a recovered outer code; and decoding one of the recovered outer code, the deframed outer code, and the deinterleaved outer code with an outer decoder in the receiving terminal to generate recovered data.

Item 2: the method of item 1, wherein the method further comprises at least one of: interleaving, by an outer interleaver in a transmitting terminal, the outer code to generate an interleaved outer code before modulation by a transmit modulator; or frame processing one of the outer code and the interleaved outer code by a transmit frame processor in the transmitting terminal to generate a framed outer code prior to modulation by the transmit modulator.

Item 3: the method of item 1, wherein the method further comprises at least one of: interleaving, by a satellite interleaver in the satellite, the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; and/or the inner code and the interleaved inner code are frame processed by a satellite frame processor in the satellite to generate a framed inner code prior to modulation by the satellite modulator.

Item 4: the method of item 1, wherein the method further comprises at least one of: frame-processing the demodulated inner code by a first receive frame processor in the receiving terminal to generate a deframed inner code before decoding by the inner decoder; or deinterleaves one of the demodulated inner code and the inner code of the deframed frame by an inner deinterleaver in the receiving terminal to generate a deinterleaved inner code before decoding by the inner decoder.

Item 5: the method of item 1, wherein the method further comprises at least one of: frame processing the recovered outer code by a second receive frame processor in the receiving terminal to produce a deframed outer code before decoding by the outer decoder; or deinterleaving, by an outer deinterleaver in the receiving terminal, one of the recovered outer code and the deframed outer code to generate a deinterleaved outer code before decoding by the outer decoder.

Item 6: the method of item 1, wherein the data is at least one of communication data, command data, and user data.

Item 7: the method of item 1, wherein at least one of the outer encoder and inner encoder performs Forward Error Correction (FEC) encoding.

Item 8: the method of item 1, wherein at least one of the outer decoder and inner decoder performs FEC decoding.

Item 9: the method of item 1, wherein the outer decoder corresponds to an outer encoder and the inner decoder corresponds to an inner encoder.

Item 10: the method of item 1, wherein the transmitting terminal and receiving terminal are each a ground station, a mobile device, or a vehicle.

Item 11: a system for processing data, the system comprising: an outer encoder in the transmitting terminal that encodes the data to generate an outer code; a transmit modulator in the transmitting terminal that modulates one of the outer code, the interleaved outer code, and the framed outer code to generate a modulated outer code; a satellite demodulator in the satellite that demodulates the modulated outer code to generate a demodulated outer code; an inner encoder in the satellite that encodes the demodulated outer code to generate an inner code; a satellite modulator in the satellite that modulates one of the internal code, the interleaved internal code, and the framed internal code to generate a modulated internal code; a reception demodulator in the reception terminal that demodulates the modulated inner code to generate a demodulated inner code; an inner decoder in the receiving terminal decoding one of the demodulated inner code, the deframed inner code, and the deinterleaved inner code to generate a recovered outer code; an outer decoder in the receiving terminal is utilized that decodes one of the recovered outer code, the unframed outer code, and the deinterleaved outer code to generate recovered data.

Item 12: the system of item 11, wherein the system further comprises at least one of: an outer interleaver in the transmitting terminal for interleaving the outer code to generate an interleaved outer code prior to modulation by the transmit modulator; or a transmit frame processor in the transmitting terminal for frame processing one of the outer code and the interleaved outer code to generate a framed outer code prior to modulation by the transmit modulator.

Item 13: the system of item 11, wherein the system further comprises at least one of: a satellite interleaver in the satellite for interleaving the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; or a satellite frame processor in the satellite for frame processing one of the inner code and the interleaved inner code to generate a framed inner code prior to modulation by the satellite modulator.

Item 14: the system of item 11, wherein the system further comprises at least one of: a first reception frame processor in the reception terminal for frame-processing the demodulated inner code to generate a deframed inner code before decoding by the inner decoder; or an inner deinterleaver in the receiving terminal for deinterleaving one of the demodulated inner code and the inner code of the deframed frame to generate a deinterleaved inner code before decoding by the inner decoder.

Item 15: the system of item 11, wherein the system further comprises at least one of: a second receive frame processor in the receiving terminal for frame processing the recovered outer code to produce a deframed outer code before decoding by the outer decoder; or an outer deinterleaver in the receiving terminal for deinterleaving one of the recovered outer code and the deframed outer code to generate a deinterleaved outer code before decoding by the outer decoder.

Item 16: the system of item 11, wherein the data is at least one of communication data, command data, and user data.

Item 17: the system of item 11, wherein at least one of the outer encoder and inner encoder is operable to perform Forward Error Correction (FEC) encoding.

Item 18: the system of item 11, wherein at least one of the outer decoder and the inner decoder is operable to perform FEC decoding.

Item 19: the system of item 11, wherein the outer decoder corresponds to the outer encoder and the inner decoder corresponds to the inner encoder.

Item 20: the system of item 11, wherein the transmitting terminal and receiving terminal are each a ground station, a mobile device, or a vehicle.

While particular embodiments have been illustrated and described, it should be understood that the above discussion is not intended to limit the scope of these embodiments. Although embodiments and variations of many aspects of the present invention have been disclosed and described herein, such disclosure is provided for purposes of illustration and description only. Accordingly, various changes and modifications may be made without departing from the scope of the claims.

Where the above-described methods indicate certain events occurring in a particular order, those of ordinary skill in the art having the benefit of this disclosure will recognize that the ordering may be modified and that such modifications are in accordance with the variations of the disclosure. In addition, where possible, portions of the methods may be performed concurrently in parallel processing, as well as performed sequentially. Additionally, more or less parts of the method may be performed.

Accordingly, the embodiments are intended to illustrate alternatives, modifications, and equivalents that may fall within the scope of the claims.

Although certain illustrative embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the true spirit and scope of the art disclosed. There are many other examples in the art, each differing from the others only in details. Accordingly, the disclosed technology is intended to be limited only to the extent required by the appended claims and the rules and principles of applicable law.

Claims

1. A method for processing data, the method comprising:

encoding data with an outer encoder in a transmitting terminal to generate an outer code;

modulating the outer code with a transmit modulator in the transmitting terminal to generate a modulated outer code;

demodulating the modulated outer code with a satellite demodulator in a satellite to generate a demodulated outer code;

encoding the demodulated outer code with an inner encoder in the satellite to generate an inner code;

modulating the inner code with a satellite modulator in the satellite to generate a modulated inner code;

demodulating the modulated inner code with a reception demodulator in a receiving terminal to generate a demodulated inner code;

decoding the demodulated inner code with an inner decoder in the receiving terminal to generate a recovered outer code; and is

Decoding the recovered outer code with an outer decoder in the receiving terminal to generate recovered data,

wherein the outer encoder utilizes a forward error correction concatenated coding scheme to generate the outer code and/or the inner encoder utilizes a forward error correction concatenated coding scheme to generate the inner code.

2. The method of claim 1, wherein the method further comprises at least one of:

interleaving, by an outer interleaver in the transmitting terminal, the outer code to generate an interleaved outer code prior to modulation by the transmit modulator; and

frame processing one of the outer code and the interleaved outer code by a transmit frame processor in the transmitting terminal to generate a framed outer code prior to modulation by the transmit modulator,

wherein the modulating comprises modulating the interleaved outer code or the framed outer code with a transmit modulator in the transmitting terminal to generate the modulated outer code.

3. The method of claim 1, wherein the method further comprises at least one of:

interleaving, by a satellite interleaver in the satellite, the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; and

frame processing one of the inner code and the interleaved inner code by a satellite frame processor in the satellite to generate a framed inner code prior to modulation by the satellite modulator,

wherein the modulating comprises modulating the interleaved inner code or the framed inner code with the satellite modulator in the satellite to generate the modulated inner code.

4. The method of claim 1, wherein the method further comprises at least one of:

frame processing the demodulated inner code by a first receive frame processor in the receiving terminal to generate a deframed inner code prior to decoding by the inner decoder; and

deinterleaving, by an inner deinterleaver in the receiving terminal, one of the demodulated inner code and the inner code of the deframed frame to generate a deinterleaved inner code before decoding by the inner decoder,

wherein the decoding comprises decoding the unframed inner code or the deinterleaved inner code with the inner decoder in the receiving terminal to generate the recovered outer code.

5. The method of claim 4, wherein the method further comprises at least one of:

frame processing the recovered outer code by a second receive frame processor in the receiving terminal to produce a deframed outer code prior to decoding by the outer decoder; and

deinterleaving, by an outer deinterleaver in the receiving terminal, one of the recovered outer code and the deframed outer code to generate a deinterleaved outer code before decoding by the outer decoder,

wherein the decoding comprises decoding the outer code of the de-framed or the de-interleaved outer code with the outer decoder in the receiving terminal to generate the recovered data.

6. A system for processing data, the system comprising:

an outer encoder in a transmitting terminal, the outer encoder to encode data to generate an outer code;

a transmit modulator in the transmitting terminal, the transmit modulator to modulate the outer code to generate a modulated outer code;

a satellite demodulator in the satellite for demodulating the modulated external code to generate a demodulated external code;

an inner encoder in the satellite for encoding the demodulated outer code to generate an inner code;

a satellite modulator in the satellite to modulate the internal code to generate a modulated internal code;

a reception demodulator in the reception terminal for demodulating the modulated inner code to generate a demodulated inner code;

an inner decoder in the receiving terminal for decoding the demodulated inner code to generate a recovered outer code; and

an outer decoder in the receiving terminal for decoding the recovered outer code to generate recovered data,

wherein the outer encoder is configured to generate the outer code using a forward error correction concatenated coding scheme and/or the inner encoder is configured to generate the inner code using a forward error correction concatenated coding scheme.

7. The system of claim 6, wherein the system further comprises at least one of:

an outer interleaver in the transmitting terminal, the outer interleaver for interleaving the outer code to generate an interleaved outer code prior to modulation by the transmit modulator; and

a transmit frame processor in the transmitting terminal for frame processing one of the outer code and the interleaved outer code to generate a framed outer code prior to modulation by the transmit modulator,

wherein the transmit modulator in the transmitting terminal is further configured to modulate the interleaved outer code or the framed outer code to generate the modulated outer code.

8. The system of claim 6, wherein the system further comprises at least one of:

a satellite interleaver in the satellite for interleaving the inner code to generate an interleaved inner code prior to modulation by the satellite modulator; and

a satellite frame processor in the satellite for frame processing one of the inner code and the interleaved inner code to generate a framed inner code prior to modulation by the satellite modulator,

wherein the satellite modulator in the satellite is further configured to modulate the interleaved inner code or the framed inner code to generate the modulated inner code.

9. The system of claim 6, wherein the system further comprises at least one of:

a first receive frame processor in the receiving terminal for frame processing the demodulated inner code to generate a deframed inner code prior to decoding by the inner decoder; and

an inner deinterleaver in the receiving terminal for deinterleaving one of the demodulated inner code and the inner code of the deframed frame to generate a deinterleaved inner code before decoding by the inner decoder,

wherein the inner decoder in the receiving terminal is further configured to decode the unframed inner code or the deinterleaved inner code to generate the recovered outer code.

10. The system of claim 9, wherein the system further comprises at least one of:

a second receive frame processor in the receive terminal for frame processing the recovered outer code to produce a deframed outer code prior to decoding by the outer decoder; and

an outer deinterleaver in the receiving terminal for deinterleaving one of the recovered outer code and the outer code of the deframed frame to generate a deinterleaved outer code before decoding by the outer decoder,

wherein the outer decoder in the receiving terminal is further configured to decode the de-framed outer code or the de-interleaved outer code to generate the recovered data.