CN110098200A - Dot structure and its manufacturing method - Google Patents
Dot structure and its manufacturing method Download PDFInfo
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- CN110098200A CN110098200A CN201910370833.XA CN201910370833A CN110098200A CN 110098200 A CN110098200 A CN 110098200A CN 201910370833 A CN201910370833 A CN 201910370833A CN 110098200 A CN110098200 A CN 110098200A
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- contact hole
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000012774 insulation material Substances 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 description 27
- 239000010408 film Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 230000012447 hatching Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000717 retained effect Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000233 poly(alkylene oxides) Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000570 polyether Chemical class 0.000 description 1
- 229920001470 polyketone Chemical class 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 125000001501 propionyl group Chemical group O=C([*])C([H])([H])C([H])([H])[H] 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a kind of dot structures, including substrate, active member, the first insulating pattern layer, the second insulating pattern layer and pixel electrode.Active member is set on substrate.First insulating pattern layer is set on active member, and has the first contact hole.Second insulating pattern layer is set on the first insulating pattern layer, and has the second contact hole.Pixel electrode is set on the second insulating pattern layer, and is electrically connected by the first electrode of the first contact hole and the second contact hole and active member.The side wall of the first insulating pattern layer at the first contact hole and bottom surface have the first angle α.The side wall of the second insulating pattern layer at the second contact hole and bottom surface have the second angle β.Second angle β is less than the first angle α.In addition, the manufacturing method of above-mentioned dot structure is also suggested.
Description
Technical field
The invention relates to a kind of dot structure and its manufacturing methods.
Background technique
Etching technique is often applied to display panel and semiconductor related industry, can be divided mainly into wet etching (Wet
Etching) with dry-etching (Dry Etching).In general, wet etching is isotropic etching, and dry-etching is non-
Isotropic etching.The processing time of isotropic etching is short compared with the processing time of anisotropic etching.However, utilizing isotropic etching
After patterning a lower film layer, it will appear apparent undercutting (undercut) between the lower film layer and upper film layer that are patterned and ask
Topic, and then influence the display quality of display panel and/or the reliability of electronic component.Therefore, needing one kind at present can solve
State the technical solution of problem.
Summary of the invention
The present invention provides a kind of dot structure, excellent performance.
The present invention provides a kind of manufacturing method of dot structure, can produce the dot structure of excellent performance.
A kind of dot structure of the invention, including substrate, active member, the first insulating pattern layer, the second insulating pattern layer
And pixel electrode.Active member is set on substrate.First insulating pattern layer is set on active member, and has first to connect
Touch window.First contact hole is overlapped in the first electrode of active member.Second insulating pattern layer is set on the first insulating pattern layer,
And there is the second contact hole.Second contact hole is overlapped in the first electrode of active member.Pixel electrode is set to the second insulation figure
In pattern layer, and it is electrically connected by the first electrode of the first contact hole and the second contact hole and active member.In the first contact hole
The first insulating pattern layer at place has side wall and bottom surface.The bottom surface of the side wall of first insulating pattern layer and the first insulating pattern layer
With the first angle α.The second insulating pattern layer at the second contact hole has side wall and bottom surface.Second insulating pattern layer
The bottom surface of side wall and the second insulating pattern layer has the second angle β.Second angle β is less than the first angle α.
The manufacturing method of a kind of dot structure of the invention, comprising: in forming active member on substrate；In on active member
Form the first insulation material layer；In forming the second insulation material layer on the first insulation material layer；It is mask patterning using half mode
Second insulation material layer, to form second insulating layer, wherein second insulating layer has opening；Using second insulating layer as mask pattern
Change the first insulation material layer, to form the first insulating pattern layer and the second insulating pattern layer, wherein the first insulating pattern layer has
First contact hole；Second insulating pattern layer has the second contact hole, and the first contact hole and the second contact hole are overlapped in active member
First electrode；And first insulating pattern layer have side wall and bottom surface, the side wall and the first insulating pattern of the first insulating pattern layer
The bottom surface of layer has the first angle α, and the second insulating pattern layer has side wall and bottom surface, the side wall and second of the second insulating pattern layer
The bottom surface of insulating pattern layer has the second angle β, and the α of β < 0.5；And pixel electrode is formed, pass through the first contact hole and second
The first electrode of contact hole and active member is electrically connected.
The manufacturing method of a kind of dot structure of the invention, comprising: in forming active member on substrate；In on active member
Form the first insulation material layer；In forming the second insulation material layer on the first insulation material layer；The second insulation material layer is patterned,
And prebake conditions processing procedure is carried out to the second insulation material layer, to form second insulating layer, wherein second insulating layer has opening, opening
It is overlapped in the first electrode of active member；With second insulating layer for mask patterning first insulation material layer, to form first absolutely
Edge pattern layer, wherein the first insulating pattern layer has the first contact hole, the first contact hole of the first insulating pattern layer is overlapped in master
The first electrode of dynamic element, the first insulating pattern layer at the first contact hole have side wall；It is dried after being carried out to second insulating layer
It is baked journey, to form the second insulating pattern layer, wherein the second insulating pattern layer covers the side wall of the first insulating pattern layer, and second
Insulating pattern layer has the second contact hole；And pixel electrode is formed, the second contact hole and active by the second insulating pattern layer
The first electrode of element is electrically connected.
Based on above-mentioned, in the dot structure and its manufacturing method of one embodiment of the invention, by the first insulating pattern layer
The bottom surface of side wall and the first insulating pattern layer has the first angle α, the side wall of the second insulating pattern layer and the second insulating pattern layer
Bottom surface there is the second angle β, and the second angle β is less than the first angle α.The dot structure of one embodiment of the invention is less prone to
Undercutting problem.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Figure 1A is the upper schematic diagram according to the dot structure of one embodiment of the invention.
Figure 1B is the diagrammatic cross-section according to the hatching line A-A ' of Figure 1A dot structure being painted.
Fig. 2A to Fig. 2 E is the manufacturing process diagrammatic cross-section of the regional area 10a of the dot structure 10 of Figure 1B.
Fig. 3 A is the upper schematic diagram according to the dot structure of another embodiment of the present invention.
Fig. 3 B is the diagrammatic cross-section according to the hatching line B-B ' and hatching line C-C ' of Fig. 3 A dot structure being painted.
Fig. 4 A to Fig. 4 C is the manufacturing process diagrammatic cross-section of the regional area 20a of the dot structure 20 of Fig. 3 B.
Fig. 5 A is the upper schematic diagram according to the dot structure of another embodiment of the present invention.
Fig. 5 B is the diagrammatic cross-section according to the hatching line D-D ' of Fig. 5 A dot structure being painted.
Fig. 6 A to Fig. 6 D is the manufacturing process diagrammatic cross-section of the regional area 30a of the dot structure 30 of Fig. 5 B.
Wherein, appended drawing reference:
10,20,30: dot structure
10a, 20a, 30a: region
100: substrate
110: active member
112: grid
113: gate insulation layer
114: semiconductor pattern
116: first electrode
116a: first part
116b: second part
116c: lug boss
116d, 124d: top surface
118: second electrode
120: the first insulation material layers
A part of 120a: the first insulation material layer
124,126: the first insulating pattern layer
124a, 126a: the first contact hole
124b, 126b, 144b, 146b, 148b: side wall
124c, 126c, 144c, 146c, 148c: bottom surface
124e: the first boundary side
126d: inner recess
126e, 148d: boundary side
130: chromatic filter layer
132,142c, 146a: opening
140: the second insulation material layers
140a, 142a, 144-1: first part
140b, 142b, 144-2: second part
140c: Part III
144a, 148a: the second contact hole
144d: the second boundary side
142,146: second insulating layer
144,148: the second insulating pattern layer
150: pixel electrode
170: the first signal wires
172: common electrode
172 ': island-shaped pattern
180: second signal line
200,210: half mode exposure mask
202,212,222: opaque region
204,214: partially transparent region
206,224: transparent region
220: exposure mask
A-A ', B-B ', C-C ', D-D ': hatching line
G: annular gap
L: distance
Z: vertical direction
α: the first angle
β: the second angle
Specific embodiment
The present invention is hereinafter described more fully with reference to the accompanying drawings, exemplary implementation the invention is shown in the accompanying drawings
Example.As the skilled person will recognize, described embodiment can be modified in a variety of ways, without departing from
The spirit or scope of the present invention.
In the accompanying drawings, for the sake of clarity, it is exaggerated the thickness in layer, film, panel, region etc..Throughout the specification, phase
Same appended drawing reference indicates identical element.It should be appreciated that ought such as layer, film, region or substrate element be referred to as another
It when element "upper" or " being connected to " another element, can be connect directly on another element or with another element, or intermediate
Element can be there is also.On the contrary, when element is referred to as " directly on another element " or when " being directly connected to " another element, no
There are intermediary elements.As it is used herein, " connection " can refer to physics and/or electric connection.Furthermore " electric connection " or
" coupling " system can there are other elements between two element.
In addition, the relative terms of such as "lower" or " bottom " and "upper" or " top " can be used to describe herein a member
The relationship of part and another element, as shown in the figure.It should be appreciated that relative terms are intended to include other than orientation shown in figure
The different direction of device.For example, being described as be in the member of the "lower" side of other elements if the device in an attached drawing is overturn
Part will be oriented at the "upper" side of other elements.Therefore, exemplary term "lower" may include the orientation of "lower" and "upper", depend on
In the specific orientation of attached drawing.Similarly, if the device in an attached drawing is overturn, be described as be in other elements " lower section " or
The element of " lower section " will be oriented in other elements " top ".Therefore, exemplary term " above " or " following " may include
Above and below orientation.
" about " used herein, " approximation " or " substantial " includes described value and determines in those of ordinary skill in the art
Particular value acceptable deviation range in average value, it is contemplated that the spy of the measurement and error relevant to measurement that are discussed
Fixed number amount (that is, limitation of measuring system).For example, " about " can indicate in one or more standard deviations of described value, or
± 30%, in ± 20%, ± 10%, ± 5%.Furthermore " about " used herein, " approximation " or " substantial " can be according to optical
Matter, etching property or other properties to select more acceptable deviation range or standard deviation, and can not have to a standard deviation
It is applicable in whole property.
Exemplary embodiment is described herein with reference to the sectional view of the schematic diagram as idealized embodiments.It therefore, can be with
Anticipate the change in shape of the diagram of the result as such as manufacturing technology and/or (and/or) tolerance.Therefore, as described herein
Embodiment should not be construed as limited to the specific shape in region as shown here, but including such as shape caused by manufacturing
Deviation.It can have coarse and/or nonlinear characteristic for example, being illustrated and described as flat region usually.It is sharp shown in addition,
Angle can be round.Therefore, region shown in figure is substantially schematical, and their shape is not intended to and shows area
The accurate shape in domain, and not be intended to limit the scope of the claims.
Unless otherwise defined, all terms (including technical and scientific term) used herein have leads with belonging to the present invention
The normally understood identical meaning of the those of ordinary skill in domain.It will be further appreciated that such as in usually used dictionary
Those of definition term should be interpreted as having and their meanings in the relevant technologies and context of the invention are consistent
Meaning, and will not be interpreted Utopian or excessively formal meaning, unless clearly definition so herein.
Figure 1A is the upper schematic diagram according to the dot structure of one embodiment of the invention.Figure 1B is the hatching line A- according to Figure 1A
The diagrammatic cross-section for the dot structure that A ' is painted.Figure 1A omits the substrate 100, gate insulation layer 113 and chromatic filter layer 130 of Figure 1B
Be painted.Fig. 2A to Fig. 2 E is the manufacturing process diagrammatic cross-section of the regional area 10a of the dot structure 10 of Figure 1B.Cooperate below
Figure 1A, Figure 1B and Fig. 2A to Fig. 2 E illustrate the present invention the manufacturing process of the dot structure 10 of an embodiment.
Figure 1B is please referred to, firstly, providing substrate 100.In the present embodiment, substrate 100 is, for example, hard substrate (rigid
substrate).However, the invention is not limited thereto, in other embodiments, substrate 100 is also possible to flexible substrate
(flexible substrate).For example, the material of above-mentioned hard substrate can be glass, quartz or other appropriate materials
Material；The material of above-mentioned flexible substrate can be plastic cement or other suitable materials.
Then, in formation active member 110 on substrate 100.In the present embodiment, active member 110 include grid 112,
Semiconductor pattern 114, first electrode 116 and second electrode 118.For example, Figure 1A and Figure 1B is please referred to, in the present embodiment
In, it can be prior to forming the first conductive layer on substrate 100, the first conductive layer may include grid 112, sharing of separating with grid 112
Electrode 172 and the first signal wire 170 being connect with grid 112.Figure 1B is please referred to, then, gate insulation layer 113 is formed, to cover
Lid grid 112 and common electrode 172.Then, semiconductor pattern 114 is formed on gate insulation layer 113.Then, in semiconductor figure
The second conductive layer is formed in case 114.Second conductive layer includes first electrode 116, second electrode 118 and second signal line 180.The
One electrode 116 and second electrode 118 separate in structure each other and twoth area electric connections different from semiconductor pattern 114 respectively.
Second electrode 118 is connect with second signal line 180.
Figure 1A and Figure 1B is please referred to, the first electrode 116 of active member 110 includes first part 116a and second part
116b, first part 116a is Chong Die with semiconductor pattern 114, and second part 116b connect with first part 116a and by first
116a is divided to extend outwardly.Grid 112, semiconductor pattern 114, first electrode 116 and second electrode 118 form active member 110
At least part, such as, but not limited to: thin film transistor (TFT).It should be noted that at least one of above-mentioned formation active member 110
The method divided is to form bottom grid film transistor as example.However, the invention is not limited thereto, in other embodiments
In, at least part of active member 110 is also possible to other types of thin film transistor (TFT), and forms it otherwise.
Figure 1B is please referred to, then, in forming the first insulating pattern layer 124 and the second insulation figure on the second conductive layer above-mentioned
Pattern layer 144 cooperates Fig. 2A to Fig. 2 D to illustrate it below.
Figure 1B and Fig. 2A is please referred to, firstly, in forming the first insulation material layer 120 on active member 110.First insulation material
The bed of material 120 covers active member 110.In the present embodiment, the material of the first insulation material layer 120 include inorganic material (such as:
Silica, silicon nitride, silicon oxynitride, other suitable materials or above-mentioned at least two kinds materials stack layer), organic material (example
Such as: polyesters (PET), polyalkenes, poly- propionyl class, polycarbonate-based, polyalkylene oxide class, polyphenyl alkenes, polyethers, polyketone class,
Polyalcohols, polyacetals class, other suitable materials or combinations of the above), other suitable materials or combinations of the above.
A referring to figure 2., then, in forming the second insulation material layer 140 on the first insulation material layer 120.For example,
In the present embodiment, formed before the second insulation material layer 140 on the first insulation material layer of Yu 120, also optionally in
Organic material layer is formed on first insulation material layer 120, in the present embodiment for example, chromatic filter layer 130, chromatic filter layer
130 have the opening 132 Chong Die with the second part 116b of first electrode 116, and the second insulation material layer 140 can insert colored filter
The opening 132 of photosphere 130, however, the present invention is not limited thereto.In the present embodiment, the material and second of the first insulation material layer 120
The material of insulation material layer 140 can not be identical；For example, for same etching solution, the side of the first insulation material layer 120
The lateral etch rate of the second insulation material layer 140, however, the present invention is not limited thereto can be greater than to etch-rate.
Fig. 2A and Fig. 2 B is please referred to, then, in the present embodiment, second can be patterned first with half mode exposure mask 200 absolutely
Edge material layer 140, to form second insulating layer 142.In the present embodiment, half mode exposure mask 200 have opaque region 202,
Partially transparent region 204 and transparent region 206 respectively correspond first part 140a, the second part of the second insulation material layer 140
140b and Part III 140c.A referring to figure 2. specifically firstly, being exposure mask with half mode exposure mask 200, insulate to second
Material layer 140 is exposed process, wherein the first part 140a of the second insulation material layer 140 is not almost exposed, second absolutely
The second part 140b and Part III 140c of edge material layer 140 are exposed, and the second part of the second insulation material layer 140
Light exposure of the light exposure of 140b less than the Part III 140c of the second insulation material layer 140.In the present embodiment, the second insulation
The material of material layer 140 is, for example, eurymeric photoresist, however, the present invention is not limited thereto.In other embodiments, the second insulation material layer
140 material is also possible to minus photoresist, and half mode exposure mask 200 of appropriate mix.
Then A and Fig. 2 B referring to figure 2. carries out developing procedure to the second insulation material layer 140 exposed, to be formed
Second insulating layer 142.In the present embodiment, the second insulation material layer 140 is optionally eurymeric photoresist；Complete work of developing
After sequence, the overwhelming majority of the first part 140a for the second insulation material layer 140 not almost being exposed can be retained and form
The first part 142a of two insulating layers 142, is exposed but the second part 140b meeting of the second insulation material layer 140 that light exposure is small
It is partly removed and is formed the second part 142b of second insulating layer 142, wherein the second part 142b of second insulating layer 142
Average film thickness much smaller than second insulating layer 142 first part 142a average film thickness；The second insulation material exposed completely
The Part III 140c of the bed of material 140 can be then removed, and form the opening 142c of second insulating layer 142, the first insulation material of exposure
A part of 120a of the bed of material 120.
Fig. 2 B to Fig. 2 D is please referred to, is exposure mask with second insulating layer 142 then, in the present embodiment, second insulating layer
142 are used as hard mask, pattern the first insulation material layer 120, to form the first insulating pattern layer 124 and the second insulating pattern
Layer 144.It for example, in the present embodiment, can be the case where second insulating layer 142 covers the first insulating layer 120 (such as Fig. 2 C institute
Show) under, a dry etch process is carried out, to form the first insulating pattern layer 124 and the second insulating pattern layer 144.For example,
The dry etch process carried out in the present embodiment is isotropic etching.In the present embodiment, although the side of second insulating layer 142
To etch-rate less than the first insulating layer 120 lateral etch rate (i.e. within the identical dry etch process time, second absolutely
The volume that edge layer 142 is etched in a lateral direction can be less than the body that the first insulating layer 120 is etched in a lateral direction
Product), but since the second part 142b of second insulating layer 142 is very thin and small in size, after completing dry etch process
(as shown in Figure 2 D), the second insulating pattern layer 144 can expose the sub-fraction of the top surface 124d of the first insulating pattern layer 124, and
The problem of being not susceptible to undercutting (under cut).
Fig. 2 C and Fig. 2 D is please referred to, after carrying out preceding dry etch process, least a portion of second insulating layer 142 can be gone
It removes, and forms the second insulating pattern layer 144.Second insulating pattern layer 144 has the opening 142c of corresponding second insulating layer 142
The second contact hole 144a of (being shown in Fig. 2 B), corresponding second insulating layer 142 second part 142b (being shown in Fig. 2 B) the
The first part 144-1 of two part 144-2 and the first part 142a (being shown in Fig. 2 B) of corresponding second insulating layer 142,
In the second insulating pattern layer 144 second part 144-2 average film thickness be much smaller than the second insulating pattern layer 144 first part
The average film thickness of 144-1.The second part 144-2 of the second insulating pattern layer 144 at the second contact hole 144a has side wall
The 144b and bottom surface 144c being connected with side wall 144b.
First insulating pattern layer 124 has the first contact hole 124a.First contact hole 124a and the second contact hole 144a weight
It is laminated on the second part 116b of the first electrode 116 of active member 110.In the present embodiment, in the Vertical Square of vertical substrate 100
To on z, the upright projection of the first contact hole 124a is located in the range of the upright projection of the second contact hole 144a.
The bottom that the first insulating pattern layer 124 at the first contact hole 124a has side wall 124b and is connected with side wall 124b
Face 124c.In the present embodiment, the second insulating pattern layer 144 does not cover the side wall 124b of the first insulating pattern layer 124.First absolutely
The bottom surface 124c of the side wall 124b of edge pattern layer 124 and the first insulating pattern layer 124 has the first angle α.Second insulating pattern
The bottom surface 144c of the second part 144-2 of the side wall 144b and the second insulating pattern layer 144 of the second part 144-2 of layer 144 has
There is the second angle β.In the present embodiment, the second angle β can be located on the top surface 124d of the first insulating pattern layer 124.Second folder
Angle beta is less than the first angle α.For example, in the present embodiment, the second angle β is less than the half of the first angle α, i.e. the α of β < 0.5,
However, the present invention is not limited thereto.
In the present embodiment, the side wall 124b of the top surface 124d of the first insulating pattern layer 124 and the first insulating pattern layer 124
With the first boundary side 124e.The bottom surface 144c of the side wall 144b of second insulating pattern layer 144 and the second insulating pattern layer 144 tool
There is the second boundary side 144d.First boundary spaced a distance L of 144d in 124e and the second boundary.For example, in this implementation
In example, distance L is greater than 0.5 micron (μm), but invention is not limited thereto.
Fig. 2 E and Figure 1B are please referred to, then, in formation pixel electrode 150 on the second insulating pattern layer 144.Specifically,
Pixel electrode 150 covers the second insulating pattern layer 144 and the first insulating pattern layer 124.Pixel electrode 150 passes through the first contact hole
The first electrode 116 of 124a and the second contact hole 144a and active member 110 is electrically connected.In this, dot structure is just completed
10。
Fig. 3 A is the upper schematic diagram according to the dot structure of another embodiment of the present invention.Fig. 3 B is the hatching line according to Fig. 3 A
The diagrammatic cross-section for the dot structure that B-B ' and hatching line C-C ' are painted.Fig. 3 A omit the substrate 100 of Fig. 3 B, gate insulation layer 113 and
Chromatic filter layer 130 is painted.Fig. 4 A to Fig. 4 C is that the manufacturing process section of the regional area 20a of the dot structure 20 of Fig. 3 B shows
It is intended to.It need to should be noted that, the embodiment of Fig. 3 A~3B and Fig. 4 A~4C continue to use the embodiment of Figure 1A~1B and Fig. 2A~2E
Element numbers and partial content wherein being indicated identical or approximate element using identical or approximate label, and are omitted
The explanation of same technique content.Explanation about clipped can refer to previous embodiment, no longer repeat in this.
The embodiment of Fig. 3 A~Fig. 3 B and Fig. 4 A~Fig. 4 C is main with the embodiment of Figure 1A~Figure 1B and Fig. 2A~Fig. 2 E
Difference is: dot structure 20 includes island-shaped pattern 172 '.By island-shaped pattern 172 ', made using half mode exposure mask 210
First insulating pattern layer 124 and the second insulating pattern layer 144 out, wherein half mode exposure mask 210 (being plotted in Fig. 4 A) has difference
The number in the region of light transmittance is few compared with half mode exposure mask 200 (being plotted in Fig. 2A), and the acquisition cost of half mode exposure mask 210 is compared with half mode
Exposure mask 200 is low, and then can reduce the manufacturing cost of dot structure 20.Cooperate Fig. 3 A, Fig. 3 B and Fig. 4 A to Fig. 4 C below, illustrates
The manufacturing process of the dot structure 20 of bright another embodiment of the present invention.
Fig. 3 A and Fig. 3 B is please referred to, firstly, providing substrate 100.Then, in formation active member 110 on substrate 100.It lifts
It, in the present embodiment, can be prior to forming the first conductive layer on substrate 100 for example, the first conductive layer is in addition to grid 112 and shares
Except electrode 172, it may also include island-shaped pattern 172 '.Island-shaped pattern 172 ' is separated with common electrode 172.172 ' quilt of island-shaped pattern
Common electrode 172 is isolated, also that is, there are an annular gap g between island-shaped pattern 172 ' and common electrode 172.
Then, gate insulation layer 113, semiconductor pattern 114 and the second conductive layer are sequentially formed on the first conductive layer,
Middle gate insulation layer 113 covers grid 112 and island-shaped pattern 172 '.Second conductive layer includes first electrode 116 and second electrode
118.In the present embodiment, the second part 116b of first electrode 116 is stackable is set to island-shaped pattern 172 ', island-shaped pattern
On annular gap g and partial common electrode 172 between 172 ' and common electrode 172.In the present embodiment, first electrode
116 second part 116b has lug boss 116c (being shown in Fig. 3 B), and lug boss 116c is arranged in island-shaped pattern 172 '.
Fig. 3 B is please referred to, then, in sequentially forming the first insulating pattern layer 124 and the second insulating pattern on the second conductive layer
Layer 144 cooperates Fig. 4 A to Fig. 4 C to illustrate it below.
Fig. 3 B and Fig. 4 A is please referred to, is insulated in sequentially forming the first insulation material layer 120 and second on active member 110
Material layer 140.In the present embodiment, since the second part 116b of first electrode 116 has lug boss 116c, the
It before two insulation material layers 140 are not fully cured, is influenced by gravity, the second insulation material layer 140 can be towards the outer of lug boss 116c
Beach stream is enclosed, and then makes the second insulation material layer 140 after solidifying that there is second part 140b, a part of shape of second part 140b
At on lug boss 116c and thinner thickness.
Fig. 4 A and Fig. 4 B is please referred to, then, in the present embodiment, second can be patterned first with half mode exposure mask 210 absolutely
Edge material layer 140, to form the second insulating pattern layer 144.In the present embodiment, half mode exposure mask 210 has opaque region
212 and partially transparent region 214, respectively correspond the first part 140a and second part 140b of the second insulation material layer 140.Portion
The second part 140b of the second insulation material layer 140 divided is located on the lug boss 116c of first electrode 116.
A referring to figure 4. is exposed work to the second insulation material layer 140 firstly, being exposure mask with half mode exposure mask 210
Sequence, wherein the first part 140a of the second insulation material layer 140 is not almost exposed, second of the second insulation material layer 140
140b is divided to be exposed.Fig. 4 A and Fig. 4 B is please referred to, then, developing procedure is carried out to the second insulation material layer 140 exposed, with
Form the second insulating pattern layer 144.In the present embodiment, after completing developing procedure, the first part 140a that is not almost exposed
The overwhelming majority can be retained, the second part 140b exposed in right amount can be partly removed.Specifically, it is located at the first electricity
A part that the thickness of second part 140b on the lug boss 116c of pole 116 is thin can be removed, and the first insulating materials of exposure
A part of 120a on the lug boss 116c of the second part 116b positioned at first electrode 116 of layer 120.
Fig. 4 B is please referred to, is exposure mask with the second insulation material layer 140 after exposing then, in the present embodiment, second absolutely
Edge material layer 140 is used as hard mask, the first insulation material layer 120 is patterned, to form the first insulating pattern layer 124 and second
Insulating pattern layer 144.For example, in the present embodiment, can after exposure the second insulation material layer 140 covering first insulation
In the case where material layer 120, a dry etch process is carried out, to form the first insulating pattern layer 124 and the second insulating pattern layer
144.In the present embodiment, after completing dry etch process, the second insulating pattern layer 144 can expose the first insulating pattern layer
The sub-fraction of 124 top surface 124d, and it is not susceptible to the problem of undercuting (under cut).
Fig. 4 B is please referred to, after carrying out preceding dry etch process, least a portion of second insulation material layer 140 can be gone
It removes, and forms the second insulating pattern layer 144.Second insulating pattern layer 144 has the second contact hole of respective protrusions portion 116c
144a, corresponding second insulation material layer 140 second part 140b second part 144-2 and corresponding second insulation material layer
The first part 144-1 of 140 first part 140a, wherein the average film of the second part 144-2 of the second insulating pattern layer 144
Average film thickness of the thickness much smaller than the first part 144-1 of the second insulating pattern layer 144.Second at the second contact hole 144a is exhausted
The bottom surface 144c that the second part 144-2 of edge pattern layer 144 has side wall 144b and is connected with side wall 144b.
First insulating pattern layer 124 has the first contact hole 124a.First contact hole 124a and the second contact hole 144a weight
It is laminated on the lug boss 116c of the first electrode 116 of active member 110.In the present embodiment, the lug boss 116c of first electrode 116
Protrude from the first contact hole 124a.In the present embodiment, on the vertical direction z of vertical substrate 100, the first contact hole 124a's
Upright projection is located in the range of the upright projection of the second contact hole 144a.In the present embodiment, in the vertical of vertical substrate 100
On the z of direction, the upright projection of island-shaped pattern 172 ' is located at the upright projection and/or the second contact hole 144a of the first contact hole 124a
Upright projection in.
The bottom that the first insulating pattern layer 124 at the first contact hole 124a has side wall 124b and is connected with side wall 124b
Face 124c.In the present embodiment, the second insulating pattern layer 144 does not cover the side wall 124b of the first insulating pattern layer 124.First absolutely
The bottom surface 124c of the side wall 124b of edge pattern layer 124 and the first insulating pattern layer 124 has the first angle α.Second insulating pattern
The bottom surface 144c of the second part 144-2 of the side wall 144b and the second insulating pattern layer 144 of the second part 144-2 of layer 144 has
There is the second angle β.Second angle β is less than the first angle α.For example, the second angle β less than the first angle α half, also
That is, the α of β < 0.5, however, the present invention is not limited thereto.In the present embodiment, the second angle β can be located at the top of the first insulating pattern layer 124
On the 124d of face.
In the present embodiment, the side wall 124b of the top surface 124d of the first insulating pattern layer 124 and the first insulating pattern layer 124
With the first boundary side 124e.The bottom surface 144c of the side wall 144b of second insulating pattern layer 144 and the second insulating pattern layer 144 tool
There is the second boundary side 144d.First boundary spaced a distance L of 144d in 124e and the second boundary.For example, in this implementation
In example, distance L is greater than 0.5 micron (μm), but invention is not limited thereto.
Fig. 4 C and Fig. 3 B is please referred to, then, in formation pixel electrode 150 on the second insulating pattern layer 144.Pixel electrode
150 are electrically connected by the first electrode 116 of the first contact hole 124a and the second contact hole 144a and active member 110.In this,
Just dot structure 20 is completed.
Based on above-mentioned, the dot structure 20 and its manufacturing method of one embodiment of the invention also have and dot structure above-mentioned
10 and its similar effect and advantage of manufacturing method, it is just no longer repeated in this.
Fig. 5 A is the upper schematic diagram according to the dot structure of another embodiment of the present invention.Fig. 5 B is the hatching line according to Fig. 5 A
The diagrammatic cross-section for the dot structure that D-D ' is painted.Fig. 5 A omits the substrate 100, gate insulation layer 113 and chromatic filter layer of Fig. 5 B
130 are painted.Fig. 6 A to Fig. 6 D is the manufacturing process diagrammatic cross-section of the regional area 30a of the dot structure 30 of Fig. 5 B.It needs
Bright, the embodiment of Fig. 5 A~Fig. 5 B and Fig. 6 A~Fig. 6 D continues to use the element of the embodiment of Figure 1A~Figure 1B and Fig. 2A~Fig. 2 E
Label and partial content wherein being indicated identical or approximate element using identical or approximate label, and are omitted identical
The explanation of technology contents.Explanation about clipped can refer to previous embodiment, no longer repeat in this.
The embodiment of Fig. 5 A~Fig. 5 B and Fig. 6 A~Fig. 6 D is main with the embodiment of Figure 1A~Figure 1B and Fig. 2A~Fig. 2 E
Difference is: the second insulating pattern layer 148 of dot structure 30 covers the side wall 126b of the first insulating pattern layer 126.Match below
Fig. 5 A, Fig. 5 B and Fig. 6 A to Fig. 6 D are closed, the manufacturing process of the dot structure 30 of another embodiment is illustrated the present invention.
Fig. 5 A and Fig. 5 B is please referred to, in the present embodiment, dot structure 30 is substantially similar with dot structure 10.In this reality
It applies in example, firstly, providing substrate 110.Then, sequentially in formation active member 110, the first insulating pattern layer 126 on substrate 100
And the second insulating pattern layer 148, cooperate Fig. 6 A to Fig. 6 D to illustrate it below.
Fig. 5 B and Fig. 6 A is please referred to, is insulated in sequentially forming the first insulation material layer 120 and second on active member 110
Material layer 140.In the present embodiment, the second insulation material layer 140 can be patterned first with exposure mask 220, to form the second insulation
Layer 146.In the present embodiment, exposure mask 220 has opaque region 222 and transparent region 224, respectively corresponds the second insulating materials
The first part 140a and second part 140b of layer 140.Specifically, firstly, with exposure mask 220 to the second insulation material layer 140
It is exposed process, wherein the first part 140a of the second insulation material layer 140 is not almost exposed, the second insulation material layer
140 second part 140b is exposed.Fig. 6 A and Fig. 6 B is please referred to, then, the second insulation material layer 140 exposed is carried out
Developing procedure can be retained the overwhelming majority for the first part 140a not almost being exposed, the second part exposed completely
140b can be then removed.
Then, in the present embodiment, to 140 (i.e. most first be retained of the second insulation material layer after exposure
Part 140a) prebake conditions processing procedure is carried out, to form a second insulating layer 146.Fig. 6 A and Fig. 6 B is please referred to, preliminary drying baking is being carried out
After journey, with the second insulating layer 146 that has carried out prebake conditions processing procedure but be not fully cured for exposure mask, in the present embodiment, second
Insulating layer 146 is used as hard mask, the first insulation material layer 120 is patterned, to form the first insulating pattern layer 126.Citing and
Speech in the present embodiment can be in second insulating layer 146 (i.e. the retained first part 140a of the overwhelming majority) the first insulation of covering
In the case where material layer 120, a dry etch process is carried out, to form the first insulating pattern layer 126.
Fig. 6 B is please referred to, second insulating layer 146 has opening 146a.Opening 146a is overlapped in the first of active member 110
The second part 116b of electrode 116.Second insulating layer 146 at opening 146a has side wall 146b and is connected with side wall 146b
Bottom surface 146c.The side wall 146b of second insulating layer 146 is located at the top of the second part 116b of first electrode 116.
First insulating pattern layer 126 has the first contact hole 126a.First contact hole 126a is overlapped in active member 110
The second part 116b of first electrode 116.The first insulating pattern layer 126 at the first contact hole 126a have side wall 126b and
The bottom surface 126c being connected with side wall 126b.The bottom surface of the side wall 126b of first insulating pattern layer 126 and the first insulating pattern layer 126
126c has the first angle α.First angle α is located on the top surface 116d of the second part 116b of first electrode 116.In this implementation
In example, the side wall 126b of the first insulating pattern layer 126 and the bottom surface 146c of second insulating layer 146 can form inner recess 126d.This
When, second insulating layer 146 not yet covers the side wall 126b of the first insulating pattern layer 126.
Fig. 6 B and Fig. 6 C is please referred to, then, toasts processing procedure after carrying out to second insulating layer 146, to form the second insulation figure
Pattern layer 148.In the present embodiment, after carrying out aforementioned rear baking processing procedure, the second insulating pattern layer 148 covers the first insulating pattern
The side wall 126b of layer 126, the problem of undercutting (under cut) can be improved whereby.Second insulating pattern layer 148 has the second contact
Window 148a.Second contact hole 148a is overlapped in the second part 116b of the first electrode 116 of active member 110.In the second contact
The bottom surface 148c that the second insulating pattern layer 148 at window 148a has side wall 148b and is connected with side wall 148b.Second insulation figure
The bottom surface 148c of the side wall 148b of pattern layer 148 and the second insulating pattern layer 148 has the second angle β.In the present embodiment, second
Angle β is located on the top surface 116d of the second part 116b of first electrode 116, and the second angle β is less than the first angle α.
In the present embodiment, the side wall 148b of the second insulating pattern layer 148 covers the side wall of the first insulating pattern layer 126
126b.Specifically, the bottom surface 126c of the side wall 126b of the first insulating pattern layer 126 and the first insulating pattern layer 126, which has, hands over
Boundary side 126e.The bottom surface 148c of the side wall 148b of second insulating pattern layer 148 and the second insulating pattern layer 148 has boundary side
148d.In the present embodiment, on the vertical direction z of vertical substrate 100, the boundary side 148d's of the second insulating pattern layer 148
Upright projection is located in the range of the upright projection of the boundary side 126e of the first insulating pattern layer 126.
Fig. 6 D and Fig. 5 B is please referred to, then, in formation pixel electrode 150 on the second insulating pattern layer 148.Specifically,
Pixel electrode 150 covers the second insulating pattern layer 144.Pixel electrode 150 passes through the second contact hole of the second insulating pattern layer 148
The first electrode 116 of 148a and active member 110 is electrically connected.In this, dot structure 30 is just completed.
In conclusion the dot structure of one embodiment of the invention, including substrate, active member, the first insulating pattern layer,
Two insulating pattern layers and pixel electrode.Active member is set on substrate.First insulating pattern layer is set on active member,
And there is the first contact hole.First contact hole is overlapped in the first electrode of active member.Second insulating pattern layer is set to first
On insulating pattern layer, and there is the second contact hole.Second contact hole is overlapped in the first electrode of active member.Pixel electrode setting
It is electrically connected on the second insulating pattern layer, and by the first electrode of the first contact hole and the second contact hole and active member.
The first insulating pattern layer at the first contact hole has side wall and bottom surface.The second insulating pattern layer at the second contact hole
With side wall and bottom surface.In particular, having first in the side wall of the first insulating pattern layer and the bottom surface of the first insulating pattern layer
Angle α has the second angle β in the side wall of the second insulating pattern layer and the bottom surface of the second insulating pattern layer, and the second angle β is small
In the first angle α.The dot structure of one embodiment of the invention is less prone to undercutting problem.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope should be defined by the scope of the appended claims.
Claims (12)
1. a kind of dot structure characterized by comprising
One substrate；
One active member is set on the substrate；
One first insulating pattern layer, is set on the active member, and has one first contact hole, which is overlapped in
One first electrode of the active member；
One second insulating pattern layer is set on the first insulating pattern layer, and has one second contact hole, second contact hole
It is overlapped in the first electrode of the active member；And
One pixel electrode is set on the second insulating pattern layer, and by first contact hole and second contact hole and is somebody's turn to do
The first electrode of active member is electrically connected；
Wherein, the first insulating pattern layer at first contact hole has one side wall and a bottom surface, the first insulation figure
The bottom surface of the side wall of pattern layer and the first insulating pattern layer has one first angle α, at second contact hole this
Two insulating pattern layers have one side wall and a bottom surface, the side wall of the second insulating pattern layer and the second insulating pattern layer
The bottom surface has one second angle β, and the second angle β is less than first angle α.
2. dot structure as described in claim 1, which is characterized in that the α of β < 0.5.
3. dot structure as described in claim 1, which is characterized in that second angle β is located at the first insulating pattern layer
On one top surface, and the second insulating pattern layer does not cover the side wall of the first insulating pattern layer.
4. dot structure as claimed in claim 3, which is characterized in that the top surface of the first insulating pattern layer and this first absolutely
The side wall of edge pattern layer has one first boundary side, the side wall of the second insulating pattern layer and the second insulating pattern layer
The bottom surface has one second boundary side, first boundary spaced a distance L while with second boundary.
5. dot structure as claimed in claim 4, which is characterized in that L > 0.5 μm.
6. dot structure as described in claim 1, which is characterized in that in a vertical direction of the vertical substrate, this first
One upright projection of contact hole is located in the range of a upright projection of second contact hole.
7. dot structure as described in claim 1, which is characterized in that further include:
One island-shaped pattern, wherein first electrode stacking is set in the island-shaped pattern, and one in the vertical substrate is vertical
On direction, a upright projection of the island-shaped pattern is located at a upright projection of first contact hole or the one of second contact hole is hung down
It delivers directly in shadow.
8. dot structure as described in claim 1, which is characterized in that the first electrode has a lug boss, and the lug boss is prominent
For first contact hole.
9. dot structure as described in claim 1, which is characterized in that the second insulating pattern layer covers first insulating pattern
The side wall of layer.
10. a kind of manufacturing method of dot structure characterized by comprising
In forming an active member on a substrate；
In one first insulation material layer of formation on the active member；
In one second insulation material layer of formation on first insulation material layer；
Using mask patterning second insulation material layer of half mode, to form a second insulating layer, wherein second insulation
Layer has an opening；
With the second insulating layer for mask patterning first insulation material layer, to form one first insulating pattern layer and one the
Two insulating pattern layers, wherein the first insulating pattern layer has one first contact hole；The second insulating pattern layer has one second
Contact hole, first contact hole and second contact hole are overlapped in a first electrode of the active member；And the first insulation figure
Pattern layer has one side wall and a bottom surface, and the side wall of the first insulating pattern layer and the bottom surface of the first insulating pattern layer have
One first angle α, the second insulating pattern layer have one side wall and a bottom surface, the side wall of the second insulating pattern layer and this
The bottom surface of two insulating pattern layers has one second angle β, and the α of β < 0.5；And
A pixel electrode is formed, it is electrical by the first electrode of first contact hole and second contact hole and the active member
Connection.
11. the manufacturing method of dot structure as claimed in claim 10, which is characterized in that further include:
Before the first electrode for forming the active member, an island-shaped pattern is formed, wherein first electrode stacking is set to
In the island-shaped pattern, and in a vertical direction of the vertical substrate, a upright projection of the island-shaped pattern be located at this first
In one upright projection of contact hole or a upright projection of second contact hole.
12. a kind of manufacturing method of dot structure characterized by comprising
In forming an active member on a substrate；
In one first insulation material layer of formation on the active member；
In one second insulation material layer of formation on first insulation material layer；
Second insulation material layer is patterned, and a prebake conditions processing procedure is carried out to second insulation material layer, to form one second
Insulating layer, wherein the second insulating layer has an opening, and the superposition of end gap is in a first electrode of the active member；
With the second insulating layer for mask patterning first insulation material layer, to form one first insulating pattern layer, wherein
The first insulating pattern layer has one first contact hole, and first contact hole of the first insulating pattern layer is overlapped in the active element
The first electrode of part, the first insulating pattern layer at first contact hole have one side wall；
Processing procedure is toasted after carrying out one to the second insulating layer, to form one second insulating pattern layer, wherein second insulating pattern
Layer covers the side wall of the first insulating pattern layer, and the second insulating pattern layer has one second contact hole；And
A pixel electrode is formed, second contact hole of the second insulating pattern layer and the first electrode of the active member are passed through
It is electrically connected.
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| TW108101844A TWI710122B (en) | 2019-01-17 | 2019-01-17 | Pixel structure and manufacturing method thereof |
| TW108101844 | 2019-01-17 |
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| CN1682259A (en) * | 2002-09-20 | 2005-10-12 | 株式会社半导体能源研究所 | Display device and manufacturing method thereof |
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| CA2986526C (en) * | 2017-07-31 | 2023-10-17 | Queen's University At Kingston | Autorotating unmanned aerial vehicle surveying platform |
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|---|---|---|---|---|
| CN1682259A (en) * | 2002-09-20 | 2005-10-12 | 株式会社半导体能源研究所 | Display device and manufacturing method thereof |
| CN101452947A (en) * | 2007-12-07 | 2009-06-10 | 精工爱普生株式会社 | Light-emitting device, electronic apparatus, and film-forming method |
| CN101488479A (en) * | 2009-02-13 | 2009-07-22 | 友达光电股份有限公司 | Thin-film transistor array substrate and manufacturing method thereof |
| CN106340531A (en) * | 2015-07-10 | 2017-01-18 | 三星显示有限公司 | Organic light-emitting display apparatus |
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