CN110098194B

CN110098194B - Semiconductor device and method of manufacture

Info

Publication number: CN110098194B
Application number: CN201910066184.4A
Authority: CN
Inventors: 永井孝一; 中村亘; 中村光宏; 伊藤昭男
Original assignee: Fujitsu Semiconductor Memory Solution Ltd
Current assignee: Fujitsu Semiconductor Memory Solution Ltd
Priority date: 2018-01-31
Filing date: 2019-01-24
Publication date: 2023-07-04
Anticipated expiration: 2039-01-24
Also published as: CN110098194A; US10847522B2; JP7027916B2; DE102019200787A1; JP2019134071A; DE102019200787B4; US20190237471A1

Abstract

A semiconductor device, comprising: a substrate; a transistor formed on a surface of the substrate; a first insulating film formed over the transistor; a second insulating film formed on the first insulating film; a third insulating film formed on the second insulating film; a fourth insulating film formed on the third insulating film; and a ferroelectric capacitor formed on the fourth insulating film, wherein the third insulating film has a hydrogen permeability higher than that of the first insulating film, and the second insulating film and the fourth insulating film have a hydrogen permeability and an oxygen permeability higher than those of the first insulating film and the third insulating film.

Description

Semiconductor device and method of manufacture

Technical Field

The disclosure discussed herein relates to a semiconductor device and method of manufacture.

Background

The development of ferroelectric random access memories (ferams) that retain information in ferroelectric capacitors by utilizing polarization inversion of ferroelectric memories has recently been advanced. FeRAM is a non-volatile memory configured to hold information even when power is turned off. The ferroelectric memory has high integration, high-speed driving, high durability and low power consumption.

Has a perovskite crystal structure and a remnant polarization of about 10. Mu.C/cm ² To 30 muC/cm ² Is mainly used as a ferroelectric film material for forming a ferroelectric capacitor; examples of ferroelectric oxides include PZT (Pb (Zr, ti) O ₃ ) And SBT (SrBi) ₂ Ta ₂ O ₉ ). The ferroelectric properties of ferroelectric oxides are liable to deteriorate due to moisture from an interlayer insulating film having a high affinity with water, such as a silicon oxide film. That is, during a high temperature process of forming a metal wiring or forming an interlayer insulating film after forming a ferroelectric capacitor, moisture contained in the interlayer insulating film is decomposed into hydrogen and oxygen. Thus, hydrogenThe gas reacts with oxygen in the ferroelectric oxide, starving the ferroelectric film of oxygen, which reduces the crystallinity of the ferroelectric film. The oxygen deficiency due to the moisture contained in the interlayer insulating film may occur not only during the high temperature process but also by long-term use of the ferroelectric memory. The decrease in crystallinity of the ferroelectric film causes deterioration of the ferroelectric capacitor.

Accordingly, various researches have been made on the structure of the ferroelectric film in the related art to reduce the entry of hydrogen into the ferroelectric film. For example, a structure having a ferroelectric capacitor directly covered with an aluminum oxide film on the upper side and the side is known in the art. Further, a structure having a silicon nitride film which is formed on the surface of a semiconductor substrate and is provided between the semiconductor substrate and a transistor connected to a ferroelectric capacitor is known in the art. Aluminum oxide films and silicon nitride films are not easily permeable to hydrogen and moisture. Further, a structure having a guard ring (guard ring) provided around a memory cell portion including a plurality of ferroelectric capacitors is known in the art.

However, the related art technology cannot sufficiently reduce the deterioration of the ferroelectric capacitor due to hydrogen.

Related art documents

Patent literature

Patent document 1: japanese patent laid-open publication No. 2005-268478.

Disclosure of Invention

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same capable of further reducing deterioration of a ferroelectric capacitor caused by hydrogen.

According to one aspect of the embodiment, a semiconductor device includes:

a substrate;

a transistor formed on a surface of the substrate;

a first insulating film formed over the transistor;

a second semiconductor film formed on the first semiconductor film;

a third semiconductor film formed on the second semiconductor film;

a fourth semiconductor film formed on the third semiconductor film; and

a ferroelectric capacitor formed on the fourth insulating film,

wherein the hydrogen permeability of the third insulating film is higher than that of the first insulating film,

wherein the hydrogen permeability and the oxygen permeability of the second insulating film and the fourth insulating film are higher than the hydrogen permeability and the oxygen permeability of the first insulating film and the third insulating film.

According to another aspect of the embodiment, a method of manufacturing a semiconductor device includes:

forming a transistor on a surface of a substrate;

forming an insulating film over the transistor;

forming a second insulating film on the first insulating film, the second insulating film having a higher hydrogen permeability and an oxygen permeability than the first insulating film;

forming a third insulating film on the second insulating film, the third insulating film having a hydrogen permeability higher than that of the first insulating film, the third insulating film having a hydrogen permeability and an oxygen permeability lower than those of the second insulating film;

forming a fourth insulating film on the third insulating film, the fourth insulating film having a higher hydrogen permeability and an oxygen permeability than the first insulating film and the third insulating film;

forming a ferroelectric capacitor on the fourth insulating film; and

annealing is performed to desorb hydrogen contained in the second insulating film and the fourth insulating film.

Advantageous effects

According to the disclosed technology, the deterioration of the ferroelectric capacitor caused by hydrogen gas can be further reduced.

Drawings

Fig. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment;

fig. 2A is a cross-sectional view (part 1) showing a manufacturing method of a semiconductor device according to the first embodiment;

fig. 2B is a cross-sectional view (part 2) showing a manufacturing method of the semiconductor device according to the first embodiment;

fig. 2C is a cross-sectional view (section 3) showing a manufacturing method of the semiconductor device according to the first embodiment;

fig. 2D is a cross-sectional view (part 4) showing a manufacturing method of the semiconductor device according to the first embodiment;

fig. 2E is a cross-sectional view (part 5) showing a manufacturing method of the semiconductor device according to the first embodiment;

fig. 3 is a view showing a schematic layout of a semiconductor device according to a second embodiment;

fig. 4 is a view showing a semiconductor device according to a second embodiment before dicing is performed;

fig. 5 is a cross-sectional view showing a semiconductor device according to a second embodiment;

FIG. 6 is a cross-sectional view showing transistors within a memory cell portion;

fig. 7 is a view showing a circuit configuration of the memory cell section;

fig. 8A is a cross-sectional view (part 1) showing a manufacturing method of a semiconductor device according to a second embodiment;

fig. 8B is a cross-sectional view (section 2) showing a manufacturing method of the semiconductor device according to the second embodiment.

Fig. 8C is a cross-sectional view (part 3) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8D is a cross-sectional view (part 4) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8E is a cross-sectional view (part 5) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8F is a cross-sectional view (part 6) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8G is a cross-sectional view (part 7) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8H is a cross-sectional view (section 8) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8I is a cross-sectional view (part 9) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8J is a cross-sectional view (section 10) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8K is a cross-sectional view (part 11) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8L is a cross-sectional view (section 12) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8M is a cross-sectional view (part 13) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8N is a cross-sectional view (section 14) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8O is a cross-sectional view (section 15) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8P is a cross-sectional view (part 16) showing a manufacturing method of the semiconductor device according to the second embodiment.

Fig. 8Q is a cross-sectional view (part 17) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8R is a cross-sectional view (18 th portion) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8S is a cross-sectional view (part 19) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8T is a cross-sectional view (portion 20) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8U is a cross-sectional view (21 st part) showing a manufacturing method of a semiconductor device according to the second embodiment;

fig. 8V is a cross-sectional view (part 22) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8W is a cross-sectional view (23 rd portion) showing a manufacturing method of the semiconductor device according to the second embodiment;

fig. 8X is a cross-sectional view (24 th portion) showing a manufacturing method of a semiconductor device according to the second embodiment;

FIG. 9 is a cross-sectional view showing a sample used for the experiment;

fig. 10A is a graph (part 1) showing experimental results; and

fig. 10B is a graph (section 2) showing the experimental results.

Detailed Description

Specific embodiments are described below with reference to the accompanying drawings.

First embodiment

First, a first embodiment will be described. Fig. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.

As shown in fig. 1, a semiconductor device 100 according to the first embodiment includes a substrate 101 and a transistor Tr formed on a surface of the substrate 101. The semiconductor device 100 further includes a first insulating film 111 formed over the transistor Tr, a second insulating film 112 formed on the first insulating film 111, a third insulating film 113 formed on the second insulating film 112, and a fourth insulating film 114 formed on the third insulating film 113. The semiconductor device 100 further includes a ferroelectric capacitor Q formed on the fourth insulating film 114. The hydrogen permeability of the third insulating film 113 is higher than that of the first insulating film 111, and the hydrogen permeability and the oxygen permeability of the second insulating film 112 and the fourth insulating film 114 are higher than those of the first insulating film 111 and the third insulating film 113.

An element isolation insulating film 102 configured to define an element region in which the transistor Tr is formed on the surface of the substrate 101. The transistor Tr includes, for example, a first conductivity-type well 191, a second conductivity-type impurity diffusion layer 193, a gate insulating film 194, and a gate electrode 195. An insulating film 103 is formed to cover the transistor Tr on the substrate 101, and an insulating film 104 is formed on the insulating film 103.

The ferroelectric capacitor Q includes a lower electrode 121, a ferroelectric film 122, and an upper electrode 123. A fifth insulating film 131 is formed on the fourth insulating film 114 to cover the upper surface and the side surfaces of the ferroelectric capacitor Q. The hydrogen permeability of the fifth insulating film 131 is lower than that of the third insulating film 113, and the oxygen permeability of the fifth insulating film 131 is lower than that of the second insulating film 112 and the fourth insulating film 114.

The first conductor 116 may be formed in the first insulating film 111 and the second insulating film 112, the second conductor 118 may be formed in the third insulating film 113 and the fourth insulating film 114, and the third conductor 106 may be formed in the insulating film 103 and the insulating film 104. The second conductor 118 is connected to the first conductor 116 and the ferroelectric capacitor Q, and the third conductor 106 is in contact with the lower surface of the first conductor 116 and connected to the transistor Tr.

Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described. Fig. 2A to 2E are cross-sectional views showing a manufacturing method of the semiconductor device 100 according to the first embodiment in the order of steps.

First, as shown in fig. 2A, an element isolation insulating film 102 is formed on the surface of a substrate 101. Subsequently, the transistor Tr is formed in the element region. After that, an insulating film 103 is formed so as to cover the transistor Tr, and an insulating film 104 is formed on the insulating film 103.

Subsequently, as shown in fig. 2B, a first insulating film 111, a second insulating film 112, a third insulating film 113, and a fourth insulating film 114 are sequentially formed for the insulating film 104. The third conductor 106 may be formed after the insulating film 103 and the insulating film 104 are formed. The first conductor 116 may be formed after the first insulating film 111 and the second insulating film 112 are formed. The second conductor 118 may be formed after the third insulating film 113 and the fourth insulating film 114 are formed.

Subsequently, as shown in fig. 2C, a ferroelectric capacitor Q having a lower electrode 121, a ferroelectric film 122, and an upper electrode 123 is formed on the fourth insulating film 114.

And then annealing is performed. In this annealing, the moisture contained in the second insulating film 112 and the moisture contained in the fourth insulating film 114 are decomposed into hydrogen and oxygen. Since the first insulating film 111 has the lowest hydrogen permeability among the first insulating film 111, the second insulating film 112, the third insulating film 113, and the fourth insulating film 114, hydrogen generated in the second insulating film 112 and hydrogen generated in the fourth insulating film 114 are released upward over the fourth insulating film 114. That is, as shown in fig. 2D, the hydrogen contained in the second insulating film 112 and the fourth insulating film 114 is desorbed. This anneal may also be used as a recovery anneal for ferroelectric capacitor Q. The oxygen permeability of the first insulating film 111 and the third insulating film 113 is lower than that of the second insulating film 112 and the fourth insulating film 114. Therefore, even if annealing is performed in an atmosphere containing oxygen, the first conductor 116, the second conductor 118, and the third conductor 106 are hardly oxidized.

Subsequently, as shown in fig. 2E, a fifth insulating film 131 is formed on the fourth insulating film 114 to cover the upper surface and the side surfaces of the ferroelectric capacitor Q.

After that, an upper layer wiring or the like is formed to complete the semiconductor device 100.

In the semiconductor device 100, as described above, among the first insulating film 111, the second insulating film 112, the third insulating film 113, and the fourth insulating film 114, the first insulating film 111 has the lowest hydrogen permeability, and therefore, hydrogen generated in the second insulating film 112 and hydrogen generated in the fourth insulating film 114 are released upward above the fourth insulating film 114. Therefore, even if the upper layer wiring or the like is exposed to a temperature at which water can be decomposed during formation of the fifth insulating film 131, deterioration of the ferroelectric capacitor Q due to the water contained in the second insulating film 112 and the fourth insulating film 114 does not easily occur. In addition, deterioration of the ferroelectric capacitor Q due to long-term use is less likely to occur. According to the first embodiment, the deterioration of the ferroelectric capacitor due to hydrogen can be further reduced.

Second embodiment

The semiconductor device according to the second embodiment is described below. The semiconductor device according to the second embodiment relates to an example of a ferroelectric memory. Fig. 3 is a view showing a schematic layout of a semiconductor device according to a second embodiment. Fig. 4 is a view showing a semiconductor device according to a second embodiment before dicing is performed. Fig. 5 is a cross-sectional view showing a semiconductor device according to a second embodiment. Fig. 5 corresponds to a cross-sectional view taken along the line V-V in fig. 3.

As shown in fig. 3, the semiconductor device 200 according to the second embodiment includes a memory cell portion 1, a logic circuit portion 2, a peripheral circuit portion 3, and a pad portion 4. The pad portion 4 is arranged near the periphery of the semiconductor device 200, and the memory cell portion 1, the logic circuit portion 2, and the peripheral circuit portion 3 are arranged inward with respect to the pad portion 4.

In order to manufacture the semiconductor device 200, as shown in fig. 4, a plurality of semiconductor devices 200 are formed in parallel on one wafer, and the semiconductor devices 200 are cut along the dicing lines 11 by a dicing process. Details of the manufacturing method of the semiconductor device 200 are described later.

As shown in fig. 5, in the semiconductor device 200, an element isolation insulating film 202 defining an element region is formed on the surface of a substrate 201. The transistor TrC is formed in the element region in the memory cell portion 1, the transistor TrL is formed in the element region in the logic circuit portion 2, and the transistor TrP is formed in the element region in the peripheral circuit portion 3.

The transistor TrC will be described below. Fig. 6 is a cross-sectional view showing a transistor within a memory cell portion.

As shown in fig. 6, the transistor TrC includes a P-type well 291, an N-type low concentration impurity diffusion layer 292, an N-type high concentration impurity diffusion layer 293, a gate insulating film 294, a gate 295, and a sidewall insulating film 296. For example, boron (B) is contained As a P-type impurity in the well 291, phosphorus (P) is contained As an N-type impurity in the N-type low concentration impurity diffusion layer 292, and arsenic (As) is contained As an N-type impurity in the N-type high concentration impurity diffusion layer 293. For example, the gate length of the transistor TrC is 110nm to 180nm. The gate insulating film 294 is a silicon oxide film having a thickness of 6nm to 7 nm. Gate 295 is an amorphous silicon film having a thickness of 40nm to 60nm. The sidewall insulating film 296 is a silicon oxide film having a thickness of 35nm to 55 nm. A silicide film such as a tungsten silicide (WSi) film having a thickness of 120nm to 180nm may be formed on the surface of the gate electrode 295 and on the surface of the high concentration impurity diffusion layer 293.

As with the transistor TrC, the transistors TrL and TrP also include a well, an impurity diffusion layer, a gate insulating film, a gate electrode, and a sidewall insulating film. In fig. 5 and the like, the gate electrode and the like of the transistor TrP are arranged on the element isolation insulating film 202, which means that the gate electrode and the like of the transistor TrP include a portion extending to the element isolation insulating film 202. Like the transistor TrP, the gate electrode or the like of the transistor TrL also includes a portion extending to the element isolation insulating film 202.

An insulating film 203 covering the transistor TrC, the transistor TrL, and the transistor TrP is formed over the substrate 201, and an interlayer insulating film 204 is formed over the insulating film 203. The insulating film 203 is, for example, a silicon oxynitride film (SiON film), and the interlayer insulating film 204 is an undoped silicate glass (NSG) film having a flat surface.

An oxidation preventing film 211 is formed on the interlayer insulating film 204, and an interlayer insulating film 212 is formed on the oxidation preventing film 211. An oxidation preventing film 213 is formed on the interlayer insulating film 212, and an interlayer insulating film 214 is formed on the oxidation preventing film 213. For example, the oxidation preventing film 211 and the oxidation preventing film 213 are silicon nitride (SiN) films, and the interlayer insulating film 212 and the interlayer insulating film 214 are silicon oxide films. The nitrogen content of the oxidation resistant film 213 is lower than that of the oxidation resistant film 211, and the hydrogen permeation rate of the oxidation resistant film 213 is higher than that of the oxidation resistant film 211. For example, in analysis by X-ray photoelectron spectroscopy, the oxidation resistant film 211 does not show a si—o bond peak (bond peak); however, the oxidation resistant film 213 shows si—o bond peaks. That is, the oxidation resistant film 213 exhibits a Si-O bond peak larger than that of the oxidation resistant film 211. The hydrogen permeability and the oxygen permeability of the interlayer insulating film 212 and the interlayer insulating film 214 are higher than those of the oxidation resistant film 211 and the oxidation resistant film 213. For example, the nitrogen content of the oxidation preventing film 213 is 40.0 at% or more and less than 45.0 at%, and the ratio of the N content to the Si content in the oxidation preventing film 213 is 0.70 or more and less than 1.00. However, the nitrogen content of the oxidation resistant film 211 is 45.0 at% or more and 50.0 at% or less, and the ratio of the N content to the Si content in the oxidation resistant film 211 is 1.00 or more and 1.30 or less. Therefore, the degree of nitridation in the oxidation resistant film 213 is lower than that in the oxidation resistant film 211. The oxidation preventing film 211 and the oxidation preventing film 213 are formed on the memory cell portion 1, the logic circuit portion 2, the peripheral circuit portion 3, and the pad portion 4, so that the oxidation preventing film 211 and the oxidation preventing film 213 are provided on the entire semiconductor device 200 in plan view.

In the memory cell section 1, a ferroelectric capacitor Q having a lower electrode 221, a ferroelectric film 222, and an upper electrode 223 is formed on the interlayer insulating film 214. For example, the lower electrode 221 includes an iridium (Ir) film, the ferroelectric film 222 includes a lead zirconate titanate (PZT) film, and the upper electrode 223 includes iridium oxide (IrO) _x ) And (3) a film. A barrier film 231 is formed on the interlayer insulating film 214 to cover the upper surface and the side surfaces of each ferroelectric capacitor Q. Such as alumina (AlO) _x ) The hydrogen permeability of the barrier film 231 such as a film is lower than that of the oxidation-resistant film 213, and the oxygen permeability of the barrier film 231 is lower than that of the interlayer insulating film 212 and the interlayer insulating film 214. The barrier film 231 is formed on the memory cell portion 1, the logic circuit portion 2, the peripheral circuit portion 3, and the pad portion 4 such that the barrier film 231 is disposed on the entire semiconductor device 200 in plan view. An interlayer insulating film 232 is formed on the barrier film 231. For example, the interlayer insulating film 232 is a silicon oxide film having a flat surface.

In the memory cell portion 1, openings (contact holes) 205C are each formed in the insulating film 203 and the interlayer insulating film 204, and conductive plugs 206C are formed in the openings 205C. The conductive plug 206C is electrically connected to the high concentration impurity diffusion layer of the transistor TrC. An opening (wiring trench) 215 is formed in the oxidation preventing film 211 and the interlayer insulating film 212, and a wiring 216 is formed in the opening 215. Openings (through holes) 217 are each formed in the oxidation preventing film 213 and the interlayer insulating film 214, and a conductive plug 218 is formed in the opening 217. Openings (through holes) 233 are each formed in the barrier film 231 and the interlayer insulating film 232, and a conductive plug 235C is formed in the opening 233. For example, conductive plug 206C, wire 216, conductive plug 218, and conductive plug 235C include tungsten (W) films. A portion of the wiring 216 serves as a conductive base for electrically connecting the conductive plug 206C and the conductive plug 218 to each other.

In the logic circuit portion 2, an opening (contact hole) 205L is formed in the insulating film 203 and the interlayer insulating film 204, and a conductive plug 206L is formed in the opening 205L. The conductive plug 206L is electrically connected to the high concentration impurity diffusion layer of the transistor TrL. Openings (through holes) 234L are each formed in the oxidation preventing film 211, the interlayer insulating film 212, the oxidation preventing film 213, the interlayer insulating film 214, the barrier film 231, and the interlayer insulating film 232, and a conductive plug 235L is formed in the opening 234L. For example,

conductive plugs

206L and 235L include tungsten (W) films.

In the peripheral circuit section 3, an opening (contact hole) 205P is formed in the insulating film 203 and the interlayer insulating film 204, and a conductive plug 206P is formed in the opening 205P. The conductive plug 206P is electrically connected to the gate of the transistor TrP. An opening (via) 234P is formed in the oxidation preventing film 211, the interlayer insulating film 212, the oxidation preventing film 213, the interlayer insulating film 214, the barrier film 231, and the interlayer insulating film 232, and a conductive plug 235P is formed in the opening 234P. For example,

conductive plugs

206P and 235P include tungsten (W) films.

A wiring 241C connected to the conductive plug 235C, a wiring 241L connected to the conductive plug 235L, and a wiring 241P connected to the conductive plug 235P are formed on the interlayer insulating film 232. A flat interlayer insulating film 242 covering the wiring 241C, the wiring 241L, and the wiring 241P is formed on the interlayer insulating film 232. In the pad portion 4, a pad is formed on the outermost surface.

The circuit configuration of the memory cell section 1 is described below. Fig. 7 is a view showing a circuit configuration of the memory cell section.

As shown in fig. 7, the memory cell section 1 includes a memory cell MC having one transistor TrC and one ferroelectric capacitor Q. A gate 295 of the transistor TrC is included in the word line WL, a wiring 241C is included in the plate line PL, and the transistor TrC and the ferroelectric capacitor Q are electrically connected via the conductive plug 206C, the wiring 216, and the conductive plug 218. Fig. 5 shows portions corresponding to the regions 21 of the two memory cells in fig. 7, and a wiring 216 connected to a high-concentration impurity diffusion layer 293 (see fig. 6) is included as a local interconnect in the bit line BL, the high-concentration impurity diffusion layer 293 being common to the two transistors TrC.

Next, a method of manufacturing the semiconductor device 200 according to the second embodiment will be described. Fig. 8A to 8E are cross-sectional views showing a manufacturing method of the semiconductor device 200 according to the second embodiment in the order of steps.

First, as shown in fig. 8A, an element isolation insulating film 202 for Shallow Trench Isolation (STI) is formed on the surface of a substrate 201. Subsequently, a transistor TrC is formed in the element region in the memory cell portion 1, a transistor TrL is formed in the element region in the logic circuit portion 2, and a transistor TrP is formed in the element region in the peripheral circuit portion 3. Forming each transistor TrC may include, for example: forming a well 291 by boron (B) ion implantation; forming a gate insulating film 294 and a gate 295; forming a low concentration impurity diffusion layer 292 by phosphorus (P) ion implantation using the gate electrode 295 as a mask; forming a sidewall insulating film 296; the high-concentration impurity diffusion layer 293 is formed by arsenic (As) ion implantation using the gate electrode 295 and the sidewall insulating film 296 As masks. Forming the transistors TrL and TrP may include forming transistors having a plurality of sizes and conductivity types according to an integrated circuit.

After the transistors TrC, trL, and TrP are formed, as shown in fig. 8B, an insulating film 203 covering the transistors TrC, trL, and TrP is formed. For example, a silicon oxynitride film (SiON film) which is formed by a plasma Chemical Vapor Deposition (CVD) method and has a thickness of 160nm to 240nm may be used as the insulating film 203. Subsequently, an interlayer insulating film 204 is formed over the insulating film 203, and the surface of the interlayer insulating film 204 is planarized. For example, an NSG film which is formed by a plasma CVD method using tetraethyl orthosilicate (TEOS) and has a thickness of 480nm to 720nm may be used as the interlayer insulating film 204. The thickness of the interlayer insulating film 204 may be 1000nm to 1200nm. In the planarization process of the surface of the interlayer insulating film 204, the surface of the interlayer insulating film 204 is polished 160nm to 240nm by a Chemical Mechanical Polishing (CMP) method.

After that, as shown in fig. 8C, a resist pattern 251 is formed on the interlayer insulating film 204. The resist pattern 251 includes an opening 252C, an opening 252L, and an opening 252P, wherein the opening 252C exposes a predetermined contact hole forming region in the memory cell portion 1, the opening 252L exposes a predetermined contact hole forming region in the logic circuit portion 2, and the opening 252P exposes a predetermined contact hole forming region in the peripheral circuit portion 3. Subsequently, the interlayer insulating film 204 and the insulating film 203 are etched using the resist pattern 251 as a mask. As a result, an opening (contact hole) 205C is formed in the memory cell portion 1, an opening (contact hole) 205L is formed in the logic circuit portion 2, and an opening (contact hole) 205P is formed in the peripheral circuit portion 3.

Subsequently, as shown in fig. 8D, the resist pattern 251 is removed, a conductive plug 206C is formed in the opening 205C, a conductive plug 206L is formed in the opening 205L, and a conductive plug 206P is formed in the opening 205P. Forming the

conductive plugs

206C, 206L, and 206P may include, for example: forming a barrier metal film by a Physical Vapor Deposition (PVD) method; forming a tungsten (W) film on the barrier metal film by a CVD method; the barrier metal film and the W film on the interlayer insulating film 204 are removed. Forming the barrier metal film may include, for example: forming a titanium (Ti) film having a thickness of 16nm to 24nm; a titanium nitride (TiN) film is formed on the titanium (Ti) film, the titanium nitride (TiN) film having a thickness of 40nm to 60nm. The thickness of the W film is 400nm to 600nm. For example, the barrier metal film and the W film located on the interlayer insulating film 204 may be removed by a CMP method.

Thereafter, as shown in fig. 8E, an oxidation-resistant film 211 is formed on the interlayer insulating film 204, the conductive plugs 206C, the conductive plugs 206L, and the conductive plugs 206P. For example, a first silicon nitride (SiN) film which is formed by a CVD method and has a thickness of 32nm to 48nm may be used as the oxidation resistant film 211. In the process of forming the first SiN film, for example, silane (SiH ₄ ) As a raw material for Si; ammonia (NH) ₃ ) Or nitrous oxide (N) ₂ O) or ammonia (NH) ₃ ) And nitrous oxide (N) ₂ O) both are used as starting materials for N; the ratio of the supply amount of N atoms to the first N/Si of the supply amount of Si atoms was 190:230.

Subsequently, as shown in fig. 8F, an interlayer insulating film 212 is formed on the oxidation resistant film 211. For example, a silicon oxide film which is formed by a plasma CVD method using tetraethyl orthosilicate (TEOS) and has a thickness of 200nm to 300nm may be used as the interlayer insulating film 212.

Next, as shown in fig. 8G, a resist pattern 253 is formed on the interlayer insulating film 212. The resist pattern 253 has an opening portion 254, and the opening portion 254 exposes a predetermined wiring trench forming region located in the memory cell portion 1. After that, the interlayer insulating film 212 and the oxidation resistant film 211 are etched using the resist pattern 253 as a mask. As a result, an opening (wiring trench) 215 is formed in the memory cell portion 1.

Subsequently, as shown in fig. 8H, the resist pattern 253 is removed, and the wiring 216 is formed in the opening 215. Forming the wiring 216 may include, for example: a barrier metal film is formed by a PVD method, a W film is formed on the barrier metal film by a CVD method, and the barrier metal film and the W film on the interlayer insulating film 212 are removed. Forming the barrier metal film may include, for example, forming a Ti film having a thickness of 8nm to 12nm and forming a TiN film having a thickness of 16nm to 24nm on the Ti film. The thickness of the W film is 240nm to 360nm. For example, the barrier metal film and the W film located on the interlayer insulating film 212 may be removed by a CMP method.

Subsequently, as shown in fig. 8I, an oxidation preventing film 213 is formed over the interlayer insulating film 212 and the wiring 216. For example, a second silicon nitride (SiN) film, which is formed by a CVD method and has a thickness of 80nm to 180nm, may be used as the oxidation resistant film 213. In the process of forming the first SiN film, for example, silane (SiH ₄ ) As a raw material for Si; ammonia (NH) ₃ ) Or nitrous oxide (N) ₂ O) or ammonia (NH) ₃ ) And nitrous oxide (N) ₂ O) both are used as starting materials for N; the second N/Si ratio of the supply amount of N atoms to the supply amount of Si atoms is smaller than the first N/Si ratio. For example, the second N/Si ratio is 100 to 185.

Subsequently, as shown in fig. 8J, an interlayer insulating film 214 is formed on the oxidation resistant film 213. For example, a silicon oxide film which is formed by a plasma CVD method using TEOS and has a thickness of 180nm to 280nm may be used as the interlayer insulating film 214.

Subsequently, as shown in fig. 8K, a resist pattern 255 is formed on the interlayer insulating film 214. The resist pattern 255 has an opening 256, and the opening 256 exposes a predetermined via forming region in the memory cell portion 1. Subsequently, the interlayer insulating film 214 and the oxidation resistant film 213 are etched using the resist pattern 255 as a mask. As a result, an opening (through hole) 217 is formed in the memory cell portion 1.

Subsequently, as shown in fig. 8L, the resist pattern 255 is removed, and a conductive plug 218 is formed in the opening 217. Forming the conductive plug 218 may include, for example: forming a barrier metal film by a PVD method; forming a W film on the barrier metal film by a CVD method; the barrier metal film and the W film on the interlayer insulating film 214 are removed. Forming the barrier metal film may include, for example, forming a Ti film having a thickness of 8nm to 12nm and forming a TiN film having a thickness of 16nm to 24nm on the Ti film. The thickness of the W film is 240nm to 360nm. For example, the barrier metal film and the W film located on the interlayer insulating film 214 may be removed by a CMP method.

Thereafter, as shown in fig. 8M, a lower electrode 221, a ferroelectric film 222, an upper electrode 223, a hard mask 224, and an insulating film 225 are sequentially formed with respect to the interlayer insulating film 214 and the conductive plug 218. For example, an iridium (Ir) film which is formed by a PVD method and has a thickness of 40nm to 60nm may be used as the lower electrode 221. For example, a PZT film having a thickness of 75nm to 85nm may be used as the ferroelectric film 222. For example, iridium oxide (IrO) _x ) A film may be used as the upper electrode 223, iridium oxide (IrO _x ) The film is formed by PVD method and has a thickness of 160nm to 240nm. A titanium aluminum nitride (TiAlN) film, which is formed by a PVD method and has a thickness of 160nm to 240nm, may be used as the hard mask 224. For example, a silicon oxide film which is formed by a plasma CVD method using TEOS and has a thickness of 160nm to 240nm may be used as the insulating film 225. A crystallization anneal may be performed between forming the ferroelectric film 222 and forming the upper electrode 223 to promote crystallization of the ferroelectric film 222.

Subsequently, as illustrated in fig. 8N, a resist pattern 257 is formed on the insulating film 225. The resist pattern 257 covers a predetermined ferroelectric capacitor forming area and exposes the remaining portion. Subsequently, etching is performed on the insulating film 225, the hard mask 224, the upper electrode 223, the ferroelectric film 222, and the lower electrode 221 using the resist pattern 257 as a mask. As a result, the ferroelectric capacitor Q is formed.

After that, as shown in fig. 8O, the resist pattern 257, the insulating film 225, and the hard mask 224 are removed, and the surface of the ferroelectric capacitor Q is cleaned, for example, using a scrubber.

Subsequently, recovery annealing is performed in an oxygen atmosphere to solve the problem of oxygen deficiency occurring in the ferroelectric film 222. For example, the recovery annealing temperature may be 300 ℃ to 400 ℃, and the recovery annealing time may be 30 minutes to 60 minutes. In this recovery annealing process, the problem of oxygen deficiency is solved, and as shown in fig. 8P, hydrogen generated by water decomposition in the interlayer insulating film 212 and hydrogen generated by water decomposition in the interlayer insulating film 214 are purged. In addition, since the oxidation preventing film 213 and the oxidation preventing film 211 prevent oxygen from penetrating, oxygen is prevented from penetrating under the oxidation preventing film 213 and the oxidation preventing film 211. Accordingly, oxidation of the conductive plug 206C, the wiring 216, and the like is prevented.

Next, as shown in fig. 8Q, a barrier film 231 is formed, the barrier film 231 covering the upper surface and the side surface of each ferroelectric capacitor Q. For example, alumina (AlO) _x ) The film may be used as a barrier film 231, aluminum oxide (AlO _x ) The film is formed by a PVD method or a CVD method and has a thickness of 10nm to 30nm.

After that, as shown in fig. 8R, an interlayer insulating film 232 is formed on the barrier film 231, and the surface of the interlayer insulating film 232 is planarized. For example, a silicon oxide film which is formed by a plasma CVD method using TEOS and has a thickness of 1200nm to 1800nm may be used as the interlayer insulating film 232. In the process of planarizing the surface of the interlayer insulating film 232, the surface of the interlayer insulating film 232 is polished by a CMP method.

Subsequently, as shown in fig. 8S, a resist pattern 259 is formed on the interlayer insulating film 232. The resist pattern 259 has an opening 260, and the opening 260 exposes a predetermined via forming region in the memory cell portion 1. Subsequently, the interlayer insulating film 232 and the barrier film 231 are etched using the resist pattern 259 as a mask. As a result, an opening (through hole) 233 is formed in the memory cell portion 1.

Next, as shown in fig. 8T, the resist pattern 259 is removed.

Thereafter, as shown in fig. 8U, a resist pattern 261 is formed on the interlayer insulating film 232 and also inside the opening 233. The resist pattern 261 includes an opening 262L and an opening 262P, the opening 262L exposing a predetermined via forming region located in the logic circuit portion 2, and the opening 262P exposing a predetermined via forming region located in the peripheral circuit portion 3. Subsequently, etching is performed on the interlayer insulating film 232, the barrier film 231, the interlayer insulating film 214, the oxidation preventing film 213, the interlayer insulating film 212, and the oxidation preventing film 211 using the resist pattern 261 as a mask. As a result, an opening (via) 234L is formed in the logic circuit portion 2, and an opening (via) 234P is formed in the peripheral circuit portion 3.

Subsequently, as shown in fig. 8V, the resist pattern 261 is removed.

Thereafter, as shown in fig. 8W, a conductive plug 235C is formed in the opening 233, a conductive plug 235L is formed in the opening 234L, and a conductive plug 235P is formed in the opening 234P. Forming conductive plugs 235C, conductive plugs 235L, and conductive plugs 235P may include, for example: forming a TiN film as a barrier metal film by a PVD method; forming a W film on the barrier metal film by a CVD method; and removing the TiN film and the W film located on the interlayer insulating film 232. The thickness of the TiN film is 80nm to 120nm, and the thickness of the W film is 240nm to 360nm. For example, the TiN film and the W film located on the interlayer insulating film 232 may be removed by a CMP method.

Subsequently, as shown in fig. 8X, a wiring 241C is formed over the conductive plug 235C, a wiring 241L is formed over the conductive plug 235L, and a wiring 241P is formed over the conductive plug 235P. Subsequently, an interlayer insulating film 242 is formed, and the interlayer insulating film 242 covers the wiring 241C, the wiring 241L, and the wiring 241P, and the surface of the interlayer insulating film 242 is planarized.

Further, upper layer wirings, pads, and the like are formed to complete the semiconductor device 200.

In the semiconductor device 200, as described above, since the oxidation preventing film 211 has the lowest hydrogen permeability among the oxidation preventing film 211, the interlayer insulating film 212, the oxidation preventing film 213, and the interlayer insulating film 214, hydrogen generated in the interlayer insulating film 212 and hydrogen generated in the interlayer insulating film 214 are released upward over the interlayer insulating film 214. Therefore, even when the barrier film 231 is exposed to a temperature at which moisture can be decomposed at the time of formation of an upper layer wiring or the like after formation, deterioration of the ferroelectric capacitor Q due to moisture contained in the interlayer insulating film 212 and the interlayer insulating film 214 does not easily occur. In addition, deterioration of the ferroelectric capacitor Q due to long-term use is also less likely to occur. Accordingly, the deterioration of the ferroelectric capacitor Q due to hydrogen can be further reduced.

After the formation of the interlayer insulating film 212 and before the formation of the oxidation resistant film 213, hydrogen contained in the interlayer insulating film 212 can be desorbed by annealing. Therefore, hydrogen generated in the interlayer insulating film 212 can be further reduced, which can further reduce degradation of the ferroelectric capacitor Q.

Note that the interlayer insulating film 204 also contains moisture; however, this moisture may be decomposed during the recovery anneal to desorb hydrogen through the wiring 216. Even if moisture remains in the interlayer insulating film 212 after the recovery annealing, the distance between the interlayer insulating film 212 and the ferroelectric capacitor Q is large, so that any moisture remaining in the interlayer insulating film 212 does not cause deterioration of the ferroelectric capacitor Q.

In addition, the lower the nitrogen content, the more easily the silicon nitride film contains oxygen atoms; therefore, the etching selectivity (i.e., the ratio of etching rates) of the silicon nitride film and the silicon oxide film becomes small. Therefore, the etching selectivity of forming the opening 215 in the oxidation resistant film 211 is higher than that of forming the opening 217 in the oxidation resistant film 213. In the second embodiment, since the oxidation preventing film 211 does not need to be permeated with hydrogen, the nitrogen content of the silicon nitride film used in the oxidation preventing film 211 is higher than the nitrogen content in the oxidation preventing film 213 in consideration of the processing accuracy of the opening portion 215.

An experiment is shown below, which is conducted with respect to the relationship between the nitrogen content and the hydrogen permeability in the silicon nitride film. Fig. 9 is a cross-sectional view showing a sample used in the experiment.

In this experiment, two samples were used; as shown in fig. 9, each sample was carried out by forming a silicon oxide film 302 on a silicon substrate 301, forming a silicon nitride film 303 on the silicon oxide film 302, and forming a silicon oxide film 304 on the silicon nitride film 303And (3) preparation. In this experiment, the conditions for forming the silicon oxide film 302 and the silicon oxide film 304 were the same in the two samples, while the conditions for forming the silicon nitride film 303 were different in the two samples. In the first sample, the ratio of N/Si (atomic ratio) of the supply amount of N atoms to the supply amount of Si atoms was set to 142 at the time of forming the silicon nitride film 303. In the second sample, the ratio of N/Si (atomic ratio) of the supply amount of N atoms to the supply amount of Si atoms was set to 211 at the time of forming the silicon nitride film 303. Specifically, in the first sample, siH is used when the silicon nitride film 303 is formed ₄ The flow rate of (C) is 155sccm, NH ₃ Is 900 flow rate; in the second sample, the flow rate of SiH was 480sccm and NH at the time of formation of the silicon nitride film 303 ₃ Is 3850. Then, annealing was performed at 350 ℃ for 40 minutes under an oxygen atmosphere, and the hydrogen concentration in the silicon oxide film 302, the silicon nitride film 303, and the silicon oxide film 304 was measured by a Secondary Ion Mass Spectrometry (SIMS) method before and after annealing.

Fig. 10A shows experimental results of the first sample, and fig. 10B shows experimental results of the second sample. The horizontal axis in fig. 10A and 10B represents the depth from the surface of the silicon oxide film 304. As shown in fig. 10A, for the first sample, the hydrogen concentration after annealing was greatly reduced compared to the hydrogen concentration in all of the silicon oxide film 302, the silicon nitride film 303, and the silicon oxide film 304 before annealing was performed. For the second sample, the hydrogen concentration after annealing was greatly reduced compared to the hydrogen concentration in the silicon oxide film 304 before annealing was performed. However, in the silicon nitride film 303 and the silicon oxide film 302, the hydrogen concentration after annealing is hardly reduced as compared with the hydrogen concentration before annealing. These results indicate that the hydrogen permeability of the silicon nitride film 303 of the first sample is higher than that of the silicon nitride film 303 of the second sample, which makes the silicon nitride film 303 of the first sample suitable for the oxidation resistant film 213 and the silicon nitride film 303 of the second sample suitable for the oxidation resistant film 211.

The examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification embody the superiority and inferiority of the invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, modifications and alterations can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

a substrate;

a transistor formed on a surface of the substrate;

a first insulating film formed over the transistor;

a second insulating film formed on the first insulating film;

a third insulating film formed on the second insulating film;

a fourth insulating film formed on the third insulating film; and

a ferroelectric capacitor formed on the fourth insulating film,

wherein the hydrogen permeability and the oxygen permeability of the second insulating film and the fourth insulating film are higher than those of the first insulating film and the third insulating film,

wherein the first insulating film is a first silicon nitride film, the third insulating film is a second silicon nitride film, and the nitrogen content of the second silicon nitride film is lower than that of the first silicon nitride film.

2. The semiconductor device according to claim 1, wherein an analysis by X-ray photoelectron spectroscopy shows that a Si-O bond peak of the third insulating film is larger than a Si-O bond peak of the first insulating film.

3. The semiconductor device according to claim 1 or 2, further comprising:

a fifth insulating film which is formed on the first insulating film,

wherein the fifth insulating film is formed on the fourth insulating film,

the fifth insulating film covers the upper surface and the side surfaces of the ferroelectric capacitor,

the hydrogen permeability of the fifth insulating film is lower than that of the third insulating film,

the fifth insulating film has an oxygen permeability lower than that of the second insulating film and the fourth insulating film.

4. The semiconductor device according to claim 3, wherein the fifth insulating film is an aluminum nitride film.

5. The semiconductor device according to claim 1 or 2, further comprising:

a first conductor formed in the first insulating film and the second insulating film;

a second conductor formed in the third insulating film and the fourth insulating film, the second conductor being connected to the first conductor and the ferroelectric capacitor; and

and a third conductor in contact with a lower surface of the first conductor, the third conductor being connected to the transistor.

6. The semiconductor device of claim 5, further comprising:

a fourth conductor formed in the first insulating film and the second insulating film; and

and a fifth conductor in contact with a lower surface of the fourth conductor and connected to the transistor.

7. The semiconductor device according to claim 1 or 2, wherein the first insulating film and the third insulating film are provided over the entire semiconductor device in a plan view.

8. A method of manufacturing a semiconductor device, comprising:

forming a transistor on a surface of a substrate;

forming an insulating film over the transistor;

forming a ferroelectric capacitor on the fourth insulating film; and

annealing is performed to desorb hydrogen contained in the second insulating film and the fourth insulating film,

9. The method according to claim 8, wherein the method comprises,

wherein a first N/Si ratio represents a ratio of a supply amount of nitrogen atoms to a supply amount of silicon atoms at the time of forming the first insulating film,

the second N/Si ratio represents the ratio of the supply amount of nitrogen atoms to the supply amount of silicon atoms at the time of forming the third insulating film, an

The second N/Si ratio is lower than the first N/Si ratio.

10. The method of claim 8 or 9, further comprising:

forming a fifth insulating film on the fourth insulating film,

wherein the fifth insulating film covers the upper surface and the side surfaces of the ferroelectric capacitor,

11. The method of claim 10, wherein the fifth insulating film is an aluminum nitride film.

12. The method of claim 8 or 9, further comprising:

annealing is performed between forming the second insulating film and forming the third insulating film to desorb hydrogen contained in the second insulating film.