CN110098164A - 用于半导体部件的同轴互连结构 - Google Patents

用于半导体部件的同轴互连结构 Download PDF

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Publication number
CN110098164A
CN110098164A CN201811279333.7A CN201811279333A CN110098164A CN 110098164 A CN110098164 A CN 110098164A CN 201811279333 A CN201811279333 A CN 201811279333A CN 110098164 A CN110098164 A CN 110098164A
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China
Prior art keywords
semiconductor component
signal
interconnection structure
bare die
package substrate
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Pending
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CN201811279333.7A
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English (en)
Inventor
M·雅各布斯
张丽娟
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Publication of CN110098164A publication Critical patent/CN110098164A/zh
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Abstract

本公开涉及用于半导体部件的同轴互连结构,具体描述了集成到半导体部件中的同轴互连结构以及形成同轴互连结构的方法。将集成电路(IC)裸片的电路电耦合至封装衬底的迹线的同轴互连结构包括绕轴线延伸的信号芯、绕轴线延伸的接地屏蔽以及设置在信号芯与接地屏蔽之间的绝缘体。

Description

用于半导体部件的同轴互连结构
相关申请的交叉参考
本公开要求2018年1月29日提交的美国临时专利申请第62/623,416号的优先权,其公开的全部内容通过引证引入本文。
技术领域
本公开涉及用于半导体部件的同轴互连结构。
背景技术
本文提供的背景描述是为了一般地呈现本公开的应用环境的目的。除非本文另有说明,否则本部分中描述的方法不是本公开的权利要求的现有技术,并且不通过包括在本章节中而被承认为现有技术。
在无线网络工业中,半导体部件可在超过例如2.4千兆赫(GHz)的高速频率下工作。为了适应这种高速频率并改善半导体部件的信号性能,半导体部件的封装衬底或集成电路(IC)裸片可结合包括接地平面或接地迹线的结构。
半导体部件还可以包括导电柱形式的互连结构。这种互连结构通常直接制造在IC裸片的焊盘上,用作将IC裸片附接至衬底的机制,并且还为从IC裸片的电路发出的信号提供通道。如今,与互连结构相关的设计和制造技术使得相邻的互连结构彼此暴露。与在半导体部件的部分中结合接地平面或接地迹线相关联的努力相反,互连结构的暴露性质会由于信号损失或信号干扰而导致信号劣化。
发明内容
提供本发明内容以介绍在详细描述和附图中进一步描述的主题。因此,本发明内容不应被认为描述了基本特征,也不用于限制所要求主题的范围。
本公开描述了集成到半导体部件中的同轴互连结构以及形成同轴互连结构的方法。将集成电路(IC)裸片的电路电耦合至封装衬底的迹线的同轴互连结构包括绕轴线延伸的信号芯、绕轴线延伸的接地屏蔽、以及设置在信号芯与接地屏蔽之间的绝缘体。
在一些方面中,描述了一种半导体部件。该半导体部件包括:封装衬底,具有由封装衬底的独立导电层形成的对应的信号迹线和接地迹线;集成电路(IC)裸片,具有信号焊盘和接地焊盘;以及同轴互连结构,将IC裸片的信号焊盘和接地焊盘电耦合至封装衬底的对应的信号迹线和接地迹线。同轴互连结构包括绕轴线延伸的信号芯,该轴线(i)与包含信号焊盘和接地焊盘的IC裸片的平面正交以及(ii)与包含对应的信号迹线和接地迹线的封装衬底的平面正交。同轴互连结构还包括绕轴线延伸并设置为围绕信号芯的周界的接地屏蔽、以及布置在信号芯和接地屏蔽之间的绝缘体。
在其它方面中,描述了一种半导体部件。该半导体部件包括:封装衬底,具有由封装衬底的公共导电层形成的对应的信号迹线和接地迹线;集成电路(IC)裸片,具有信号焊盘和接地焊盘;以及同轴互连结构,将IC裸片的信号焊盘和接地焊盘电耦合至封装衬底的对应的信号迹线和接地迹线。同轴互连结构包括绕轴线延伸的信号芯,该轴线(i)与包含信号焊盘和接地焊盘的IC裸片的平面正交以及(ii)与包含对应的信号迹线和接地迹线的封装衬底的平面正交。同轴互连结构还包括绕轴线延伸并设置为围绕信号芯的周界的一部分的接地屏蔽以及设置在信号芯与接地屏蔽之间的绝缘体。
在其它方面中,描述了形成同轴互连结构的方法。该方法包括:在包括信号互连焊盘的材料堆叠上沉积第一导电材料;以及在第一导电材料上沉积光刻胶材料的第一涂层。经由包括照射和去除光刻胶材料的第一涂层的相同部分的第一光刻操作,暴露第一导电材料的一部分。第二导电材料沉积在第一导电材料的暴露部分上。光刻胶材料的第一涂层的剩余部分被去除,以暴露第一导电材料的一部分,并且蚀刻第一导电材料的暴露部分,以得到绕轴线延伸的信号芯。在包括信号芯的材料堆叠上沉积介电材料,并且在介电材料上沉积光刻胶材料的第二涂层。经由包括照射和去除光刻胶材料的第二涂层的相同部分的第二光刻操作,暴露介电材料的一部分。去除介电材料的暴露部分,并且去除光刻胶材料的第二涂层的剩余部分,以得到绕轴线延伸的绝缘体。第三导电材料沉积到包括信号芯和绝缘体的材料堆叠上,并且光刻胶材料的第三涂层被沉积在第三导电材料上。经由包括照射和去除光刻胶材料的第三涂层的相同部分的第三光刻操作,暴露第三导电材料的一部分。去除第三导电材料的暴露部分,并且去除光刻胶材料的第三涂层的剩余部分,以得到绕轴线延伸的接地屏蔽。然后,对信号芯、绝缘体和接地屏蔽进行抛光以得到同轴互连结构。
在附图和以下描述中阐述了一个或多个实施方式的细节。其他特征和优点将从说明书和附图以及权利要求中显而易见。
附图说明
下面描述同轴互连结构的一个或多个方面的细节。在说明书和附图中使用相同的参考标号可以指示类似的元件:
图1示出了根据一个或多个实施方式的用于制造具有同轴互连结构的半导体部件的示例性操作环境。
图2示出了根据一个或多个实施方式的示例性同轴互连结构的细节。
图3示出了根据一个或多个实施方式的另一示例同轴互连结构的细节。
图4a至图4c示出了根据一个或多个实施方式的用于制造集成电路裸片以具有同轴互连结构的示例性方法。
图5a至图5f示出了根据一个或多个实施方式的具有同轴互连结构的集成电路裸片在不同制造阶段期间的截面的示例性细节。
具体实施方式
作为制造半导体部件的一部分,集成电路(IC)裸片可以在组装制造工艺期间与封装衬底(有时被称为中介层)组合以得到半导体部件。半导体部件的互连结构将裸片电耦合至封装衬底,用于在IC裸片和封装衬底之间传播信号。在特定情况下,互连结构包括将IC裸片的焊盘连接至封装衬底的焊盘的导电接合线,而在其他情况下,互连结构可以是将IC裸片的焊盘连接至衬底的焊盘的柱或焊球形式的凸起。
接合线可使用诸如铝(Al)、铜(Cu)、银(Ag)或金(Au)的材料制造。然而,由于它们的长度,接合线易于受到由与电感相关的寄生效应而导致的信号损失。
柱可由诸如铜(Cu)的材料制造。通常,与接合线相比,柱具有改进的高频信号性能,部分原因是它们的长度缩短。然而,作为传统半导体部件制造工艺的一部分,在晶圆制造工艺或封装组装工艺期间,这些柱暴露于相邻柱,使得每个柱受到来自对应相邻柱的干扰或“串扰”。
依赖于半导体制造工艺的一种新型互连结构结合有信号芯、电介质和屏蔽,作为设置在集成电路(IC)裸片和封装衬底之间的同轴信号机制的一部分。同轴互连结构对于可用作高频(例如,≥2.4GHz)下操作的半导体部件的一部分的高频信号实现了改进的信令性能。本公开描述了用于制造这种作为半导体部件的一部分的同轴互连结构的方法和装置。
操作环境
图1示出了根据一个或多个实施方式的用于制造具有同轴互连结构的半导体部件的示例性操作环境100。
如图所示,半导体晶圆制造设施102包括半导体晶圆制造工具组。半导体晶圆制造工具组包括电镀工具104、光刻曝光工具106和蚀刻工具108。通常,半导体晶圆制造工具组可以对半导体晶圆110执行制造工艺步骤的序列。
半导体部件112可以被组装为包括具有一个或多个同轴互连件116的集成电路(IC)裸片114。典型地与超大规模集成电路(VLSI)电路相关联的IC裸片114的示例包括逻辑裸片、专用集成电路(ASIC)裸片、芯片上系统(SoC)裸片、存储器裸片(诸如动态随机存取存储器(DRAM)裸片或闪存裸片)等。在一个方面中,利用电镀工具104、光刻曝光工具106和蚀刻工具108的制造工艺步骤的序列可以在半导体晶圆110被切割用于组装成多个半导体部件112之前在半导体晶圆你110上包含的多个IC裸片114上制造同轴互连件116。
通常,电镀工具104可以使用电化学沉积工艺,以在IC裸片114的暴露金属上沉积或“生长”各种金属。暴露的金属(有时被称为晶种金属或凸下金属化(UBM)金属)通常是焊盘形式的导电金属,其向IC裸片114的电路提供相应的导电通道。电镀工具104可沉积的金属的示例包括铜(Cu)、金(Au)、镍(Ni)、钯(Pd)、银(Ag)和锡(Sn)。电镀工具104可以沉积在同轴互连件116的建造中使用的材料,包括可用于信号芯或接地屏蔽的材料。
还可使用其它沉积工具(未示出)来将材料沉积在半导体晶圆110上。其他沉积工具包括化学气相沉积(CVD)工具、物理气相沉积(PVD)工具和溅射工具。在特定情况下,其他沉积工具可将介电材料沉积在半导体晶圆上,而在其他情况下,可以使用其他沉积工具来代替电镀工具104沉积上述金属。
通常,光刻曝光工具106通过图案化的光刻掩模将能量或粒子(诸如紫外线(UV)、极紫外(EUV)光、电子束、离子束或x射线电磁波)曝光或辐射到涂覆半导体晶圆110的光刻胶材料的薄膜上。如光刻胶薄膜所接收的,与图案化光刻掩模相对应的图案可以被显影工具(未示出)显影,以从包括经由蚀刻制造工艺去除的工艺中掩蔽部分材料(例如,由电镀工具104沉积的材料)。由光刻曝光工具106执行的操作实际上可以在同轴互连116的构造期间掩蔽特征不被蚀刻。
通常,蚀刻工具108去除材料的暴露(例如,未掩蔽)部分,以得到与作为由光刻曝光工具106执行的操作的一部分而显影的图案相对应的特征。蚀刻工具108可经由干蚀刻工艺、湿蚀刻工艺等去除材料的暴露部分。蚀刻工具108所用的蚀刻剂可被调整以与一种或多种材料反应(例如,蚀刻一种或多种材料),同时对其他材料保持良性(例如,不蚀刻)。蚀刻工具108可以在同轴互连116的构造期间用于蚀刻限定同轴互连116的特征。
可以在操作环境100内执行电镀、曝光和蚀刻的多重操作,以在半导体晶圆110被切割以组装成多个半导体部件112之前在半导体晶圆110上形成同轴互连件116。值得注意的是,在特定的备选操作环境(未示出)中,可以在封装衬底上形成同轴互连116(使用执行类似操作的其他工具)而不是在半导体晶圆110上。这种备选操作环境可以包括组装或封装设施(未示出),其中最终操作完成半导体部件112的制造。
图2示出了根据一个或多个实施方式的示例性同轴互连结构的细节200。该同轴互连结构可以是图1中的同轴互连件116,如图1的半导体部件112中所包含的。
如侧视图(半导体部件112的一部分的截面图)所示,同轴互连116将IC裸片114的信号焊盘202电耦合至封装衬底206的对应信号迹线204。在该示例中,封装衬底可以是由复合纤维基环氧材料形成的多层印刷电路板(PCB),并且包括多层导电材料,诸如铜(Cu)、铝(Al)等。
同轴互连件116还将IC裸片114的接地焊盘208电耦合至封装衬底206的对应接地迹线210。此外,如该示例性同轴互连结构所示,对应的信号迹线204和对应的接地迹线210由封装衬底206的分开的导电层形成。作为整个同轴互连结构的一部分,诸如锡铅(Sn-Pb)焊接材料的导电材料(由元件212-1和212-2示出)可以包括作为同轴互连结构的一部分。
如图2的截面A-A所示,同轴互连件116由信号芯214、接地屏蔽216和绝缘体218组成。例如,信号芯214可以是导电材料,该导电材料是铜(Cu)材料、钛(Ti)材料或钨(W)材料。例如,接地屏蔽216可以是铜(Cu)材料或锡(Sn)材料的导电材料。例如,绝缘体218可以是聚酰亚胺(PI)材料、聚苯并恶唑(PBO)材料或硼磷硅酸盐玻璃(BPSG)材料的介电材料。
如同同轴互连116的该示例,接地屏蔽216完全包围绝缘体218的周界和信号芯214的周界。
此外,如图2所示,同轴互连件116(例如,信号芯214、接地屏蔽216和绝缘体218中的每一个)绕轴线220延伸,轴线220与包含信号焊盘202和接地焊盘208的IC裸片114的平面正交。轴线220还与包含对应信号迹线204和对应接地迹线210的封装衬底206的平面正交。然而,正交只是一个示例,并且在特定情况下,同轴互连件116可以是“接近”正交或者甚至“偏移”。在这种情况下,备选制造技术可使轴线220相对于与封装衬底206的平面正交的理论轴线呈+/-15°。
图3示出了根据一个或多个实施方式的示例性同轴互连结构的细节300。该同轴互连结构可以是图1中的同轴互连件116,如图1的半导体部件112中所包含的。
如侧视图(半导体部件112的一部分的截面图)所示,同轴互连件116将IC裸片114的信号焊盘302电耦合至封装衬底306的对应信号迹线304。在该示例中,封装衬底是由复合纤维基环氧材料形成的单层印刷电路板(PCB),并且包括诸如铜(Cu)、铝(Al)等的导电材料层。
同轴互连件116还将IC裸片114的接地焊盘308电耦合至封装衬底306的对应接地迹线310。此外,如该示例性同轴互连结构所示,对应信号迹线304和对应接地迹线310由封装衬底306的公共导电层形成。作为整个同轴互连结构的一部分,诸如锡铅(Sn-Pb)焊接材料的导电材料(由元件312-1和312-2示出)可包括作为耦合的一部分。
如图3的截面A-A所示,同轴互连116由信号芯314、接地屏蔽316和绝缘体318组成。例如,信号芯314可以是铜(Cu)材料、钛(Ti)材料或钨(W)材料的导电材料。例如,接地屏蔽316可以是铜(Cu)材料或锡(Sn)材料的导电材料。例如,绝缘体318可以是聚酰亚胺(PI)材料、聚苯并恶唑(PBO)材料或硼磷硅酸盐玻璃(BPSG)材料的介电材料。
如同同轴互连116的该示例,接地屏蔽316包围绝缘体318的周界的一部分和信号芯314的周界的一部分。
此外,如图3所示,同轴互连件116(例如,信号芯314、接地屏蔽316和绝缘体318中的每一个)绕轴线320延伸,轴线320与包含信号焊盘302和接地焊盘308的IC裸片114的平面正交。轴线320还与包含对应信号迹线304和对应接地迹线310的封装衬底306的平面正交。然而,正交性只是一个示例,并且在特定情况下,同轴互连件116可以是“接近”正交或者甚至“偏移”。在这种情况下,备选制造技术可使轴线220相对于与封装衬底206的平面正交的理论轴呈+/-15°。
如图3所示,接地屏蔽316的不连续性使得电耦合至单层封装衬底(例如,具有由公共导电层形成的对应信号迹线304和对应接地迹线310的封装衬底306)。可以形成具有类似不连续性质的其他接地屏蔽,诸如形成为具有多段的接地屏蔽或“柱”,以能够电耦合至单层封装衬底。
用于制造同轴互连结构的技术
图4a至图4c示出了根据一个或多个实施方式的用于制造集成电路裸片以具有同轴互连结构的示例性方法400。同轴互连结构可以是图1的同轴互连件116。图1的半导体晶圆制造工具组(例如,电镀工具104、光刻曝光工具106和蚀刻工具108)可用于在IC裸片114上制造同轴互连件116。图5a至图5f示出了根据一个或多个实施方式的具有同轴互连件116的集成电路芯片114的截面在各个制造阶段期间的示例性细节500。此外,如果示例性方法400没有改变,则图5a至图5f是对由示例性方法400执行的操作的补充。
在图4a的402处,操作将第一导电材料沉积在包括信号焊盘的材料堆叠上。材料堆叠可以是与在制品(WIP)的给定状态相关联的集成电路裸片(例如,IC裸片114)的材料堆叠。
在本示例的背景下且如图5a的细节500所示,对材料堆叠504执行操作502。信号焊盘506被包括作为材料堆叠504的一部分。如图所示,第一导电材料508被沉积在材料堆叠504(包括信号焊盘506)上。例如,第一导电材料508可以通过溅射工具、化学气相沉积(CVD)工具或物理气相沉积工具(图1中未示出)来沉积,并且可以是凸块下金属化(UBM)材料的组合,例如包括元素钛(Ti)、镍(Ni)、铜(Cu)、钨(W)、铝(Al)、铬(Cr)或钒(V)中的一种或多种。信号焊盘506可以电耦合至IC裸片114的功能电路,诸如IC裸片114的输入或输出(I/O)。
继续方法400,如图4a的404所示,操作在第一导电材料上沉积光刻胶材料的第一涂层。光刻胶材料可以是正性光刻胶材料,当被能量源照射时,正性光刻胶材料改变特性,使得可通过显影工具去除(被照射的)光刻胶材料。在进行中的示例的设置中且如图5a的操作510所示,通过涂覆工具(图1中未示出)在第一导电材料508上沉积光刻胶材料512的第一涂层。
继续方法400,在图4a的406中,第一光刻操作照射并去除光刻胶材料的第一涂层的相同部分以暴露第一导电材料的一部分。在该示例中,光刻胶材料是“正性”光刻胶材料。图1的光刻曝光工具106可在配置为横跨IC裸片114掩蔽照射图案的光刻掩模的帮助下,照射光刻胶材料的第一涂层的相同部分,光刻胶材料的该部分随后经由显影工具(图1中未示出)被去除。根据正在进行的示例且如图5a的操作514所示,光刻胶材料512的第一涂层的相同部分(未示出)已经被照射并去除以露出第一导电材料516的一部分。
在图4a的408处,继续方法400。操作将第二导电材料沉积在第一导电材料的暴露部分上。例如,图1的电镀工具104可经由电沉积工艺沉积诸如铜(Cu)材料的材料。可通过图1的电镀工具104或诸如化学气相沉积(CVD)、物理气相沉积(PVD)或溅射工具的另一工具沉积在第一导电材料的暴露部分上的其他示例材料包括钛(Ti)材料或钨(W))材料。在当前示例的背景下且如图5b的操作518所示,第二导电材料520被沉积在第一导电材料516的暴露部分上。
继续方法400,在图4a的410处,操作包括去除光刻胶材料的第一涂层的剩余部分以暴露第一导电材料的一部分,并且蚀刻第一导电材料的暴露部分以得到绕轴线延伸的信号芯。例如,灰化工具(图1中未示出)可去除光刻胶材料的第一涂层的剩余部分,而图1的蚀刻工具108可去除第一导电材料的暴露部分。在这种情况下,蚀刻工具108可以利用第一导电材料与其反应但第二导电材料与其不反应的蚀刻剂。
在当前示例的背景下且如图5b的操作522所示,已经去除了第一材料涂层的剩余部分,并且已经蚀刻了第一材料层的暴露部分来得到信号芯524。此外,如图5b的操作522所示,信号芯524绕轴线526延伸。
在图4a的412处,继续方法400。作为412处的方法的一部分,操作将介电材料沉积到包括信号芯的材料堆叠上。作为一个示例,沉积工具(诸如物理气相沉积(PVD)工具或化学气相沉积(CVD)工具(图1中未示出))可将诸如聚酰亚胺(PI)材料、聚苯并恶唑(PBO)材料或硼磷硅酸盐玻璃(BPSG)材料的介电材料沉积在材料堆叠上。在当前示例的背景下且如图5b的操作528所示,介电材料530已被沉积在包括信号芯524的材料堆叠504上。
继续使用方法400且如图4b的414所示,操作将光刻胶材料的第二涂层沉积在介电材料上。该光刻胶材料可以是正性光刻胶材料,当被能量源照射时,正性光刻胶材料改变特性,使得可以通过显影工具去除(被照射的)光刻胶材料。根据正在进行的示例且如图5c的操作532所示,通过涂覆工具(图1中未示出)将光刻胶材料534的第二涂层沉积在介电材料530上。
继续方法400,在图4b的416处,第二光刻操作照射并去除光刻胶材料的第一涂层的相同部分,以暴露介电材料的一部分。在该示例中,光刻胶材料是“正性”光刻胶材料。图1的光刻曝光工具106可在配置为横跨IC裸片114掩蔽照射图案的光刻掩模的帮助下,照射光刻胶材料的第二涂层的相同部分,光刻胶材料的该部分随后经由显影工具(图1中未示出)被去除。在进行的示例的背景下且如图5c的操作536所示,光刻胶材料534的第二涂层的相同部分(未示出)已经被照射并去除,以露出介电材料538的一部分。
在图4b的418处,继续方法400,去除介电材料的暴露部分。例如,可通过图1的蚀刻工具108来执行操作。在进行中的示例的设置中且如图5c的操作540所示,已经去除了介电材料的暴露部分(在操作536处被示为538)。
在图4b的420处,继续方法400,操作去除光刻胶材料的第二涂层的剩余部分,以得到绕轴线延伸的绝缘体。例如,灰化工具(图1中未示出)可去除光刻胶材料的第二涂层的剩余部分。在进行中的示例的背景下且如图5d的操作542所示,已经去除了光刻胶材料的第二涂层的剩余部分,以得到绕轴线526延伸的绝缘体544。
在图4b的422处,继续方法400,将第三导电材料沉积在材料堆叠(包括信号芯和绝缘体)上。作为示例,第三导电材料的沉积可通过溅射工具、化学气相沉积(CVD)工具或物理气相沉积(PVD)工具(图1中未示出)来执行。作为示例,第三导电材料可以是包括元素镍(Ni)、铜(Cu)、铝(Al)或锡(Sn)中的一种或多种的材料组成。根据正在进行的示例且如图5d的操作546所示,第三导电材料层548已经沉积在包括信号芯524和绝缘体544的材料堆叠504上。
在图4c的424处,继续方法400,操作在第三导电材料上沉积光刻胶材料的第三涂层。光刻胶材料可以是正性光刻胶材料,当被能量源照射时,正性光刻胶材料改变特性,使得可通过显影工具去除(被照射的)光刻胶材料。在进行中的示例的设置中且如图5d的操作550所示,通过涂覆工具(图1中未示出)将光刻胶材料552的第三涂层沉积在第三导电材料548上。
在图4c的426处,继续方法400,其中第三光刻操作照射并去除光刻胶材料的第三涂层的相同部分以暴露第三导电材料的一部分。在该示例中,光刻胶材料是“正性”光刻胶材料。图1的光刻曝光工具106可以在配置为横跨IC裸片114掩蔽照射图案的光刻掩模的帮助下,照射光刻胶材料的第三涂层的相同部分,随后经由显影工具(图1中未示出)去除光刻胶材料的该部分。在进行中的示例的背景下且如图5e的操作554所示,已经照射并去除了光刻胶材料552的第三涂层的相同部分(未示出),以露出第三导电材料556的一部分。
继续方法400,在图4c操作的428处,操作去除第三导电材料的暴露部分。例如,可通过图1的蚀刻工具108来执行该操作。根据正在进行的示例且如图5e的操作558所示,已经去除了介电材料的暴露部分(在操作554处被示为556)。
在图4c的430处,继续方法400,并且操作去除光刻胶材料的第三涂层的剩余部分,以得到绕轴线延伸的接地屏蔽。例如,灰化工具(图1中未示出)可去除光刻胶材料的第三涂层的剩余部分。在当前示例的背景下且如图5e的操作560所示,已经去除了光刻胶材料的第三涂层的剩余部分,以得到绕轴线526延伸的接地屏蔽562。
该方法在图4c的432处继续,操作抛光信号芯、绝缘体和接地屏蔽,以得到同轴互连结构。这种操作可以通过包括电化学抛光工具或减薄工具(图1中未示出)的一个或多个工具来执行。在当前示例的背景下且如图5f的操作564所示,信号芯、绝缘体和接地屏蔽已经被抛光以得到同轴互连结构566。
附加工具可执行将具有这种同轴互连结构566的IC裸片连接至封装衬底作为半导体部件的一部分的操作。例如,这样的工具可以包括热压缩工具(用于热压接合)、分配工具(用于底部填充IC裸片)和焊料回流工具(用于基于焊料的接合)等。
变形例
各种变形例对于同轴互连结构的上述构造以及对于上述制造操作来说是可能的。
作为结构变型的一个示例,用于形成绝缘体的介电材料(例如,图2的绝缘体218)在一些情况下可以是气相(例如,空气)的材料而不是固相的材料。
作为结构变型的另一示例,并且作为先进半导体封装技术的一部分,封装衬底(例如,图2的封装衬底206)可以是硅中介层或具有硅通孔(TSV)互连件的另一集成电路裸片。
作为制造技术的变型例的示例,光刻操作可以基于“负性”光刻胶材料而不是所描述的“正性”光刻胶材料。在这种情况下,光刻胶材料的被照射部分和光刻胶材料的被去除部分将不是上述材料的相同部分。
作为制造技术的变型例的另一示例,制造操作的特定实例可以包括在封装衬底(例如,图2的封装衬底206)上制造同轴互连结构,而不是在IC裸片(例如,IC裸片114)上制造同轴互连结构。尽管在封装衬底上执行制造操作的工具与图1所示和所述的工具不同,但是操作将反映方法400所述的那些操作。
尽管已经以结构特征和/或方法操作特有的语言描述了主题,但是应当理解,在所附权利要求中定义的主题不是必须限于这里所描述的特定特征或操作,包括它们被执行的顺序。

Claims (20)

1.一种半导体部件,包括:
封装衬底,具有由所述封装衬底的独立导电层形成的对应的信号迹线和接地迹线;
集成电路(IC)裸片,具有信号焊盘和接地焊盘;以及
同轴互连结构,所述同轴互连结构将所述IC裸片的所述信号焊盘和所述接地焊盘电耦合至所述封装衬底的对应的所述信号迹线和所述接地迹线,所述同轴互连结构包括
信号芯,绕轴线延伸,所述轴线(i)与包含所述信号焊盘和所述接地焊盘的所述IC裸片的平面正交以及(ii)与包含对应的所述信号迹线和所述接地迹线的所述封装衬底的平面正交;
接地屏蔽,绕所述轴线延伸并被设置为围绕所述信号芯的周界;以及
绝缘体,设置在所述信号芯和所述接地屏蔽之间。
2.根据权利要求1所述的半导体部件,其中所述封装衬底是多层印刷电路板(PCB)。
3.根据权利要求2所述的半导体部件,其中所述多层印刷电路板(PCB)由复合纤维基环氧材料形成,并且包括铜或铝的多层。
4.根据权利要求1所述的半导体部件,其中所述封装衬底是具有硅通孔(TSV)互连的硅中介层。
5.根据权利要求1所述的半导体部件,其中所述集成电路裸片是存储器裸片,所述存储器裸片是动态随机存取存储器(DRAM)裸片或者闪存裸片。
6.根据权利要求1所述的半导体部件,其中所述集成电路裸片是逻辑裸片。
7.根据权利要求1所述的半导体部件,其中所述集成电路裸片是片上系统(SoC)裸片。
8.根据权利要求1所述的半导体部件,其中所述信号芯是铜(Cu)材料。
9.根据权利要求1所述的半导体部件,其中所述信号芯是钛(Ti)或钨(W)材料。
10.根据权利要求1所述的半导体部件,其中所述绝缘体是聚酰亚胺(PI)材料、聚苯并恶唑(PBO)材料或硼磷硅酸盐玻璃(BPSG)材料。
11.根据权利要求1所述的半导体部件,其中所述绝缘体是气相的材料。
12.根据权利要求1所述的半导体部件,其中所述接地屏蔽是铜(Cu)材料。
13.根据权利要求1所述的半导体部件,其中所述接地屏蔽是锡(Sn)材料。
14.一种半导体部件,包括:
封装衬底,具有由所述封装衬底的公共导电层形成的对应的信号迹线和接地迹线;
集成电路(IC)裸片,具有信号焊盘和接地焊盘;以及
同轴互连结构,所述同轴互连结构将所述IC裸片的所述信号焊盘和所述接地焊盘电耦合至所述封装衬底的对应的所述信号迹线和所述接地迹线,所述同轴互连结构包括:
信号芯,绕轴线延伸,所述轴线(i)与包含所述信号焊盘和所述接地焊盘的所述IC裸片的平面正交以及(ii)与包含对应的所述信号迹线和所述接地迹线的所述封装衬底的平面正交;
接地屏蔽,绕所述轴线延伸并被设置为围绕所述信号芯的周界的一部分;以及
绝缘体,设置在所述信号芯与所述接地屏蔽之间。
15.根据权利要求14所述的半导体部件,其中所述封装衬底是单层印刷电路板(PCB),所述单层印刷电路板包括复合纤维基环氧材料,并且所述封装衬底包括铜或铝的单层。
16.根据权利要求14所述的半导体部件,其中所述集成电路裸片是存储器裸片,所述存储器裸片是动态随机存取存储器裸片或者闪存存储器裸片、逻辑裸片或片上系统裸片。
17.一种用于制造同轴互连结构的方法,所述方法包括:
在包括信号焊盘的材料堆叠上沉积第一导电材料;
在所述第一导电材料上沉积光刻胶材料的第一涂层;
经由第一光刻操作,照射和去除所述光刻胶材料的第一涂层的相同部分,以暴露所述第一导电材料的一部分;
在所述第一导电材料的暴露部分上沉积第二导电材料;
去除所述光刻胶材料的第一涂层的剩余部分,以暴露所述第一导电材料的一部分,并且蚀刻所述第一导电材料的暴露部分,以得到信号芯,所述信号芯绕轴线延伸;
在包括所述信号芯的所述材料堆叠上沉积介电材料;
在所述介电材料上沉积光刻胶材料的第二涂层;
经由第二光刻操作,照射和去除所述光刻胶材料的第二涂层的一部分,以暴露所述介电材料的一部分;
去除所述介电材料的暴露部分;
去除所述光刻胶材料的第二涂层的剩余部分,以得到绝缘体,所述绝缘体绕所述轴线延伸;
在包括所述信号芯和所述绝缘体的材料堆叠上沉积第三导电材料;
在所述第三导电材料上沉积光刻胶材料的第三涂层;
经由第三光刻操作,照射和去除所述光刻胶材料的第三涂层的一部分,以暴露所述第三导电材料的一部分;
去除所述第三导电材料的暴露部分;
去除所述光刻胶材料的第三涂层的剩余部分,以得到接地屏蔽,所述接地屏蔽绕所述轴线延伸;以及
抛光所述信号芯、所述绝缘体和所述接地屏蔽,以得到所述同轴互连结构。
18.根据权利要求17所述的方法,其中沉积所述第二导电层包括沉积铜(Cu)材料。
19.根据权利要求17所述的方法,其中沉积所述介电材料包括沉积聚酰亚胺(PI)材料、聚苯并恶唑(PBO)材料或硼磷硅酸盐玻璃(BPSG)材料。
20.根据权利要求17所述的方法,其中沉积所述第三导电材料包括沉积锡(Sn)材料。
CN201811279333.7A 2018-01-29 2018-10-30 用于半导体部件的同轴互连结构 Pending CN110098164A (zh)

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