CN110097907B - SRAM memory - Google Patents
SRAM memory Download PDFInfo
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- CN110097907B CN110097907B CN201810083598.3A CN201810083598A CN110097907B CN 110097907 B CN110097907 B CN 110097907B CN 201810083598 A CN201810083598 A CN 201810083598A CN 110097907 B CN110097907 B CN 110097907B
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- bit line
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention provides an SRAM memory. The SRAM memory includes: the number of the blocks meets an exponential function of 2, the memory cells of each block are single-ended eight-transistor SRAM cells, the number of the read bit lines of each block is the same, all the read bit lines of each block are provided with corresponding control signal lines, and each read bit line is respectively laid adjacently and parallel to the corresponding control signal line in the wiring process so as to enable the corresponding read bit lines and the corresponding control signal lines to be coupled through line capacitance; two adjacent blocks are matched with each other, the two matched blocks share one group of differential amplifiers, the number of the differential amplifiers is the same as that of the read bit lines of each block, a first input end of each differential amplifier is connected to one read bit line of one of the blocks, and a second input end of each differential amplifier is connected to one read bit line of the other block, wherein the position of the read bit line corresponds to that of the read bit line connected with the first input end. The invention can improve the data reading speed of the SRAM.
Description
Technical Field
The invention relates to the technical field of memories, in particular to an SRAM memory.
Background
The memory cells of the SRAM memory include 6-transistor memory cells, 8-transistor memory cells, and the like, wherein the single-ended eight-transistor SRAM cells are shown in fig. 1, and the read-write control is separated and includes a write word line WWL, two write bit lines BL and BLB, a read word line RWL, and a read bit line RBL.
For the SRAM memory using the single-ended eight-transistor SRAM cell as the memory cell, as shown in fig. 2, when the SRAM memory performs a read operation, the single-ended eight-transistor SRAM cell can be read only through one read bit line RBL, i.e., single-ended read. Because no comparison signal is used as a reference, when the single-ended eight-transistor SRAM unit is read to be 0, the RBL needs to be pulled down from VDD to the flip level VDD/2 of the inverter to read data; as more and more SRAM cells are suspended from the read bit lines, the leakage current on the read bit lines increases, which results in slower and slower data read speeds.
Disclosure of Invention
In order to solve the above problems, the present invention provides an SRAM memory, which can eliminate the influence of leakage current and improve the data reading speed of a single-ended eight-transistor SRAM cell.
The invention provides an SRAM memory, comprising: the number of the blocks meets an exponential function of 2, the storage units of each block are single-ended eight-transistor SRAM units, the number of the read bit lines of each block is the same, all the read bit lines of each block are provided with corresponding control signal lines, and the read bit lines are respectively adjacently laid and parallel to the corresponding control signal lines in the wiring process so as to enable the corresponding read bit lines and the corresponding control signal lines to be coupled through line capacitance;
the two adjacent blocks are matched with each other, the two matched blocks share a group of differential amplifiers, the number of the differential amplifiers is the same as the number of the read bit lines of each block, a first input end of each differential amplifier is connected to one read bit line of one of the blocks, a second input end of each differential amplifier is connected to one read bit line of the other block corresponding to the position of the read bit line connected with the first input end, and when the differential amplifiers are used for data reading, when an SRAM unit on one read bit line connected with the differential amplifiers is selected, the data stored by the SRAM unit is output.
Alternatively, both the control signal line and the corresponding read bit line are disposed in a metal layer at the time of wiring.
Optionally, the control signal line is connected to a control signal, and under the action of the control signal, the control signal line triggers the potential of the corresponding read bit line to a voltage value through a line capacitance coupling relationship with the corresponding read bit line during a read operation.
Alternatively, for two blocks matched with each other, the bit line for reading data selected by one block is used as an operating bit line, the read bit line in the other block corresponding to the position of the operating bit line is used as a reference bit line, when the potential of the operating bit line is higher than that of the reference bit line, the differential amplifier outputs a high level, and when the potential of the operating bit line is lower than that of the reference bit line, the differential amplifier outputs a low level.
Optionally, the line capacitance between the corresponding read bit line and control signal line in each of the blocks varies with the size of the memory array in the block.
Compared with the prior art, the SRAM memory provided by the invention has the advantages that the reading mode of the single-end eight-tube SRAM unit is designed into differential reading, so that the influence of leakage current can be eliminated, and the data reading speed of the single-end eight-tube SRAM unit is accelerated.
Drawings
FIG. 1 is a schematic diagram of a single-ended eight-transistor SRAM cell;
FIG. 2 is a schematic structural diagram of a conventional SRAM memory;
FIG. 3 is a schematic structural diagram of an SRAM memory according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the operation of the SRAM memory according to the present invention in a read "0" operation;
FIG. 5 is a timing diagram of the operation of the SRAM memory according to the present invention in the read "1" operation.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides an SRAM memory, which comprises: a plurality of blocks, that is, the SRAM has a Multi-Bank structure, for example, the SRAM may include 2, 4, or 8 blocks, the number of the blocks satisfies an exponential function of 2, the memory cells of each block are single-ended eight-transistor SRAM cells, the number of the read bit lines RBL of each block is the same, the number of the read word lines RWL of each block may be slightly different according to needs, all the read bit lines RBL of each block are provided with corresponding control signal lines, and each read bit line is respectively adjacent to and parallel to its corresponding control signal line during wiring, so that the corresponding read bit line and the control signal line are coupled through line capacitance;
the two adjacent blocks are matched with each other, the two matched blocks share a group of differential amplifiers, the number of the differential amplifiers is the same as the number of the read bit lines RBL of each block, each differential amplifier is provided with two input ends, a first input end of each differential amplifier is connected to one read bit line of one of the blocks, a second input end of each differential amplifier is connected to one read bit line of the other block corresponding to the position of the read bit line connected with the first input end, and the differential amplifiers are used for outputting data stored by the SRAM cells when the SRAM cells on one of the read bit lines connected with the differential amplifiers are selected when the data of the SRAM cells are read.
In general, both the control signal lines and the corresponding read bit lines are arranged in the metal layer when wiring. The control signal line is connected with a control signal, and under the action of the control signal, the control signal line triggers the potential of the corresponding read bit line to a voltage value through the line capacitance coupling relation with the corresponding read bit line during reading operation. Generally, when reading data, for two blocks which are matched with each other, a bit line for reading data selected in one block is used as an operating bit line, a read bit line in the other block corresponding to the position of the operating bit line is used as a reference bit line, when the potential of the operating bit line is higher than that of the reference bit line, the differential amplifier outputs a high level, and when the potential of the operating bit line is lower than that of the reference bit line, the differential amplifier outputs a low level.
It should be noted that, the line capacitance between the control signal line and the corresponding read bit line in each block varies with the size of the memory array in each block, when the memory array is large, the line capacitance also increases, when the memory array is small, the line capacitance also decreases, so that the control signal line can excite the reference bit line to a proper potential through line capacitance coupling, rather than adopting fixed capacitance coupling, no matter how the memory array varies, because the fixed capacitance coupling is adopted, when the memory array is small, the reference bit line can be excited to a very low potential, and when the read "0" operation is performed, the read speed cannot be effectively increased; when the memory array is large, the reference bit line is pulled to a higher potential, which may affect the functional correctness when reading "1".
For clarity, an SRAM memory including two blocks is illustrated. As shown in FIG. 3, the SRAM memory comprises two blocks of BANK0 and BANK1, the memory cells of BANK0 and BANK1 are single-ended eight-pipe SRAM cells, BANK0 and BANK1 have the same structure and respectively comprise N +1 read bit lines and m +1 read word lines, N and m are positive integers, the read bit lines of BANK0 are sequentially marked as RBL0[0] to RBL0[ N ], the read word lines of BANK0 are sequentially marked as RWL0[0] to RWL0[ m ], the read bit lines of BANK1 are sequentially marked as RBL1[0] to RBL1[ N ], the read word lines of BANK1 are sequentially marked as RWL1[0] to RWL1[ m ], all the read bit lines of BANK1 and BANK1 respectively are provided with a corresponding control signal line, the control signal line corresponding to RBBL 1[ TB ] is marked as RBTB [0], the control signal corresponding to RBTB 1[ TB ] and the control signal [ 72, the control signal [ TB ] is marked as RBTB 1[ TB ] and the control signal [ 72, the control signal [ TB 1] corresponding to RBTB 1[ TB [ 72 ] and the like, the control signal [ TB1, the like, the control signal line corresponding to RBL1[1] is designated as BSTB1[1], and so on, the control signal line corresponding to RBL1[ N ] is designated as BSTB1[ N ], each read bit line is respectively laid adjacently and is parallel to the corresponding control signal line in the wiring process, so that the corresponding read bit line and the control signal line are coupled through line capacitance, namely, line capacitance coupling exists between RBL0[0] and BSTB0[0], line capacitance coupling exists between RBL0[ N ] and BSTB0[ N ], line capacitance coupling exists between RBL1[0] and BSTB1[0], and line capacitance coupling exists between RBL1[ N ] and BSTB1[ N ].
BANK0 and BANK1 cooperate with each other, sharing a set of differential amplifiers, if the SRAM comprises four blocks BANK0, BANK1, BANK2 and BANK3, BANK0 and BANK1 cooperate with each other, BANK2 and BANK3 cooperate with each other, since BANK0 and BANK1 each comprise N +1 read bit lines, the SRAM memory further comprises N +1 differential amplifiers, denoted SA [0] SA [ N ], wherein a first input terminal of SA [0] is connected to the read bit line RBL0[0] of BANK0, a second input terminal of SA [0] is connected to the read bit line RBL1[0] of BANK1, a first input terminal of SA [1] is connected to the read bit line RBL0[1] of BANK0, a second input terminal of SA [1] is connected to the read bit line RBL1[1] of BANK1, and so on, a first input terminal of BANK [ N ] is connected to the read bit line RBL0[1] of BANK1, a respective read bit line for reading data [ 8653 ] of BANK1, when the SRAM unit on one of the reading bit lines connected with the differential amplifier is selected, the data stored by the SRAM unit is output.
The operation of the SRAM memory shown in fig. 3 when reading data is discussed in detail below.
When a read operation is performed on one read bit line in one of BANKs BANK0, for example on RBL0[ M ] in BANK0, RBL0[ M ] is the working bit line, fully utilizes the reading bit line corresponding to the position in the block BANK1 in the non-working state, namely RBL1[ M ] in BANK1, using RBL1[ M ] as a reference bit line, because a control signal line BSTB 1M parallel to the RBL 1M is laid at the adjacent position of the RBL, applying a control signal to BSTB1[ M ], exciting RBL1[ M ] to a certain potential VRef through the line capacitance coupling relation between BSTB1[ M ] and RBL1[ M ], connecting two input ends of a differential amplifier SA [ M ] to RBL0[ M ] and RBL1[ M ] respectively, when the difference between the potential on RBL0[ M ] and the potential VRef reaches a certain threshold, the differential amplifier SA [ M ] is turned on, outputting the data to be read. The potential on RBL0[ M ] is lower than VRef, SA [ M ] outputs low level, the potential on RBL0[ M ] is higher than VRef, SA [ M ] outputs high level. Obviously, a way of differentially reading data is used here.
Specifically, RBL0[ M ] is precharged to a high level prior to a read operation.
When a read "0" operation is performed, as shown in fig. 4, RBL0[ M ] indicates its waveform with a solid line, RBL1[ M ] indicates its waveform with a dotted line, BSTB1[ M ] changes from "1" to "0" before RWL0[ M ] is turned on, RBL1[ M ] is excited to a certain potential through line-capacitance coupling, after RWL0[ M ] is turned on, the potential of RBL0[ M ] is pulled down to a certain threshold value smaller than this potential by the SRAM cell, the threshold value is adjusted according to design requirements, for example, the threshold value can be set to 100mV, then the differential amplifier SA [ M ] is turned on by an enable signal SAENI, and finally OUTPUT OUTPUTs a low level.
When a read "1" operation is performed, as shown in fig. 5, RBL0[ M ] indicates its waveform by a solid line and RBL1[ M ] indicates its waveform by a broken line, and similarly, before RWL0[ M ] is turned on, BSTB1[ M ] changes from "1" to "0", RBL1[ M ] is excited to a certain potential by line-capacitance coupling, and after RWL0[ M ] is turned on, RBL0[ M ] does not need to be pulled down because of the read "1", and differential amplifier SA [ M ] is directly turned on by enable signal SAENI, and finally OUTPUT OUTPUTs a high level.
Correspondingly, if reading operation is performed on RBL1[ M ] in BANK1, RBL1[ M ] is an operating bit line, a read bit line corresponding to a position in block BANK0 in a non-operating state, namely RBL0[ M ] in BANK0 is fully utilized, RBL0[ M ] is used as a reference bit line, a control signal line BSTB0[ M ] parallel to the direction of RBL0[ M ] is laid at a position adjacent to the RBL0[ M ], a control signal is applied to BSTB0[ M ], RBL0[ M ] can be excited to a certain potential VRef through a line capacitance coupling relation between BSTB0[ M ] and RBL0[ M ], two input ends of a differential amplifier SA [ M ] are respectively connected into RBL0[ M ] and RBL1[ M ], and when a difference between the potential on RBL1[ M ] and the potential VRef reaches a certain threshold, the differential amplifier [ M ] is turned on, and data is read. The specific operation timing is similar to that of reading RBL0[ M ], and is not described herein again.
Therefore, the SRAM memory provided by the embodiment of the present invention can provide a reference bit line for the working bit line during data reading, the reference bit line and the working bit line for reading data are respectively connected to the two input ends of the differential amplifier, differential reading is performed through the differential amplifier, an influence of leakage current can be eliminated, and the reading speed is faster. Furthermore, the reference bit line used by the invention does not add an extra reference bit line, but fully utilizes the existing reading bit line in a non-working state as the reference bit line, and does not need to add too many peripheral circuits, thereby not needing to increase too much area. Meanwhile, the reference bit line used by the invention is changed along with the change of the working bit line, and the loads borne by the two bit lines are the same, so that the two comparison bit lines are matched quite. Furthermore, the present invention deactivates the reference bit line to a certain potential by controlling the line capacitance coupling between the signal line and the reference bit line, and since the line capacitance varies with the size of the memory array, the reference bit line can be activated to a suitable potential regardless of whether the memory array is large or small, and thus the design using the line capacitance coupling is applicable to any size of memory.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. An SRAM memory, comprising: the number of the blocks meets an exponential function of 2, the storage units of each block are single-ended eight-transistor SRAM units, the number of the read bit lines of each block is the same, all the read bit lines of each block are provided with corresponding control signal lines, each read bit line is respectively and adjacently laid and parallel to the direction of the corresponding control signal line during wiring, so that the corresponding read bit lines and the corresponding control signal lines are coupled through line capacitance, when the control signal lines are connected with control signals, the control signal lines trigger the potential of the corresponding read bit lines to a voltage value through the line capacitance coupling relation between the control signal lines and the corresponding read bit lines under the action of the control signals during reading operation;
the two adjacent blocks are matched with each other, the two matched blocks share a group of differential amplifiers, the number of the differential amplifiers is the same as the number of the read bit lines of each block, a first input end of each differential amplifier is connected to one read bit line of one of the blocks, a second input end of each differential amplifier is connected to one read bit line of the other block corresponding to the position of the read bit line connected with the first input end, and when the differential amplifiers are used for data reading, when an SRAM unit on one read bit line connected with the differential amplifiers is selected, the data stored by the SRAM unit is output.
2. The SRAM memory of claim 1, wherein the control signal lines and corresponding read bit lines are disposed in a metal layer when routing.
3. The SRAM memory according to claim 1, wherein, for two blocks which are matched with each other, a bit line for reading data which is selected in one of the blocks is used as an operating bit line, a read bit line in the other block corresponding to the position of the operating bit line is used as a reference bit line, the differential amplifier outputs a high level when the operating bit line potential is higher than the reference bit line potential, and outputs a low level when the operating bit line potential is lower than the reference bit line potential.
4. The SRAM memory of claim 1, wherein a line capacitance between a corresponding read bit line and a control signal line in each of the blocks varies with a size of a memory array in the block.
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| CN201810083598.3A CN110097907B (en) | 2018-01-29 | 2018-01-29 | SRAM memory |
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| CN201810083598.3A CN110097907B (en) | 2018-01-29 | 2018-01-29 | SRAM memory |
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| CN110097907B true CN110097907B (en) | 2021-03-19 |
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| CN1750171A (en) * | 2004-09-15 | 2006-03-22 | 株式会社瑞萨科技 | Semiconductor integrated circuite device |
| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102637448A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Amplifier sensing |
| US8345469B2 (en) * | 2010-09-16 | 2013-01-01 | Freescale Semiconductor, Inc. | Static random access memory (SRAM) having bit cells accessible by separate read and write paths |
| US8848474B2 (en) * | 2013-01-22 | 2014-09-30 | Lsi Corporation | Capacitive coupled sense amplifier biased at maximum gain point |
| CN106558336A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | For the negative voltage bit line compensation circuit and its method of work of SRAM circuit |
-
2018
- 2018-01-29 CN CN201810083598.3A patent/CN110097907B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750171A (en) * | 2004-09-15 | 2006-03-22 | 株式会社瑞萨科技 | Semiconductor integrated circuite device |
| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| US8345469B2 (en) * | 2010-09-16 | 2013-01-01 | Freescale Semiconductor, Inc. | Static random access memory (SRAM) having bit cells accessible by separate read and write paths |
| CN102637448A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Amplifier sensing |
| US8848474B2 (en) * | 2013-01-22 | 2014-09-30 | Lsi Corporation | Capacitive coupled sense amplifier biased at maximum gain point |
| CN106558336A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | For the negative voltage bit line compensation circuit and its method of work of SRAM circuit |
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