JPH07230690A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a semiconductor memory which can reduce power consumption at the time of reading out data and read out data at high speed. CONSTITUTION:Drive amplifiers 2a, 2b drive second conducting lines 3a and 3b in accordance with selecting memory cell data transmitted to first conducting lines 1a, 1b at the time of operation. This drive amplifier 2a and 2b are provided with a amplitude limiting function, and prevent potentials of the second conducting lines 3a, 3b from being fully swing. Since potential amplitude of the second conducting lines 3a, 3b is suppressed, charge/discharge current is reduced, while a signal potential is decided at high speed, and data can be read out at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a hierarchical bit line structure. More specifically, it relates to a configuration for speeding up data reading and / or reducing current consumption during data reading.

[0002]

FIG. 35 shows, for example, Japanese Patent Publication No. 3-2199.
FIG. 7 is a diagram showing a configuration of a main part of a conventional semiconductor memory device shown in Japanese Patent Laid-Open No. 6-76. FIG. 35 schematically shows a structure of a portion related to memory cells arranged in two columns and related to data reading.

In FIG. 35, main bit line pairs MBL0, ZMBL0 and MBL1, ZMBL1 are arranged corresponding to each column of memory cells MC. Memory cell MC is divided into four groups MG0, MG1, MG2, and MG3 along the column direction (extending direction of the main bit line). In each column of memory cells, a sub bit line pair is arranged corresponding to each memory cell group. For the main bit line pair MBL0 and ZMBL0, the sub bit line pair SBL00, ZSBL00, SBL01, ZSB
L01, SBL02, ZSBL02, and SBL0
3 and ZSBL03 are arranged.

Main bit line pair MBL1 and ZMBL
Similarly, for 1, the sub bit line pair SBL10, ZSB
L10, SBL11, ZSBL11, SBL12, ZS
BL12, SBL13, and ZSBL13 are arranged.

Word line WL is arranged in a direction intersecting with sub-bit line pair SBL and ZSBL (sub-bit lines are generically shown). Memory cell group MG0, MG
Although a plurality of word lines WL are arranged in each of 1, MG2, and MG3, in FIG. 35, only one word line WL is representatively shown in each of memory cell groups MG0 to MG3. Memory cells MC are arranged corresponding to the intersections of sub bit lines SBL and ZSBL and word lines WL. FIG. 35 shows, as an example, a configuration in which memory cell MC is arranged corresponding to the intersection of sub bit line SBL and word line WL. The memory cell MC is not arranged at the intersection of the word line WL and the sub bit line ZSBL. These sub bit lines SBL and Z
SBL constitutes a so-called "folded bit line", and signals having logically complementary to each other are transmitted on sub bit lines SBL and ZSBL.

For sub-bit lines SBL and ZSBL, a sense amplifier SA for differentially amplifying a signal potential on the sub-bit line pair SBL and ZSBL is provided. Here, sense amplifier SA generically indicates sense amplifiers SA00 to SA03 and SA10 to SA13 provided for each sub-bit line pair.

Main bit line MBL (main bit line M
A block selection signal BS (generically indicates block selection signals BS0 to BS3) is provided between the main bit line ZMBL (generally indicates ZMBL0 and ZMBL1) and a main bit line ZMBL (generally indicates BL0 and MBL1). A block select gate BG is provided which connects the corresponding sub bit lines SBL and ZSBL to the main bit lines MBL and ZMBL. The block selection gate BG includes a sub bit line pair SBL00, ZSBL00 to SBL03,
ZSBL03 and SBL10, ZSBL10-SBL
13, block selection gates BG00 to BG03 and BG10 to B provided corresponding to ZSBL13, respectively.
G13 is generically shown.

For the main bit lines MBL and ZMBL, the sense amplifier S via the block select gate BG.
The signal differentially amplified by A is transmitted. Therefore, main bit lines MBL and ZMBL transmit signals whose logics are complementary to each other.

Sense amplifiers SA # 0 and SA # 1 are further provided for main bit lines MBL0, ZMBL0 and MBL1, ZMBL1, respectively. Sense amplifiers SA # 0 and SA # 1 differentially amplify the signal potentials on the corresponding main bit lines MBL0, ZMBL0 and MBL1, ZMBL1.

Main bit lines MBL0, ZMBL0 and MBL1, ZMBL1 are rendered conductive in response to column select signals YS0 and YS1, respectively, and corresponding main bit lines MBL0, ZMBL0 and MBL1 and ZMBL1 are selectively subjected to internal data. IO gates IG0 and IG1 for connecting to transmission bus IO are provided. Column selection signals YS0 and YS1 are generated by a column decoder (not shown).

The internal data transmission bus IO is a preamplifier PA.
Connected to. Preamplifier PA amplifies the signal on internal data transmission bus IO during operation to generate internal read data and applies it to output circuit OB. Output circuit OB buffers the internal read data supplied from preamplifier PA during operation and outputs read data Dout to the outside.

The memory cell MC includes a memory cell capacitor MCb for storing information and a memory cell transistor for transmitting the information stored in the memory cell capacitor MCb to the corresponding sub bit line SBL (or ZSBL) at the time of selection. Including MCa. Next, the operation will be briefly described.

In operation, one word line WL is selected. Only the memory cell group including the selected word line is activated, and the remaining memory cell groups maintain the precharged state (standby state). Now, the word line W belonging to the memory cell group MG0
Suppose L is selected. Memory cell group MG0
At, when the potential of the word line WL rises to "H",
The information stored in the memory cell MC is transmitted to the sub bit line SBL. On the other hand, sub-bit lines ZSBL00 and ZS
Information stored in the memory cell MC is not transmitted to BL10,
The precharge state is maintained.

When a sufficient signal potential difference is generated in each of sub-bit lines SBL00, ZSBL00 and SBL10, ZSBL10, sense amplifiers SA00 and SA10 included in memory cell group MG0 are activated and corresponding sub-bit line pairs SBL00, ZSBL00 and SBL10, The signal potential on ZSBL10 is differentially amplified. In the memory cell groups MG1 to MG3, the sense amplifier is not activated. Sense amplifier SA
00 and SA10, sub-bit line pair SB
L00, ZSBL00 and SBL10, ZSBL10
After the upper signal potential is amplified, the block selection signal BS0
Is activated, block select gates BG00 and BG10 are rendered conductive, and sub-bit line pair SBL0
0, ZSBL00 and SBL10, ZSBL10 to the main bit line pair MBL0, ZMBL0 and MBL1,
Connect to ZMBL1. As a result, the main bit line M
The signal potential on BL0, ZMBL0 and MBL1, ZMBL1 changes to the potential level corresponding to the signal potential differentially amplified by the sense amplifiers SA00 and SA10. The lengths of main bit lines MBL and ZMBL are longer than the lengths of sub bit lines SBL and ZSBL, and the signal potential difference between main bit lines MBL and ZMBL is sub bit lines SBL00, ZSBL00 and SBL1.
0, which is smaller than the signal potential difference of ZSBL10.

Next, sense amplifiers SA # 0 and SA #
1 is activated and the main bit lines MBL0, ZMB
The signal potentials on L0 and MBL1, ZMBL1 are amplified and driven to a high level or a low level according to the stored information of the selected memory cell MC. After that, the column selection signal YS0 or YS1 is activated,
The data amplified by sense amplifier SA # 0 or SA # 1 is transmitted onto internal read data bus IO. Then, preamplifier PA is activated, amplifies the signal potential on internal read data bus IO, transmits internal read data, and output circuit OB generates and outputs read data Dout from this internal read data.

[0016]

FIG. 36 shows a schematic operation waveform of the semiconductor memory device shown in FIG. In FIG. 36, signal waveforms during a data read operation when sub bit lines SBL and ZSBL and main bit lines MBL and ZMBL are precharged to an intermediate potential of Vcc / 2 (Vcc is an operating power supply potential) are shown as an example. Be done.

As shown in FIG. 36, the potential of the word line WL selected at time t1 rises to "H", and the precharge potentials of the sub-bit lines SBL and ZSBL are stored in the memory cells connected to the selected word line WL. It changes according to the information (in FIG. 36, the case where the storage information of the selected memory cell is “H” is shown). When the potential difference between the sub-bit lines SBL and ZSBL is sufficiently expanded, the sense amplifier SA provided in the sub-bit lines SBL and ZSBL is activated, the potential difference between the sub-bit lines SBL and ZSBL is expanded, and one of the sub-bit lines (SBL) Rises to the power supply potential Vcc level, and the other sub-bit line (ZS
BL) drops to the ground potential level.

At time t1, the block selection signal BS
Are activated (raised to "H"), and the sub-bit lines SBL and ZSBL are turned on to the main bit lines MBL and Z.
Connected to MBL. As a result, the main bit line MB
The potentials of L and ZMBL change from the precharge potential, then sense amplifier SA # is activated, the potentials of main bit lines MBL and ZMBL are amplified, and the potential of one main bit line is at the power supply potential Vcc level and the other. The main bit line of is discharged to the ground potential level.

After the potentials on main bit lines MBL and ZMBL are amplified, column select signal YS is activated (raised to "H"), and main bit lines MBL and ZMBL are connected to internal read data bus IO. Thereafter, output data Dout is output at time t3 via preamplifier PA and output circuit OB shown in FIG.

As described above, from the time t0 when the potential of the word line WL rises to "H" to the time t2 when the column selection signal YS is activated, the sub-bit lines SBL and ZSBL.
Amplifier SA and main bit line M provided in
It is necessary to activate the sense amplifier SA # provided in BL and ZMBL. The time t1 at which the block selection signal BS is activated can be the same as the time t0 at which the potential of the word line WL rises. However, in this case, the sense amplifier S provided on the sub bit lines SBL and ZSBL
It is necessary to drive both the sub bit lines SBL and ZSBL and the main bit lines MBL and ZMBL by A, and it is necessary to make the driving power of the sense amplifier SA provided on the sub bit lines SBL and ZSBL relatively large, so that the occupied area is large. Become.

Sense amplifiers SA provided on the sub bit lines SBL and ZSBL and main bit lines MBL and ZMBL
It is possible that the sense amplifier SA # provided in the sub-bit line SBL is activated at the same time. And the main bit line MBL is charged to the "H" level, while the sense amplifier SA # discharges the sub bit line SBL and the main bit line MBL to the "L" level.
In some cases, sense amplifiers SA and SA # perform amplification operations in opposite directions, which causes a problem that accurate data reading cannot be performed. Therefore, the sense amplifier SA provided on the sub bit lines SBL and ZSBL amplifies the potential difference between the sub bit lines SBL and ZSBL, and activates the sense amplifier SA # after the potential difference between the main bit lines MBL and ZMBL becomes a sufficiently large value. Therefore, the potential of the word line WL is "H".
Main bit lines MBL and ZMBL after rising to
It takes a long time until the potential of is sufficiently amplified, which causes a problem that data cannot be read at high speed.

Further, main bit lines MBL and ZM
BL is driven to the power supply potential Vcc level and the ground potential level by sense amplifier SA #. Therefore, the current consumption due to charging / discharging of main bit lines MBL and ZMBL is increased, and the current consumption during the sensing operation is reduced. There is a problem that you can not do.

Further, main bit lines MBL and ZM
After the potential of BL is set to the power supply potential Vcc level and the ground potential level, the column selection signal YS is activated (“H”).
Therefore, after the sense amplifier SA # is activated,
The column selection signal YS cannot be activated until the potentials of the main bit lines MBL and ZMBL reach a stable state.
There is a problem that the timing of the time t2 at which the column selection signal YS is activated cannot be advanced and the access time at the time of data reading becomes long.

In the structure of the hierarchical bit line having the sub bit line and the main bit line as described above, the sub bit line and the main bit line are set to a predetermined potential (intermediate potential Vcc / 2 or power supply potential Vcc level) during standby.
A transistor element for precharging is required. In this case, it is preferable to dispose precharge / equalize transistor elements in the memory cell array without increasing the occupied area of the memory cell array as much as possible. However, the above-mentioned prior art documents do not disclose how to arrange such a transistor element for precharge / equalize.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of reducing the current consumption during the sensing operation.

Another object of the present invention is to provide a semiconductor memory device capable of reading data at high speed.

Still another object of the present invention is to provide a semiconductor memory device capable of reducing current consumption during a sensing operation and reading data at high speed.

Still another object of the present invention is to provide a semiconductor memory device including sub bit line precharge / equalize transistors arranged efficiently.

Still another object of the present invention is to provide a semiconductor memory device in which the occupied area of the memory cell array, the current consumption and the access time during data reading are reduced.

Still another object of the present invention is to provide a dynamic semiconductor memory device which can achieve the above objects.

[0031]

A semiconductor memory device according to a first aspect of the present invention includes a plurality of memory cells each storing information.
A plurality of memory cells are connected to each other, a first conductive line for transmitting data of a selected memory cell among the plurality of memory cells, and a second conductive line provided in parallel with the first conductive line. Line and drive amplifier means for driving the second conductive line to a potential level corresponding to the signal potential on the first conductive line according to the signal potential on the first conductive line.
The drive amplifier means includes means for suppressing the signal potential amplitude on the second conductive line.

The semiconductor memory device according to claim 1 further includes
A data read line for transmitting a data signal corresponding to a signal potential on the second conductive line, and a gate means for connecting the second conductive line and the data read line in response to a selection signal.

According to another aspect of the semiconductor memory device of the present invention, the first conductive line includes a pair of sub-bit lines transmitting complementary logic signals, and the second conductive line transmitting complementary logic signals. And a pair of main bit lines.

In the drive amplifier means in the semiconductor memory device of the present invention, the control gate is connected to one sub-bit line of the sub-bit line pair, and one conduction terminal thereof is connected to the other sub-bit line of the sub-bit line pair, and A first conductivity type first transistor element whose other conduction terminal is connected to receive a sense drive signal, one conduction terminal of which is connected to the one sub-bit line, and a control gate of which is connected to the other sub-bit line A second transistor element of the first conductivity type, the other conductive terminal of which is connected to receive the sense drive signal, and each of the first and second transistor elements in response to the isolation instruction signal. While connecting the control gate to the first and second sub-bit lines, the first and second sub-bit lines are connected. A separating element for separating one conductive terminal of each of the transistor elements from the other and one sub bit line, and one conductive terminal of each of the first and second transistor elements in response to the connection instruction signal. Connection means for connecting to one and the other main bit line are included.

A semiconductor memory device according to a third aspect further includes a second conductivity type transistor element pair in which one conduction terminal and a control gate are cross-coupled and connected to a main bit line pair. The signal potential of the main bit line is differentially amplified.

According to a fourth aspect of the semiconductor memory device of the present invention, in the drive amplifier means of the second aspect, one of the conduction terminals and the control gate are cross-coupled and connected to the sub-bit line pair, and the drive amplifier means is provided on the sub-bit line pair. A pair of second conductivity type transistor elements for differentially amplifying the signal potential are included.

According to another aspect of the semiconductor memory device of the present invention, the signal on the second conductive line is amplified without affecting the signal potential on the second conductive line and transmitted to the data read line via the gate means. Means are further included.

A semiconductor memory device according to a sixth aspect includes a buffer amplifier having a high input impedance for amplifying the potential of the second conductive line.

A semiconductor memory device according to a seventh aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the first conductive lines have a first sub-bit line pair for transmitting signals of complementary logics and a logic of the first sub-bit line pair. A second sub-bit line pair for transmitting complementary signals is included, and the first and second sub-bit line pairs are arranged so as to extend in opposite directions with respect to the drive amplifier means.

According to a seventh aspect of the present invention, in the drive amplifier means of the semiconductor memory device, one conduction terminal and the control gate are cross-coupled to each other and connected to the first sub-bit line pair, and in response to the first sense drive signal. A pair of first first differentially amplifying signal potentials on the first sub-bit line pair
First sense means including a conductive type transistor element;
In response to the isolation instruction signal, a first transistor for pairing the control gate of the first transistor element pair and the first sub-bit line pair with each other for isolating the respective one conduction terminal and the first sub-bit line pair. 1 separation means, one of the conduction terminals and the control gate are cross-coupled and connected to the second sub-bit line pair, and the signal potential on the second sub-bit line pair is supplied in response to the second sense drive signal. Second sense means including a pair of transistor elements of a second conductivity type for complementary amplification; and a control gate and a second gate of each of the second pair of transistor elements in response to the isolation indicating signal. A second isolation means for isolating the second one of the second conduction element and the one conduction terminal of the second transistor element pair while connecting the sub-bit line pair. The signal potential on one conduction terminal of each of the first and second transistor element pairs is transmitted to the main bit line pair via the connection means.

A semiconductor memory device according to an eighth aspect is the semiconductor memory device according to the first aspect, wherein the first conductive line is divided into first and second portions with respect to the drive amplifier means, and further responds to the block selection signal. Means for disconnecting one of the first and second portions from the drive amplifier means.

According to a ninth aspect of the semiconductor memory device of the present invention, the drive amplifier means according to the first aspect includes a sense means for amplifying a signal potential on the first conductive line in response to a sense drive signal, and a read activation signal. Is activated in response to
Included is read gate means for driving the second conductive line to the first power supply potential level in response to a signal on the first conductive line.

A semiconductor memory device according to a tenth aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the first conductive line includes a pair of sub-bit lines transmitting signals of complementary logics, and the second conductive bit line includes a second pair of sub-bit lines. The conductive line includes a pair of main bit lines transmitting signals of complementary logics to each other, and the drive amplifier means further has a first conductive terminal and a control gate cross-coupled to each other and connected to the sub-bit line pair. Pair of first transistor elements of the first conductivity type for differentially amplifying the signal potential on the pair of sub-bit lines in response to the sense drive signal of the first bit line, and one conduction terminal and the control gate of each cross. A pair of coupled and connected to the sub-bit line pair for differentially amplifying the signal potential on the sub-bit line pair in response to the second sense drive signal. The second conductivity type second transistor element is provided between one sub bit line and one main bit line, and between the other sub bit line and the other main bit line, and responds to the read activation signal. And a pair of read gates for transmitting the first potential onto the corresponding main bit line in response to the signal potential on the sub bit line.

According to an eleventh aspect of the semiconductor memory device of the ninth aspect, in the semiconductor memory device of the ninth aspect, the read activation signal is activated earlier than when the first and second sense drive signals are activated.

A semiconductor memory device according to a twelfth aspect of the present invention is the semiconductor memory device according to the first aspect, further including an initialization transistor for precharging the first conductive line to a predetermined potential during standby. Has a control gate formed of the same conductive layer as the transistor included in the memory cell and has the same size as the transistor of this memory cell.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells each storing information, and a pair of sub-bit lines connected to the plurality of memory cells and transmitting complementary logic signals, A pair of main bit lines that are arranged in parallel with the sub bit line pair and transmit signals of complementary logics, and one conductive terminal and a control gate of each pair are cross-coupled and connected to the sub bit line pair. A pair of first conductivity type first transistor elements for differentially amplifying the signal potential on the pair, one conduction terminal of each pair and a control gate are cross-coupled and connected to a sub-bit line pair, Between a pair of second conductivity type transistor elements that differentially amplify the signal potential on the sub-bit line pair, and between one sub-bit line and one main bit line And a pair of read gate means provided between the other sub bit line and the other main bit line, activated in response to the read activation signal, and transmitting the potential on the corresponding sub bit line to the corresponding main bit line. including.

A semiconductor memory device according to a fourteenth aspect of the invention includes a plurality of memory cells each storing information, and a pair of sub-bit lines connected to the plurality of memory cells and transmitting signals having complementary logics. . The pair of sub-bit lines includes a first portion, a second portion, and a pair of signal lines connecting the first and second portions. The sub bit line pair includes a first sub bit line and a second sub bit line.

According to a fourteenth aspect of the semiconductor memory device, one conduction terminal thereof is further connected to one signal line of the signal line pair, the control gate thereof is connected to the second sub bit line of the first portion, and the other. A first transistor element of a first conductivity type whose one conduction terminal is connected to receive the first sense drive signal, and one conduction terminal of which is connected to the other signal line of the signal line pair and whose control gate is A second transistor element of the first conductivity type, which is connected to the first sub-bit line of the portion 1 and the other conduction terminal of which is connected to receive the first sense drive signal, and one conduction terminal of which is one signal Line, the control gate of which is connected to the second sub-bit line of the second portion, and the other conductive terminal of which is connected to receive the second sense drive signal. A third transistor element of the second conductivity type, one conduction terminal of which is connected to the other signal line, its control gate is connected to the first sub-bit line of the second portion, and the other conduction terminal is the second A fourth transistor element of the second conductivity type connected to receive the sense drive signal of the second conductive line, and the signal line pair and the first and second sub-bit lines of the first portion in response to the isolation instruction signal. A pair of first isolation transistors for isolation, and a pair of second isolation transistors for isolating the first and second sub-bit lines of the second portion and the signal line pair in response to the isolation instruction signal. An isolation transistor and a pair of transfer transistor elements for connecting the signal line pair and the main bit line pair for a predetermined period when the isolation instruction signal is activated are included.

According to a fifteenth aspect of the present invention, in the semiconductor memory device, a pair of bit lines transmitting signals whose logics are complementary to each other, a plurality of word lines arranged so as to intersect with the sub-bit line pair, and the plurality of word lines. For coupling each of the sub-bit lines to an associated sub-bit line in response to a signal potential on a corresponding word line and a capacitor for storing information. A plurality of memory cells each having an access transistor, and an initialization transistor having the same layout pattern as that of the access transistor and setting the sub-bit line pair to a predetermined potential level at initialization.

[0050]

According to the semiconductor memory device of the present invention, since the drive amplifier means suppresses the potential amplitude of the second conductive line, the charge / discharge current of the second conductive line is reduced and the second conductive line is reduced.
The timing of determining the potential of the conductive line is accelerated, and data can be read at high speed.

According to another aspect of the semiconductor memory device of the present invention, the transistor element pair in which one conduction terminal and the control gate, which are components of the drive amplifier means, are cross-coupled, each control gate is connected to the sub-bit line pair. Since one of the conduction terminals is separated from the sub bit line pair by the separation transistor, the main bit line pair can be driven according to this memory cell data when the memory cell data appears on the sub bit line pair, and the main bit can be driven at a fast timing. A bit line pair can be driven and data can be read at high speed.

According to another aspect of the semiconductor memory device of the present invention, since the amplifying means is constituted by the cross-coupled transistor element pair, the potential of the main bit line pair changed only in one potential direction is driven in the opposite direction. Therefore, when the memory cell is a dynamic memory cell, the memory cell data can be surely restored.

According to another aspect of the semiconductor memory device of the present invention, the drive amplifier means has additional amplifying means, and the additional amplifying means prevents the potential of the sub-bit line pair from affecting the potential of the main bit line pair. Differential amplification can be performed, and memory cell data can be restored while reducing current consumption.

According to another aspect of the semiconductor memory device of the present invention, the amplifying means amplifies the potential of the second conductive line without affecting the potential of the second conductive line, thereby charging and discharging the second conductive line. Since the potential of the second conductive line is amplified without performing the operation, the current consumption can be reduced and the small amplitude signal on the second conductive line is amplified, so that the data can be read at a fast timing. it can. In the semiconductor memory device according to claim 6, since the amplifying means is composed of a buffer amplifier having a high input impedance, a small amplitude signal on the second conductive line can be transmitted at high speed without changing the potential on the second conductive line. Amplification is possible, and low current consumption and high-speed data reading are possible.

According to another aspect of the semiconductor memory device of the present invention, the memory cell is in the selected state in either the first or second portion of the sub-bit line pair by the first and second selecting means and the first and second separating means. Even if the main bit line pair is controlled, the main bit line pair can be driven at high speed according to the memory cell data while suppressing the potential amplitude (potential change amount) of the main bit line pair, and the memory cell data can be driven without amplifying the main bit line potential. It is possible to restore, and it is possible to reduce the current consumption at the time of restoration.

According to another aspect of the semiconductor memory device of the present invention, since only the first conductive line of one portion is connected to the drive amplifier means by the block selection gate, the drive amplifier means is connected to the drive amplifier means of the connected one portion. It suffices to operate according to the potential of only one conductive line, and it is not necessary to operate after the memory cell data is transmitted to the entire first conductive line.
The main bit line can be driven at a fast timing, and data can be read at a high speed. Further, when the first conductive line includes a sub bit line pair, only one sub bit line pair is driven by this drive amplifier means when the memory cell data is restored, so the load capacitance of the drive amplifier means at the time of restore is reduced. It

According to another aspect of the semiconductor memory device of the present invention, the read gate means has a second potential in accordance with a signal potential on the first conductive line.
To drive the conductive line of the first level to the first power supply potential level.
The potential of the second conductive line can be changed before the potential of the conductive line is sufficiently amplified by the sensing means, and data can be read at high speed.

According to another aspect of the semiconductor memory device of the present invention,
The signal potential on the sub-bit line pair is differentially amplified by the first pair of cross-coupled first transistor elements of the second conductivity type and the second pair of cross-coupled second transistor elements of the second conductivity type. The memory cell data can be operated reliably, and the potential of the main bit line pair can be changed accurately and at high speed.

According to another aspect of the semiconductor memory device of the present invention,
Since the read gate means is activated before the activation signal of the sense means is activated, a potential change can be generated in the main bit line pair when the memory cell data appears in the sub bit line pair, and the data can be transferred at high speed. Can be read.

According to another aspect of the semiconductor memory device of the present invention, the initialization transistor has a control gate formed in the same layer as the memory cell transistor and the same size as the memory cell transistor. The initialization transistor can be formed by repeating the memory cell layout pattern by manufacturing the memory cell transistor with the same layout pattern as the memory cell transistor, and the periodicity of the layout pattern in the memory cell array is maintained. As a result, the array area can be reduced, the stability of the pattern of the memory cell transistor is maintained, and the storage characteristics of the memory cell and the reliability of the device are improved.

According to another aspect of the semiconductor memory device of the present invention,
The potential of the sub bit line pair is differentially amplified by the first and second cross-coupled transistor element pairs, and the read gate means sets the main bit line pair to the first power supply potential level according to the potential of the sub bit line pair. Therefore, the potential of the main bit line pair can be changed at high speed, and the potential amplitude of the main bit line pair can be effectively suppressed by the inherent impedance of the read gate means.

According to another aspect of the semiconductor memory device of the present invention,
The first and second isolation transistor pairs separate one of the conduction terminals of the first, second, third, and fourth transistor elements from the sub-bit line pair, and differentially amplify the potential of the sub-bit line pair to perform main amplification. Since the bit line pair is driven for a predetermined period, it is possible to change the potential of the main bit line pair when the memory cell data appears on the sub bit line pair and effectively suppress the potential amplitude of the main bit line pair. Therefore, low current consumption and high speed data reading can be realized.

According to another aspect of the semiconductor memory device of the present invention, it has the same layout pattern as the memory cell transistor of the initialization transistor, the periodicity of the pattern in the memory cell array is maintained, and the initialization transistor is efficiently used as the memory cell array. Can be placed inside.

[0064]

【Example】

[Basic Structure of the Invention] FIG. 1 is a diagram showing a basic structure of a main portion of a semiconductor memory device of the present invention. In FIG.
Only the configuration of the part related to data reading is shown. In FIG. 1, the semiconductor memory device includes a plurality of memory cells MC arranged in a matrix of rows and columns. FIG. 1 representatively shows memory cells MC arranged in 2 rows and 2 columns.

First conductive lines 1a and 1b are arranged corresponding to each column of memory cells MC. Word lines WL (WL0, WL1) are arranged corresponding to each row of memory cells MC. The memory cells MC arranged in one column are connected to the first conductive lines 1a and 1b, respectively. During operation, one word line WL (WL0 or WL0
1) is brought into the selected state, and the data of one row of memory cells MC connected to the selected word line appears on the corresponding first conductive lines 1a and 1b.

The semiconductor memory device further includes a first conductive line 1
It includes second conductive lines 3a and 3b arranged in parallel with a and 1b. First conductive line 1a and second conductive line 3
a is composed of different wiring layers. First conductive wire 1
a, 1b and the second conductive lines 3a and 3b have a multilayer wiring structure, and the first and second conductive lines 1a, 1b
Relax the pitch conditions of b, 3a and 3b.

For each of first conductive lines 1a and 1b, drive amplifiers 2a and 2b are provided for driving second conductive lines 3a and 3b in accordance with the signal potential on corresponding first conductive lines 1a and 1b. . Drive amplifiers 2a and 2b each have an amplitude limiting function, and suppress the full-swing (change between operating power supply potential Vcc and ground potential level) in potential amplitude of corresponding second conductive lines 3a and 3b. It has a function.

Amplifiers 4a and 4b for amplifying the signal potentials on the corresponding second conductive lines 3a and 3b are provided for the second conductive lines 3a and 3b, respectively. Column selection signals YS0 and YS1 are supplied to the amplifiers 4a and 4b.
IO gates IG0 and I for transmitting the output signals of amplifiers 4S and 4b to read data line 5 in response to.
G1 is provided. The data read by the read data line 5 is amplified by the preamplifier PA and output from the output circuit O.
Given to B. Output circuit OB buffers the internal read data supplied from preamplifier PA to generate and output external read data Dout. Next, the operation of the configuration shown in FIG. 1 will be described with reference to the operation waveform diagram of FIG.

In FIG. 2, the selected memory cell M
A data read operation when C stores "H" data is shown as an example. In addition, the first conductive wire 1 (1a,
1b) and the second conductive line 3 (3a, 3b) are precharged to an intermediate potential VBL between the power supply potential Vcc and the ground potential GND during standby, and the read data line 5 is connected to the power supply potential Vcc. It is precharged to the level.

First, one word line WL is selected according to an externally applied address signal (not shown), and the potential of this selected word line WL rises to "H". Memory cell MC connected to this selected word line WL
Data appears on the corresponding first conductive line 1 and the potential of the first conductive line 1 is the precharged intermediate potential VBL.
To the data stored in the memory cell MC. In FIG. 2, the first conductive line 1 is shown in a case where the potential of the first conductive line 1 rises according to the storage data of the selected memory cell MC.

Then, drive amplifier 2 (2a, 2b) is activated to generate the second signal in accordance with the signal potential on first conductive line 1.
Drive the conductive wire 3. As a result, the second conductive wire 3
Rises from the intermediate potential VBL in the precharged state. The drive amplifier 2 has an amplitude suppressing function, and the potential amplitude of the second conductive line 3 is small (potential change amount is small). Then, the amplifier 4 (4a, 4b) is activated to amplify a relatively small potential change appearing on the second conductive line 3. The potential amplified by amplifier 4 is transmitted to one conduction terminal of IO gates IG0 and IG1. The drive amplifier 2 includes a second conductive wire 3 (3
In parallel with the driving of a, 3b), the potentials on the first conductive lines 1a and 1b are amplified. As a result, the first conductive wire 1
Potential rises to the power supply potential Vcc level. The amplifying operation of the first conductive line 1 by the drive amplifier 2 is to drive the drive amplifier 2 also at the time of data writing. This is because they are the same.
When the memory cell MC needs to restore the read memory cell data like a dynamic memory cell described later, by amplifying the signal potential on the first conductive line 1 by the drive amplifier 2. , Memory cell data is restored.

After the amplification operation by the amplifier 4 is completed, the column selection signal YS (YS0 or YS1) rises to "H" and the IO gate IG (IG0 or IG1) becomes conductive,
The data amplified by the amplifier 4 is transmitted onto the read data line 5. When the potential of the read data line 5 is confirmed,
Output data Dout is output by the preamplifier PA and the output circuit OB. Here, in FIG. 2, the potential of the read data line 5 is shown to drop slightly during data reading because it is affected by the loss of the threshold voltage of the IO gate in the conductive state. This is because.

With the above structure, the second
Since the potential amplitude of the conductive line 3 is reduced, it is not necessary to charge or discharge the second conductive line 3 to the operating power supply potential Vcc or the ground potential GND, and the current consumption during data reading can be reduced. . Further, since the drive amplifier 2 drives the second conductive line 3 in accordance with the transmitted memory cell data when the data of the selected memory cell MC appears on the first conductive line 1, it is fast. The second conductive line 3 can be driven at a timing. In addition, since the potential amplitude of the second conductive line 3 is small, the potential of the second conductive line 3 can be brought into a definite state at high speed. Therefore, the amplifier 4 is activated at a fast timing,
Since the column select signal YS can be activated at a fast timing according to the column select signal YS, data reading can be performed at high speed.

Further, if a block select gate which conducts in response to a block select signal is provided between the drive amplifier 2 and the second conductive line 3, the memory cell MC can be divided into a plurality of memory cell blocks. Even in the case of a semiconductor memory device having a large storage capacity, since the memory cell is not directly connected to the second conductive line, the parasitic capacitance of the second conductive line 3 can be reduced and data can be read at high speed. It is possible to realize a semiconductor memory device having a large storage capacity. Next, a specific configuration of the semiconductor memory device of the present invention will be described.

In the following description, a dynamic semiconductor memory device (dynamic random access memory (DRAM)) in which memory cell MC is composed of one transistor and one capacitor is shown as an example. However, the semiconductor memory device may be another type of semiconductor memory device.

[First Embodiment] FIG. 3 is a diagram showing a structure of a main portion of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 3, only the configuration of a portion related to one column of memory cells is shown. In FIG. 3, the first conductive lines are sub-bit lines SBLa, ZSBLa, SBLb, and Z.
It is composed of SBLb. Sub-bit lines SBLa and ZSBLa are arranged in pairs, and sub-bit line SB
Lb and ZSBLb are arranged in pairs. Sub-bit lines SBLa and ZSBLa and sub-bit line SBL
b and ZSBLb are arranged so as to extend in opposite directions with respect to drive amplifier 2. Word line WLA
The memory cell MC is arranged at the intersection of the sub-bit line SBLb and the word line WLB and the sub-bit line SBL.
A memory cell MC is arranged corresponding to the intersection of a. The memory cell MC has a memory capacitor Mb for storing data and a corresponding sub bit line SBL (SBLa or SBLb) in response to a signal potential on the corresponding word line WL (WLA or WLB).
Access transistor Ma coupled to Signals whose logics are complementary to each other are transmitted on sub-bit lines SBLa and ZSBLa. Similarly, the sub bit line SBLb
Signals whose logics are complementary to each other are transmitted on and ZSBLb.

Drive amplifier 2 has one conduction terminal connected to node Na, its control gate connected to sub-bit line ZSBLa, and the other conduction terminal receiving the sense drive signal on sense amplifier drive signal line 15a. An n-channel MOS (insulated gate field effect) transistor 10a to be connected, one conduction terminal thereof is connected to node Nb, its control gate is connected to sub-bit line SBLa, and the other conduction terminal thereof is a sense line on signal line 15a. It includes an n channel MOS transistor 11a connected to receive a drive signal, and isolation transistors 12a and 13a for isolating nodes Na and Nb from sub bit lines SBLa and ZSBLa, respectively, in response to isolation instruction signal BLI. Transistors 10a and 11a form a cross-coupled flip-flop when isolation transistors 12a and 13a are conductive (when the sense drive signal on signal line 15a is active).

Drive amplifier 2 further has one conductive terminal connected to node Na, its control gate connected to sub-bit line ZSBLb, and the other conductive terminal connected to receive a sense drive signal on signal line 15b. N-channel MOS transistor 10b
And its one conduction terminal is connected to the node Nb, and its control gate is connected to the sub-bit line SBLb.
An n-channel MOS transistor 11b having the other conduction terminal connected to signal line 15b and isolation transistors 12b and 13b for isolating nodes Na and Nb from sub-bit lines SBLb and ZSBLb in response to isolation instruction signal BLI, respectively. Including. Transistor 1
0b and 11b form a cross-coupled flip-flop when isolation transistors 12b and 13b are turned on (when the sense drive signal on signal line 15b is active). Sub-bit line SBLa and sub-bit line SBLb form one sub-bit line SBL when isolation transistors 12a and 12b are conductive. Similarly, the sub bit line ZSBLa and the sub bit line ZSB
Lb constitutes one sub-bit line ZSBL when isolation transistors 13a and 13b are turned on.

Drive amplifier 2 further includes read gate transistors 14a and 14b rendered conductive in response to read activation signal RS and connecting nodes Na and Nb to main bit lines MBL and ZMBL, respectively. The read gate transistors 14a and 14b
Is selectively made conductive, the potential amplitudes of the main bit lines MBL and ZMBL can be made smaller than the full swing. A signal at the ground potential level is transmitted to signal lines 15a and 15b through sense activation transistors NQa and NQb which are rendered conductive in response to sense activation signals SLA and SLB, respectively.

The amplifier 4 has one conduction terminal connected to the main bit line MBL and the other conduction terminal connected to the signal line 1.
P channel MOS transistor PT1 connected to receive the sense drive signal on 6, and one conduction terminal thereof is connected to main bit line ZMBL, and its control gate is connected to main bit line MBL and the other conduction terminal thereof. P-channel MOS connected to the signal line 16
The transistor PT2 is included. The amplifier 4 constitutes a cross-coupled sense amplifier that differentially amplifies the signal lines on the main bit lines MBL and ZMBL. Main bit lines MBL and ZMBL are connected to IO gates IGa and IG.
It is connected to the read data line 5 via b. Signal line 16
A signal at the power supply potential Vcc level is transmitted above through ap channel MOS transistor (sense activation transistor) PQ which is rendered conductive in response to sense activation signal SP. Next, the operation of the configuration shown in FIG. 3 will be described with reference to the operation waveform diagram of FIG.

FIG. 4 shows, as an example, a data read operation in the case where the selected memory cell stores "H" data.

In the standby mode, row address strobe signal / RAS (not shown) is in the inactive state of "H". In this state, the main bit line M
BL, ZMBL, sub-bit line SBL (SBLa, SB
Lb) and ZSBL (ZSBLa, ZSBLb) are precharged to an intermediate potential VBL (= Vcc / 2) by a precharge means (not shown). Isolation instruction signal BLI is also in the inactive state of "H", and isolation transistors 12a, 13a, 12b and 13b are in a conductive state.

When the memory cycle starts, row address strobe signal / RAS attains an active state of "L", correspondingly isolation instruction signal BLI attains an active state of "L", and isolation transistors 12a, 13a, 12b and 13b.
Turns off. As a result, the node NA is separated from the sub bit lines SBLa and SBLb, and the node N
B is isolated from sub-bit lines ZSBLa and ZSBLb.

This row address strobe signal / RAS
In response to the fall of the signal, the address signal (not shown) applied at that time is taken in, and the row selecting operation is started. In parallel with the row selecting operation, read activation signal RS rises to "H" and nodes Na and Nb are connected to main bit lines MBL and ZMBL, respectively. Then, the corresponding word line WL is selected according to the address signal, and the signal potential on the selected word line WL rises to "H". In response to the rise of the potential of the selected word line WL,
The data of the memory cell connected to the selected word line is transmitted onto the corresponding sub bit line, and the potential of the sub bit line changes from the precharged intermediate potential VBL. Figure 4
Then, the storage data of the selected memory cell MC is "H".
The case where the potential of the sub-bit line SBL rises is shown as an example. The other sub-bit line ZSBL maintains the precharged intermediate potential.

Then, when the sense activation signal SN (SNA or SNB) rises to "H", the sense drive signal becomes "L". As described above, the sub bit line SBL
When the data of the memory cell is transmitted to a, the sense activation signal SNA rises to "H". As a result, the other conduction terminals of transistors 10a and 11a attain the ground potential level. The potential on sub-bit line SBLa is higher than the potential on sub-bit line ZSBLa. Therefore, the potential of the node Nb is discharged via the transistor 11a. At this time, since almost no current flows through the transistor 10a (the transistors 10a and 11a form a source coupled logic), the node N
The potential of a only drops a little. Nodes Na and Nb are connected to main bit lines MBL and ZMBL via read gate transistors 14a and 14b, respectively. Therefore, the main bit line ZMBL
Potential drops from the precharged intermediate potential. The potential of the main bit line MBL only drops a little.

When the predetermined period has elapsed, the read activation signal R
S falls to "L" which is an inactive state, and the read gate transistors 14a and 14b are turned off. This ends the discharge of main bit line ZMBL, and the potential level thereof is maintained between intermediate potential VBL and the ground potential level. The main bit line MBL maintains almost the intermediate potential. In this way, by driving the read activation signal RS only for a predetermined period, the main bit lines MBL and Z
The potential amplitude of MBL is reduced. Then, sense activation signal SP falls to "L", amplifier 4 is activated, and the potential of main bit line MBL is raised to the level of power supply potential Vcc. At this time, the main bit line ZMBL holds the potential level discharged by the read gate transistor 14b.

On the other hand, when read gate transistors 14a and 14b are turned off, isolation instruction signal BLI attains "H" and transistors 12a, 13a, 12b and 13b are turned on. Then, the other sense activation signal SN (SNB) in the inactive state rises to "H", and transistors 10b and 11b operate as a cross-coupled sense amplifier. Thereby, sub-bit lines SBLa and SBLb and sub-bit line ZSBLa
And ZSBLb are transistors 10a, 11a, 10
Driven by b and 11b, the potential of the sub-bit line on the low potential side (sub-bit lines ZSBLa and ZSBLb in the above-described embodiment) is discharged to the ground potential level. The other sub-bit lines SBLa and SBLb are
The potential level corresponding to the data read from the memory cell is maintained. However, since the sub-bit line SBLa and the sub-bit line SBLb are connected, the potential level of the sub-bit line SBLa to which the memory cell data is transmitted is slightly lowered.

When the potential difference between main bit lines MBL and ZMBL is sufficiently expanded by the amplification by amplifier 4, column select signal YS rises to "H" and IO gate I
Ga and IGb become conductive, and the main bit line M
BL and ZMBL are connected to the read data line 5.
As a result, the signal potential on read data line 5 changes according to the signal potentials on main bit lines MBL and ZMBL, and then data is read out via the preamplifier and the output circuit.

Then, the read activation signal RS is again "H".
, And main bit lines MBL and ZMBL are connected to nodes Na and Nb. As a result, the low-potential main bit line ZMBL is connected to the transistors 10a, 11
It is discharged to the ground potential level by the sense amplifier composed of a, 10b and 11b. On the other hand, the sub-bit lines SBLa and SBLb on the high potential side are connected to the amplifier 4
As a result, it is charged up to the power supply potential Vcc level. This completes the operation of restoring data to the selected memory cell MC. Then, when one cycle of the memory cell is completed, the row address strobe signal / RAS becomes "H".
And the potential of the word line WL falls to "L".
Further, both sense activation signals SNA and SNB fall to the inactive state of "L", and read activation signal RS also falls to "L". Similarly, the column selection signal YS falls to "L", the sense activation signal SP falls to "H", and the main bit lines MBL and ZMBL and the sub bit lines SBL and ZSBL are brought to an intermediate potential by precharging means (not shown). Precharged to VBL.

As described above, when the data of the memory cell appears on the sub bit lines SBL and ZSBL, the potential change can be caused on the main bit lines MBL and ZMBL via the read gate transistors 14a and 14b, and the amplifier 4 can be generated. The activation timing can be accelerated, and data can be read at high speed. Also,
By setting the "H" period of the read activation signal RS to an appropriate time width, the main bit lines MBL and Z
The potential difference of MBL can be reduced, the charge / discharge current of the bit line at the time of data reading can be reduced, and the current consumption can be reduced. Even if the amplifier 4 is activated, the main bit lines MBL and ZMBL
Since the potential amplitude of is smaller than the difference between the power supply potential Vcc and the ground potential level, the main bit lines MBL and ZMB
The L potential determination timing can be accelerated, the column selection signal YS activation timing can be accelerated accordingly, and data reading can be accelerated.

Further, sense activation signals SNA and S
NB can be activated immediately after the rise of the potential of word line WL, and the potential of main bit lines MBL and ZMBL can be changed at the time when memory cell data appears on the sub-bit line, so that the data can be transferred at high speed. Reading can be performed.

Sense activation signals SNA and SN
Which of B is activated first determines which sub bit line pair (SBLa, ZSBLa and S) is selected by the selected word line.
BLb, ZSBLb), and this can be determined by, for example, the most significant bit of the row address signal.

The read activation signal RS may be held in the "H" state during standby. Main bit lines MBL and ZMBL and sub bit lines SBL and ZSBL can be precharged to the same potential.

In the operation waveform diagram shown in FIG. 4, when the read activation signal RS is raised to "H" for the second time, that is, when the memory cell data restore operation is performed, the potential of the read activation signal RS is increased. The level may be boosted to a voltage level higher than power supply voltage Vcc (for surely rewriting a signal at power supply potential Vcc level to a memory cell). Further, a configuration may be used in which isolation instruction signal BLI is boosted to a voltage level higher than power supply voltage Vcc during the restore period.

In the structure shown in FIG. 4, the transistors 10a, 11a, 10b, 11b and PT1 and PT2 for the amplification operation have conductivity (n channel and p).
The channels) may be configured to have opposite conductivity.

As described above, according to the first embodiment, data can be read at high speed with low current consumption.

[Modification 1] FIG. 5 shows a structure of a main portion of a semiconductor memory device according to a first embodiment of the present invention.
5, the drive amplifier 2 is the same as the configuration of the drive amplifier 2 shown in FIG.
It has the same structure except that p channel MOS transistors 20a and 20b are used instead of 0a and 11a. This p-channel MOS transistor 2
P channel MO for conducting 0 a and 20 b in response to sense activation signal SP and transmitting a signal at power supply potential Vcc level onto sense drive signal line 16.
An S transistor PQ is provided. P channel MOS transistors 20a and 20b charge one of nodes Na and Nb to the power supply potential level in response to the sense drive signal at power supply potential Vcc level on signal line 16.

Unlike amplifier 4 shown in FIG. 3, amplifier 4 will be described in detail later, but amplifier 4 does not change the signal potentials on main bit lines MBL and ZMBL, but on main bit lines MBL and ZMBL. The signal potential is amplified and transmitted to the IO gate side. Next, the operation of the configuration shown in FIG. 5 will be described with reference to the operation waveform diagram of FIG.

First, the signal lines 15 and 16 are precharged to an intermediate potential by a precharge means (not shown). Main bit lines MBL, ZMBL and sub bit lines SBLa, ZSBLa, SBLb, ZSBLb are precharged to the intermediate potential Vcc / 2. Isolation instruction signal BLI is at "H", and isolation transistors 12a, 13a, 12b and 13b are in the ON state. Therefore, nodes Na and Nb also have intermediate potential Vcc.
It is precharged to the level.

When the row address strobe signal / RAS falls to "L", a memory cycle is started and the precharge state is completed. In response to the fall of row address strobe signal / RAS, isolation instruction signal BLI falls to "L", and transistors 12a, 13a, 12
b and 13b are turned off.

Then, the potential of word line WL rises to "H", and the data of the memory cell connected to this selected word line WL is transmitted to the corresponding sub bit line. Now, in order to simplify the following description, consider a state in which the word line WLA is selected and the memory cell data is transmitted to the sub bit line SBLa. In this state, read activation signal RS is still at "L", main bit lines MBL and ZMBL maintain a precharge potential (intermediate potential), and nodes Na and Nb are precharged. There is.

Then, sense activation signals SP and SN are activated. At this time, the sense drive signal for detecting the selected memory cell data is activated first. Therefore, since the memory cell data is being transmitted to the sub bit line SBLa, the sense activation signal SP becomes "L" first, the sense activation transistor PQ becomes conductive, and the potential on the signal line 16 becomes the power supply potential Vcc level. Rise to. As a result, the transistors 20a and 20b are activated. When the potential of sub-bit line SBLa is higher than the potential of sub-bit line ZSBLa, node Na is charged through transistor 20a. At this time, almost no current flows through the transistor 20b, so that the potential of the node Nb hardly rises. This expands the potential difference between nodes Na and Nb. The other sense drive signal SN still maintains the inactive state. Since the potential on signal line 15 is the intermediate potential and the potentials on sub-bit lines SBLa and ZSBLa are also at the intermediate potential level, transistors 10b and 11 are provided.
No discharge occurs through b. When the sense drive signal is activated, the read activation signal RS becomes "H" for a predetermined period, and the read gate transistors 14a and 14b are rendered conductive. As a result, the potential difference between the main bit lines MBL and ZMBL increases. In FIG. 6, the operation waveform when the selected memory cell stores “H” data is shown by a solid line, and the operation waveform when the stored data of the selected memory cell is “L” is shown by a broken line. Show. Then, the amplifier 4 is activated and the main bit line MB
The signal potential difference on L and ZMBL is amplified and transmitted to the IO gate. Thereafter, the data of the selected memory cell is transmitted onto the read data line via the IO gate.

The read activation signal RS is in the active state "H" only for a predetermined period, the potential difference between the main bit lines MBL and ZMBL can be made sufficiently small, and the current consumption at the time of data reading can be reduced. Yes (because the driving period of the main bit line is short).

Then, isolation instruction signal BLI attains "H", and transistors 12a, 13a, 12b and 13b.
Turns on. As a result, the nodes Na and Nb
Of the other sub-bit lines SBLa and ZSBLa
Transmitted on. At this time, the other sense drive signal SN is also activated to fall to "H" and the potential on the signal line 15 is set to the ground potential level "L". Thereby, transistors 20a and 20b form a cross-couple type sense amplifier, and drive node Na and sub bit lines SBLa and SBLb to the power supply potential level. Transistors 10b and 11b form a clock-coupled N-channel sense amplifier and discharge node Nb and sub-bit lines ZSBLa and ZSBLb to the ground potential level. This completes the operation of restoring data to the selected memory cell. At this time, isolation instructing signal BLI may be configured to be boosted to a voltage level higher than the power supply potential Vcc level during the restore operation, and surely write "H" data.

When memory cell data is transmitted onto bit line SBLb, the sense drive signal on signal line 15 first attains an active state of "H", and one of nodes Na and Nb attains the ground potential level. And be discharged. Also in this case, the read activation signal RS is set to "H" only for a predetermined period, so that the main bit lines MBL and ZM.
The potential of BL is set to the intermediate potential and a voltage level lower than it, and the potential amplitude does not make a full swing, so that power consumption can be reduced. Also in this case, the amplifier 4 amplifies the potential difference and transmits it to the IO gate side.

As described above, by providing the p-channel MOS transistor pair and the n-channel MOS transistor pair for the sub bit line, the main bit line MBL is provided.
Also, it is not necessary to drive the sub-bit line by using the amplifier 4 provided in ZMBL, and the current consumption at the time of restoration can be reduced (because it is not necessary to fully swing main bit lines MBL and ZMBL). Transistors 20a, 20b, 10b and 11b are only required to have a capability of enlarging the potential difference between main bit lines MBL and ZMBL, and corresponding sub bit lines SBL (SBLa, SBLb and Z).
It is only required to drive SBLa, ZSBLb), and the current driving force can be made relatively small, and the area occupied by the drive amplifier can be made small.

In the sense activation signal, it is preferable to shift the sense drive signal, which is activated in a delayed manner, to the active state after the isolation instruction signal BLI is in the inactive state of "H". . For example, when the sense activation signal on signal line 15 is activated in a delayed manner, when sense drive signal SN is activated when isolation instruction signal BLI is "L", node Na is activated.
This is because it is possible that the potential of node Na is discharged to the ground potential level via transistor 10b and the potential difference between node Na and node Nb is reduced (transistors 10b and 11).
The potential of b is at the same intermediate potential level when the separation instruction signal BLI is "L").

In the data write operation, read activation signal RS may be forcibly driven and maintained in the active state of "H" in response to the data write instruction signal.

As described above, isolation instruction signal BLI is maintained in the active state of "L" and the potential difference between nodes Na and Nb is expanded to drive main bit lines MBL and ZMBL. The accompanying parasitic capacitance can be reduced, and the potential difference between the nodes Na and Nb can be increased at high speed.

[Amplifier Configuration] FIG. 7 is a diagram showing a specific configuration example of the amplifier shown in FIG. In FIG. 7, amplifier 4 transmits a read amplifier 40 for amplifying the signal potentials on main bit lines MBL and ZMBL, and data amplified by read amplifier 40 to nodes Nc and Nd in response to read enable signal R. Included are data read transistors 41a and 41b, and write transistors 42a and 42b transmitting the write data transmitted through IO gates IGa and IGb to main bit lines MBL and ZMBL when writing data. Write transistors 42a and 42b are rendered conductive in response to write instruction signal W.

Read amplifier 40 has an n-channel MOS transistor 45a having one conduction terminal connected to node Ne, its control gate connected to main bit line MBL, and the other conduction terminal connected to node Nh.
And a p-channel MOS transistor 44a having one conduction terminal connected to the node Ng, the other conduction terminal connected to the node Ne, and its control gate connected to the node Ne, and one conduction terminal connected to the node Nf. The n-channel MOS transistor 45b having the other conduction terminal connected to the node Nh and the control gate connected to the main bit line ZMBL, and the one conduction terminal connected to the node Ng and the other conduction terminal connected to the node Nf. P-channel MOS transistor 4 whose control gate is connected to node Ne.
4b and one conduction terminal thereof is connected to node Ne, its control gate is connected to receive read amplifier activation signal PAE, and the other conduction terminal thereof is connected to node Ng.
A p-channel MOS transistor 43a connected to
One conduction terminal is connected to node Nf, the other conduction terminal is connected to node Ng, and its control gate is connected to receive a read amplifier activation signal PAE.
Included is an n channel MOS transistor 46 discharging h to the ground potential level in response to read amplifier activation signal PAE. A voltage at the same potential level as power supply potential Vcc is transmitted to node Ng.

Output nodes Ne and N of read amplifier 40
f is not connected to main bit lines MBL and ZMBL (writing transistors 42a and 42b are in the off state during data reading). Therefore, read amplifier 40 has a high input impedance and does not change the signal potentials on main bit lines MBL and ZMBL.
The signal potential on the upper side is amplified to amplify the transistors 41a and 41a.
It is transmitted to nodes Nc and Nd via b. As a result, even if the signal potentials on the main bit lines MBL and ZMBL are very small, the main bit is driven at high speed without increasing the consumption current (since it is not necessary to fully swing the potentials on the main bit lines MBL and ZMBL). The signal potential on lines MBL and ZMBL can be amplified.

Read data line 5 includes read data bus lines 5a and 5b transmitting signals complementary to each other. These read data bus lines 5a and 5b are connected to preamplifier PA and write driver WD. The preamplifier PA is activated at the time of data reading, and the write driver W
D is activated at the time of writing data. Next, the operation will be briefly described.

At the time of data writing, read enable signal R is at "L" and transistors 41a and 41 are provided.
b is in the off state. At the time of data writing, write driver WD generates internal write data at a predetermined timing and changes the potentials of read data bus lines 5a and 5b to the potential level corresponding to the internal write data. Then, the column selection signal YS rises to "H" and the IO gate IGa
And IGb are turned on, and the main bit line MBL
And the signal potential on ZMBL changes to the potential level corresponding to the internal write data (transistors 42a and 42b are already turned on by write instruction signal W at this time). If the driving power of the write driver WE is sufficiently large, the potentials on the main bit lines MBL and ZMBL can be swung almost completely, and therefore the sense amplifier (p channel MOS) provided on the sub bit line can be used.
The signal potential amplified and latched by the transistor and the n-channel MOS transistor can be inverted according to the internal write data. When reading data,
The write instruction signal W is set to the inactive state of "L". As a result, the transistors 42a and 42b maintain the off state. In the standby state, read amplifier activation signal PAE is at "L", transistor 46 is off, while transistors 43a and 43b are on. This causes the precharge potential V on the node Ng.
cc is transmitted to nodes Ne and Nf, and nodes Ne and Nf hold the potential level of precharge potential Vcc.

When a signal potential difference occurs on main bit lines MBL and ZMBL, read amplifier activation signal PAE is activated to "H" at a predetermined timing. As a result, the transistor 46 is turned on, and the transistors 43a and 43b are turned off. Transistor 4
One of 5a and 45b is rendered conductive according to the signal potentials on main bit lines MBL and ZMBL. If the potential of main bit line MBL is higher than that of main bit line ZMBL, node Ne is discharged to the ground potential level. With the decrease in the potential level of node Ne, transistor 44b is turned on, and node Nf is charged to the level of power supply potential Vcc. As a result, nodes Ne and Nf are driven at high speed to the ground potential level and power supply voltage Vcc level, respectively. Node Ne
The signal potentials on Nf and Nf are transmitted to nodes Nc and Nd through transistors 41a and 41b. Then, column select signal YS rises to "H", and the signal potentials on nodes Nc and Nd change to read data bus lines 5a and 5d.
It is transmitted onto b, amplified by preamplifier PA and read.

The read amplifier 40 simply uses the nodes Ne and N.
It only drives f and Nc and Nb. Therefore, the current driving capability of read amplifier 40 can be relatively small, and the current consumption thereof can be made sufficiently small, and a relatively small signal potential difference on main bit lines MBL and ZMBL can be amplified at a high speed with a low current consumption. Can be transmitted over the gate.

Read instruction signal R may be set to an active state of "H" at the start of a memory cycle and inactivated when data write instruction signal W is generated. This is the read amplifier activation signal P
The same applies to AE.

[Alternative Example of Amplifier] FIG. 8 is a diagram showing a configuration of an alternative example of the amplifier shown in FIG. In FIG. 8, amplifier 4 amplifies the signal potentials on main bit lines MBL and ZMBL to read nodes Ni and Nj during data reading.
It includes a read amplifier 50 transmitting to the above, and a write amplifier 60 activated at the time of data writing, amplifying signal potentials on nodes Ni and Nj and transmitting to main bit lines MBL and ZMBL.

The read amplifier 50 includes nodes Nl and N1.
a p-channel MOS transistor 52a and an n-channel MOS transistor 51a, which are complementarily connected between k and whose gates are connected to the main bit line MBL,
In response to the read activation signal R, the node Nk is grounded in response to the p-channel MOS transistor 52b and the n-channel MOS transistor 51b which are complementarily connected between the nodes Nl and Nk and have their gates connected to the main bit line ZMBL. It includes an n channel MOS transistor 53 discharging to a level and ap channel MOS transistor 54 rendered conductive in response to read activation signal / R to charge node Nl to the level of power supply potential Vcc. Read amplifier 50 is activated in response to read activation signals R and / R, and a clocked inverter buffer for inverting and amplifying the signal potentials on main bit lines MBL and ZMBL and transmitting it to nodes Ni and Nj. It has an amplifier configuration.

The write amplifier 60 is complementarily connected between the node Nm and the node Nn and has its gate connected to the node Nm.
p channel MOS transistor 62a and n channel MOS transistor 61a connected to i, and node N
A p-channel MOS transistor 62b and an n-channel MOS transistor 61b, which are complementarily connected between m and a node Nn and have their gates connected to a node Nj.
An n channel MOS transistor 63 which is rendered conductive in response to write activation signal W and discharges node Nn to the ground potential level, and an electrical connection which is rendered conductive in response to write activation signal / W, and node Nn is connected to the power supply potential. N-channel M charging to Vcc level
The OS transistor 64 is included.

In FIG. 8, the main bit line MB is further added.
Precharge circuit 70 for precharging L and ZMBL to intermediate potential VBL in response to equalize signal EQ is also shown. Precharge / equalize circuit 7
0 is the main bit line M in response to the equalize instruction signal.
N-channel MO that electrically shorts BL and ZMBL
An S-transistor 71 is conductive in response to the equalize signal EQ and transmits an intermediate potential VBL to the main bit line MBL, and an n-channel MOS transistor 72 is conductive in response to the equalize signal EQ to bring the intermediate potential VBL into the main bit line. It includes an n-channel MOS transistor 73 transmitting to ZMBL. These transistors 71, 72 and 73 form an initialization transistor for initializing the main bit lines MBL and ZMBL to a predetermined precharge potential during standby of the semiconductor memory device. Main bit lines MBL and ZMBL may be precharged to intermediate potential Vcc / 2 or precharged to power supply potential Vcc level. Next, the operation of the amplifier shown in FIG. 8 will be briefly described.

At the time of data reading, the reading amplifier 5
0 is activated and write amplifier 60 is deactivated. When the potential difference between main bit lines MBL and ZMBL is increased, read activation signals R and / R are activated and transistors 53 and 54 are rendered conductive. As a result, transistors 51a and 52a operate as an inverter to invert and amplify the signal potential on main bit line MBL and transmit it to node Ni. On the other hand, the transistors 51b and 52b operate as an inverter,
The signal potential on main bit line ZMBL is inverted and amplified and transmitted to node Nj. In the case of the configuration of this read amplifier 50, since the clocked inverter circuit is used, the potentials of main bit lines MBL and ZMBL change in the opposite directions with respect to the reference potential (precharge voltage level of the intermediate potential level). There is a need to. This is because the potentials of main bit lines MBL and ZMBL may be determined to have the same logic level. A configuration for changing the potentials of main bit lines MBL and ZMBL in opposite directions centering on the reference potential will be described later.

At the time of writing data, the writing amplifier 6
0 is activated in response to write activation signals W and / W. In this case, internal write data (provided from the write driver shown in FIG. 7) applied via IO gates IGa and IGb is transmitted onto nodes Ni and Nj, and signal potentials on these nodes Ni and Nj. Is inverted and amplified and transmitted to main bit lines MBL and ZMBL. Thereby, the main bit lines MBL and ZM
The signal potential on BL fully swings (operating power supply potential Vc
(c level and ground potential level), data can be written to the selected memory cell.

Further, as the read amplifier, a current mirror type differential amplifier may be used instead of the configuration shown in FIGS. 7 and 8.

[Control Signal Generation System] FIG. 9 is a diagram showing a circuit configuration for generating various control signals. In FIG. 9, the control signal generating system receives an externally applied row address strobe signal / RAS and generates an internal row address strobe signal φRAS.
In response to the internal row address strobe signal φRAS from the RAS buffer 80, an address buffer 82 which takes in an externally applied address signal AD to generate an internal row address signal, and in response to the internal row address strobe signal φRAS. CA which is activated and generates an internal column address strobe signal φCAS in response to an externally applied column address strobe signal / CAS.
It includes an S buffer 84 and a write control circuit 86 which receives internal column address strobe signal φCAS from CAS buffer 84 and external write enable signal / WE to generate internal write control signal W. Address buffer 82
Receives an address signal AD externally applied according to internal column address strobe signal φCAS to generate an internal column address signal. Write control circuit 86 generates internal write instructing signal (write activation signal) W in accordance with activation of internal column address strobe signal φCAS and write enable signal / WE, whichever is later.

The control signal generation system is further activated in response to the internal row address strobe signal φRAS, decodes the internal row address signal from the address buffer 82 to select a word line, and word is selected on the selected word line. A row selection circuit 91 for transmitting a line drive signal WL, a separation control circuit 92 for generating a separation instruction signal BLI which is activated for a predetermined period in response to an internal row address strobe signal φRAS, an internal row address strobe signal φRAS and an address. It includes a sense amplifier activation circuit 93 which receives a predetermined address bit of the row address signal from buffer 82 and generates sense activation signals SP and SN.
The sense amplifier activation circuit 93 includes an address buffer 82.
A pair of sub-bit lines intersecting a selected word line is identified according to a predetermined address signal bit given from, and one of sense activation signals SP and SN is activated first according to the identification result. Sense amplifier activation circuit 9
3 has such a structure, a circuit for generating a sense activation signal, a delay circuit for delaying the sense activation signal for a predetermined time, and one of the sense activation signal and the output of the delay circuit according to an address signal bit. It can be realized by a circuit configuration including a multiplexer to be selected.

The control signal generation system further generates a connection control signal (read activation signal RS) in response to the internal row address strobe signal φRAS and the write instruction signal W from the write control circuit 86. And a read amplifier activation signal R (and P
A read activation circuit 95 for generating AE) is included.

When internal row address strobe signal φRAS is activated, connection control circuit 94 generates a one-shot pulse signal having a prescribed time width at a prescribed timing as read activation signal RS. In response to the write instruction signal from the write control circuit, connection control circuit 94 sets read activation signal RS to "H" in which internal row address strobe signal φRAS is active. Instead of this configuration, the connection control circuit 94, when the internal row address strobe signal φRAS is in the inactive state of “L”,
A configuration may be used in which the read activation signal RS is set to the active state of "H", and the internal row address strobe signal φRAS becomes "H", and then the inactive state of "L" is reached after a predetermined time has elapsed. In the case of this configuration, in response to the write instruction signal (write activation signal) W, the read activation signal RS
Are activated again to "H".

Read amplifier activation circuit 95 sets read amplifier activation signal R (and PAE) to inactive state "L" when write instructing signal W is generated.

In the case of the structure shown in FIG. 9, it is once activated regardless of whether data is written or read. The internal write data is written to the selected memory cell at the timing of the restore operation of the memory cell data. Instead of such a configuration, output enable signal / OE is externally applied, read amplifier activation circuit 95 is activated in accordance with output enable signal OE, and read amplifier activation signal R (and PAE) is generated. The configuration may be used.

[Modification 2] FIG. 10 shows a structure of a main portion of a second modification of the semiconductor memory device according to the first embodiment of the present invention. The configuration shown in FIG. 10 differs from the configuration shown in FIG. 5 in that isolation instruction signal BLIA applied to isolation transistors 12a and 13a is applied to isolation transistors 12b and 13b.
Same as B except that they are driven separately from each other. Isolation instruction signals BLIA and BLIB are generated such that only isolation transistors provided for the selected sub-bit line pair (to which selected memory cell data is transmitted) are once turned off. For example, when word line WLA is selected, isolation instruction signal BLIA attains an active state of "L". The other separation instruction signal BLIB maintains "H". Next, the operation will be described with reference to the operation waveform diagram of FIG.

In FIG. 11, sub-bit line SBLa is used.
An operation waveform when the data of the "H" memory cell is read is shown as an example. In the standby state when the row address strobe signal / RAS is "H", the isolation instruction signals BLIA and BLIB are both at "H",
Transistors 12a, 13a, 12b and 13b are all in the on state. Sub bit line SBL (SBLa,
SBLb) and ZSBL (ZSBLa, ZSBLb)
Is precharged to intermediate potential VBL, and nodes Na and Nb are also precharged to intermediate potential VBL. Further, main bit lines MBL and ZM
BL is also precharged to the intermediate potential VBL.

When the row address strobe signal / RAS falls to "L", the memory cycle starts, the precharge / equalize means (not shown) is inactivated, and the main bit lines MBL, ZMBL and the sub bit lines SBL and ZSBL are Floating state of intermediate potential. A row selection operation is performed according to a row address signal from the outside, and the potential of the selected word line WL rises to "H". Now, the word line WLA is selected and its potential rises to "H". The potential of the non-selected word line WLB remains "L". When the potential of the word line WLA rises, the data stored in the memory cell MC is stored in the sub bit line S.
It is transmitted to BLa, and the potential of the sub-bit line SBLa slightly rises.

At the same time as or before the rise of the potential of the word line WLA, the isolation instruction signal BLIA is set to "L".
Then, the separation transistors 12a and 13a are turned off. The other separation instruction signal BLIB maintains "H".

Then, sense amplifier activation signals SP and SN are generated. At this time, the sense activation signal SP is first activated to drive the nodes Na and Nb in accordance with the selected memory cell data. As a result, the sense drive signal SPD on the signal line 16 becomes "H".
, And transistors 20a and 20b start the sensing operation. The potential of the sub bit line SBLa is higher than the potential of the sub bit line ZSBLa (sub bit line ZS
BLa maintains the precharge potential). Therefore, node Na and sub-bit line SBLb are charged through transistor 20a and their potentials rise. Node Nb and sub-bit line ZSBLb substantially maintain the precharge potential. When the potential difference between nodes Na and Nb (potential difference between sub-bit lines SBLb and ZSBLb) increases, then sense activation signal SN is activated and sense drive signal SND on signal line 15 falls to "L". As a result, node Nb and sub-bit line ZSBLb are discharged and the potential thereof is lowered.

In parallel with this sensing operation, and before the start of sensing, read activation signal RS is activated and read gate transistors 14a and 14b are turned on. Therefore, the potentials on main bit lines SBL and ZSBL rise and fall in accordance with the potential changes on nodes Na and Nb, respectively. Read activation signal R
When S goes to "L", the main bit lines MBL and ZM
The potential change of BL stops. At this time, the main bit line M
The potentials of BL and ZMBL change symmetrically around the intermediate potential VBL of the precharge potential. Figure 8 above
Even if the inverter buffer amplifier shown in is used, if the input logic threshold value of this inverter buffer amplifier is set to the intermediate potential VBL, the main bit line MBL is surely
And performs amplification operation according to the potentials of ZMBL and IO
A signal potential corresponding to memory cell data can be transmitted to the gate. At this time, the potential amplitudes of the main bit lines MBL and ZMBL are determined by the operating power supply potential Vcc and the ground potential G.
It only has a small amplitude between ND, the charge / discharge current of the main bit lines MBL and ZMBL is small (only occurs while the read activation signal RS is in the active state), and the memory consumes less current. Cell data can be read.

On the other hand, with respect to the sub bit line, sense drive signals SPD and SND are kept active, and the potential of sub bit line ZSBLb is discharged to the ground potential level. When the predetermined time has elapsed, the separation instruction signal BLIA becomes "H", and the transistor 12a
And 13a are turned on. As a result, sub-bit lines SBLa and ZSBLa are charged / discharged to the high-level power supply potential Vcc level and the ground potential level, respectively, and the restore operation for the selected memory cell is executed. During this restore operation, the separation instruction signal B
A configuration in which LIA is boosted to a potential level higher than power supply potential Vcc may be used.

As described above, by activating only one separation instructing signal, the potentials of both main bit lines MBL and ZMBL change, but the potential amplitude is small and memory cell data can be read with low current consumption. It can be transmitted onto main bit lines MBL and ZMBL.
Further, since the potential amplitudes of main bit lines MBL and ZMBL are small, the activation timing of amplifier 4 can be made faster, for example, immediately after the read activation signal RS is inactivated, and data can be read at high speed. Can be performed (main bit lines MBL and ZMBL
If the potential of the full swing, it takes more time to determine the potential).

[Modification 3] FIG. 12 shows a structure of a main portion of a third modification of the first embodiment of the semiconductor memory device of the present invention. In the structure shown in FIG. 12, a memory cell (not shown) is divided into a plurality of blocks, and sub-bit lines SBL and ZSBL are arranged in each column for each memory cell block. In FIG. 12, a configuration divided into (n + 1) blocks is shown as an example. Further, in FIG. 12, word lines are not shown in order to avoid complication of the drawing. The arrangement of memory cells and word lines is the same as in the above-described embodiments and modifications. Sub bit line SBL (SBL0
0-SBL0n and SBL10-SBL1n are generically shown) and sub-bit line ZSBL (ZSBL00
-ZSBL0n and ZSBL10-ZSBL1n are collectively referred to as block select gates BG (BG00-BG).
0n and BG10 to BG1n) to be connected to the drive amplifier 2. Only the block including the selected memory cell is driven by the drive amplifier 2 and the sub bit lines SBL and ZSBL according to the block selection signal BS (BS0 to BSn).
Are connected to perform the sensing operation of the memory cell data. The non-selected block (memory cell block other than the block including the selected memory cell) maintains the precharged state, and the block selection signal BS is also inactive.

FIG. 13 shows a structure of a drive amplifier provided for a pair of sub-bit lines in the arrangement shown in FIG. In FIG. 13, the drive amplifier 2
Has an n-channel MOS transistor 10 whose one conduction terminal is connected to the node Na, whose control gate is connected to the node Ny and whose other conduction terminal is connected to receive the sense drive signal SND, and its conduction terminal. An n-channel MO connected to node Nb, its control gate connected to node Nx, and its conduction terminal connected to receive sense drive signal SND.
The S transistor 11 is included. Nodes Nx and Ny are
Sub-bit lines SBL and ZSBL are connected via block select gates BGa and BGb, respectively. Isolation transistor 12 which is rendered non-conductive in response to isolation instruction signal BLI is provided between nodes Na and Nx, and isolation instruction signal BL is provided between nodes Nb and Ny.
Separation transistor 13 which becomes non-conductive in response to I
Is provided. Transistors 10, 11, 12 and 1
The configuration and arrangement of No. 3 are the same as the configurations in the above-described embodiment (or modified example).

The drive amplifier 2 further includes a node Na
A p-channel MOS transistor 22a having its one conduction terminal connected to a control gate connected to the node Nb and the other conduction terminal connected to receive the sense drive signal SPD, and one conduction terminal connected to the node Nb. Included is a p-channel MOS transistor 22b connected with its control gate connected to node Na and having its other conduction terminal connected to receive sense drive signal SPD. Transistors 22a and 2
2b constitutes a cross-coupled sense amplifier (restore circuit). Nodes Na and Nb are connected to main bit lines MBL and ZMBL via read gate transistors 14a and 14b, respectively. Sense amplifier drive signals SPD and SND and read activation signal RS are activated only for the selected memory cell block. These signals SPD, SND, and RS remain inactive for the non-selected memory cell block. The same applies to the block selection signal BS. The operation of the configuration shown in FIGS. 12 and 13 will now be described with reference to the operation waveform diagram of FIG.

In FIG. 14, the selected memory cell stores the data of "H", and the sub bit line SBL
And ZSBL are precharged to the intermediate potential VBL, and main bit lines MBL and ZMBL are precharged to the power supply voltage Vcc level (more accurately, Vcc-Vth level: Vth is the threshold voltage of the precharge transistor). The operation waveform in the case of being shown is shown as an example. Further, isolation instruction signal BLI and read activation signal RS are maintained at "L" in the standby state, block select gates BGa and BGb are both off, and isolation transistors 12 and 13 are also off. is there.

When the potential of selected word line WL rises to "H", the data of the memory cell connected to this selected word line is transmitted to the corresponding sub bit line. In the following description, the word line WL1 is selected and the sub bit line S
It is assumed that "H" data is read to BL. Simultaneously with or before this word line selection operation, the block selection signal BS rises to "H", and the block selection gates BGa and BGb are turned on. This block selection signal B
S is boosted to a potential level higher than the power supply potential Vcc level.

When a potential difference occurs between nodes Nx and Ny, sense drive signal SND is first lowered to "L". Since the potential of the node Nx is higher than the potential of the node Ny, the node Nb is discharged through the transistor 11 and its potential drops. When a potential difference occurs between nodes Na and Nb, sense drive signal SPD is raised to "H" and transistors 22a and 2b start the sensing operation. The potential of the node Na is the node Nb
The potential of the node Na is raised by the transistor 22a because it is higher than the potential of the node 22a.

When the potential difference between nodes Na and Nb is sufficiently widened by transistors 10, 11, 22a and 22b, read activation signal RS rises to "H" for a prescribed time, and nodes Na and Nb are connected to main bit lines MBL and ZMBL. Connected to. The potential of main bit line MBL drops slightly, while the potential of main bit line ZMBL is discharged through transistors 14b and 11 and drops. When the potential difference between main bit lines MBL and ZMBL becomes a relatively large value, read activation signal RS becomes "L", and the change in potential difference between main bit lines MBL and ZMBL is completed. Here this main bit line M
Main bit line M when BL and ZMBL are connected
The potential of BL is slightly lowered because the potential of node Na has not risen sufficiently to the power supply potential Vcc level.

When the potential difference between main bit lines MBL and ZMBL becomes a relatively large value (sufficiently smaller than full swing), amplification operation is performed by amplifier 4 and data reading is performed. When this data reading is completed,
Precharge / equalize means (not shown) is activated, and the potentials of main bit lines MBL and ZMBL return to the precharge potential level. At this time, the read activation signal RS is already in the inactive state, the read gate transistors 14a and 14b are in the off state,
Nodes Na and Nb are connected to main bit lines MBL and Z.
Separated from MBL.

When read activation signal RS falls to "L", isolation instruction signal BLI rises to "H" and transistors 12 and 13 are turned on. At this time, isolation instruction signal BLI is boosted to a potential level higher than power supply potential Vcc (for surely rewriting "H" data to selected memory cell MC). When isolation instruction signal BLI rises, node Na is connected to node Nx and sub bit line SBL, and node Nb is connected to nodes Ny and ZSBL. As a result, transistors 10 and 11 operate as a cross-coupled sense amplifier, and nodes Nb and Ny and sub bit line ZS are operated.
BL is discharged to the ground potential level, and nodes Na and N
x and sub-bit line SBL are boosted to the power supply potential Vcc level. At the time of this rewriting, the word line W
The potential of L is also boosted to a potential level higher than the power supply potential Vcc level, and the data of "H" is surely written in the selected memory cell MC, and the restoration of the memory cell data is completed. In the operation waveform shown in FIG.
The case where the selected word line WL is boosted from the beginning to a potential level higher than the power supply potential Vcc level is shown. A configuration may be used in which block selection signal BS and word line WL are boosted to a potential level as high as power supply potential Vcc level only during a restore operation (when isolation instruction signal BLI is inactive). When the restore operation is completed, the potential of the selected word line WL falls to "L", each signal returns to the original initial state, and one memory cycle is completed.

Next, the data write operation will be described. In the data write operation, the operation until the sense drive signals SND and SPD are generated is the same as the data read operation. Before the read activation signal RS rises to "H", the potentials of the main bit lines MBL and ZMBL are driven to the potential level according to the write data. At the time of data writing, the potential amplitudes of main bit lines MBL and ZMBL are fully swung, and one of them is at power supply potential Vcc level.
The other becomes the ground potential level. When read activation signal RS rises to "H", the internal write data transmitted on main bit lines MBL and ZMBL are transmitted to nodes Na and Nb. Since the data of "L" is written now, the potentials of the nodes Na and Nb are set to the main bit line MB.
Varies according to the data transmitted from L and ZMBL. When the potentials of nodes Na and Nb change, isolation instruction signal BLI is at "L" and transistors 12 and 13 are off. According to the internal write data, the potential levels of nodes Na and Nb change to the ground potential level and the power supply potential level during the activation time of read activation signal RS. After a certain period,
The read activation signal RS becomes "L", and the read gate transistors 14a and 14b are turned off. When data writing is completed, main bit lines MBL and ZM
BL is precharged to a predetermined potential level by precharging / equalizing means (not shown).

On the other hand, when read activation signal RS falls to "L", isolation instruction signal BLI is boosted to a potential level higher than the power supply potential Vcc level and transistor 1
2 and 13 are turned on. As a result, the node N
a and Nb are connected to nodes Nx and Ny, respectively. The potentials of the nodes Na and Nb have already swung in accordance with the internal write data, and the data on the high level side are latched by the transistors 22a and 22b. Therefore, when nodes Na and Nb are connected to sub-bit lines SBL and ZSBL, node N
Although the potentials of a and Nb slightly change toward the intermediate potential level, the potentials of these sub-bit lines SBL and ZSBL depend on the internal write data due to the latch operation of transistors 10, 11, 22a and 22b again. And data is written to the selected memory cell. When the data writing is completed, the potential of the word line WL falls to "L", then each signal returns to the initial state and shifts to the standby state.

In the third modification, the sub bit line can be driven in block units, and the current consumption can be reduced. It is only the sub-bit line in the selected memory cell block that the potential fully swings at the time of data reading, and the current consumption at the time of data reading can be reduced. Further, since the sense drive signal SND is always generated first, the configuration of the sense drive signal generation circuit can be simplified.

In the structure shown in FIG. 13, the conductivity types of transistors 10, 11, 22a and 22b may be reversed.

[Fourth Modification] FIG. 15 shows the first modification of the present invention.
It is a figure which shows the structure of the 4th modification of the Example of this. Figure 15
The configuration shown in FIG. 12 provides a modification of the configuration shown in FIG. Figure 1
5, two adjacent sub-bit line pairs SBL
0, ZSBL0 and the sub-bit lines SBL1, ZSBL1 have p-channel M
It shares the OS transistor portion and the read gate transistor. That is, in FIG. 15, the cross-coupled p-channel MOS transistor 22 is
a and 22b are sub-bit lines SBL0 and ZSBL
Used when 0 is selected. When the sub bit lines SBL0 and ZSBL0 are selected, the transistors 10b and 11 are selected.
b, 12b and 13b operate (the block selection signal BS0 becomes "H"). When the sub bit lines SBL1 and ZSBL1 are selected, the transistor 10
a, 11a, 12a and 13a operate. Also at this time, the block selection signal BS1 becomes "H". The operation of the configuration shown in FIG. 15 is the same as that shown in FIG. The block selection signal BS, isolation instruction signal BLI, and sense drive signal SN for the selected sub-bit line are sequentially activated. The generation timing of the sense drive signal SP and the read activation signal RS is the same as that of the operation waveform shown in FIG.

In the case of the structure shown in FIG. 15, the p-channel MOS transistor included in the drive amplifier is shared by two sub-bit line pairs, so that the area occupied by the drive amplifier can be reduced and the memory cell array occupied area can be reduced. Can be made smaller.

Also in the structure shown in FIG. 15, the sense transistors may have opposite polarities. Further, the precharge potentials of main bit lines SBL and ZSBL may be at either intermediate potential level or power source potential level.

[Fifth Modification] FIG. 16 shows a first modification of the present invention.
It is a figure which shows the structure of the 5th modification of the semiconductor memory device which is the Example of this. The configuration shown in FIG. 16 has the drive amplifier 2
Are shared by the sub-bit line pair SBLa and ZSBLa and the sub-bit line pair SBLb and ZSBLb. Sub bit lines SBLa and ZSBLa and drive amplifier 2
Block select gates BGaa and BGab are respectively provided between the drive amplifier 2 and the sub bit line S.
Block select gates BGba and BGbb are provided between BLb and ZSBLb. Other configurations are shown in FIG.
The configuration is the same as that of the drive amplifier shown in FIG. However, the structure shown in FIG. 16 is slightly different in the generation mode of isolation instruction signals BLIB and BLIA.

FIG. 17 is a signal waveform diagram representing an operation of the drive amplifier shown in FIG. In FIG. 17, an operation waveform at the time of reading data when “H” data is read onto sub bit line SBLa is shown as an example. Next, the operation of drive amplifier 2 shown in FIG. 16 will be described with reference to the operation waveform diagram of FIG.

In the standby mode, block select signals BSA and BSB are at "L", and read activation signal RS is also at "L". Also, the separation instruction signal BLIB
And BLIA are both at "L". Sub bit line S
BLa, ZSBLa, SBLb and ZSBLb are precharged to the intermediate potential VBL, and main bit lines MBLa and MSBLa are also precharged to the intermediate potential.

When row address strobe signal / RAS falls to "L", the precharge operation is completed and the memory cycle starts.

Then, a word line (not shown in FIG. 16) is selected, and the potential of the selected word line WL rises. In parallel with this word line selection operation, the block selection signal BSA rises to "H". The potentials of block select signal BSA and word line WL are raised based on the internal row address signal bits. Selected word line W
The data of the memory cell connected to L is the sub bit line SB
It is transmitted onto La and the potential of the sub-bit line SBLa rises a little. Sub-bit lines ZSBLa, SBLb and Z
SBLb is at the precharged intermediate potential VBL. When the potential on the sub bit line SBLa changes,
Next, first, sense drive signal SPD rises to "H", and the potential of node Na rises due to charging via transistor 20a. When potentials on nodes Na and Nb occur, sense drive signal SND then falls to "L", node Nb is discharged through transistor 11, and the potential drops. Here, the separation instruction signal BLI
B rises to "H" almost simultaneously with the fall of the block selection signal BSA, and the separation transistors 12b and 13b are in the ON state. Separation instruction signal BLI
A is at "L". When the potential difference between the nodes Na and Nb is sufficiently widened, the read activation signal RS remains "H" for a predetermined period.
Rising to main bit lines MBLa and ZMBLa
Potential changes from the precharged intermediate potential. When the potential difference between main bit lines MBLa and ZMBLa is sufficiently widened (sufficiently smaller than full swing), read activation signal RS falls to "L". After that, data reading is executed via the amplifier 4 at an appropriate timing.

On the other hand, in parallel with this data reading, isolation instruction signal BLIA rises to "H", and nodes Na and Nb are connected to sub bit lines SBLa and ZSBLa. As a result, transistors 20a and 20b operate as a cross-couple type sense amplifier, and the potentials of sub-bit lines SBLa and ZSBLa change to the high level of the power supply potential Vcc level and the low level of the ground potential level, respectively. Here, the separation instruction signal BLIA and the block selection signal BSA are set to the power supply potential V during the restore operation.
It is boosted to a voltage level higher than cc. When this restore operation is completed, signal / RAS rises to "L" and the potential of word line WL falls to "L". Then
The sense drive signals SPD and SND respectively return to the intermediate potential, and the sub bit lines SBLa, ZSBLa, S
BLb and ZSBLb are precharged / equalized. After completion of precharge / equalization, block selection signal BSA and isolation instruction signals BLIA and BL
IB falls to "L". Sub bit line SBLa, ZS
Separation instruction signals BLIA, BLIB after precharge / equalize operations of BLa, SBLb and ZSBLb are executed by a precharge / equalize circuit (not shown).
Is set to "L", the potentials of sub-bit lines SBLa and ZSBLa and nodes Na and Nb can be surely precharged / equalized to the intermediate potential.

In the structure shown in FIG. 16, one drive amplifier is shared by two sub-bit line pairs, and the area occupied by the drive amplifier can be greatly reduced. Further, unlike the configuration shown in FIG. 10, since the restore operation is performed only on the memory block including the selected memory cell, the current consumption during the restore operation can be significantly reduced.

In the structure shown in FIG. 16, transistors 20a and 20b and transistors 10 and 11 are provided.
May each be made opposite in their conductivity. The sense drive signals SPD and SND are generated only for the drive amplifier associated with the selected memory cell. This structure can utilize the structure of sense amplifier activating circuit 93 in the control signal generating system shown in FIG. 9, for example. A block is identified with two memory cell blocks as a unit, a sense amplifier activation signal is generated, and the generation timing of this sense amplifier activation signal is determined in which block in the two memory cell blocks the memory cell is read. Can be determined by identifying Further, simply, a signal which is the logical product of the block selection signals BSA and BSB and the signal which is the logical product of the sense activation signals SP and SN output from the sense amplifier activation circuit 93 shown in FIG. 9 is used. Good.

[Sixth Modification] FIG. 18 is a diagram showing a sixth modification of the drive amplifier of the semiconductor memory device according to the first embodiment of the present invention. In drive amplifier 2 shown in FIG. 18, an n channel MOS transistor 24 for sense activation is provided between a connection node Nw of transistors 10 and 11 and a ground potential node. Further, p for sense activation is provided between the connection node Nz of the transistors 20a and 20b and the power supply potential Vcc supply node.
A channel MOS transistor 23 is provided. The sense activation signal SN is applied to the gate of the transistor 24, and the sense activation signal S is applied to the gate of the transistor 23.
P is given. An n-channel MOS transistor 25 which is rendered conductive in response to equalize signal EQ is provided between nodes Nw and Nz.

In this structure, sense nodes Nw and Nz are surely discharged and charged to the ground potential level and the power supply potential level by transistors 24 and 23, so that the sensing operation can be performed at high speed.
This is because charging / discharging does not occur via the sense drive signal line. Further, transistor 25 can surely precharge / equalize nodes Nw and Nz to an intermediate potential level (because nodes Nw and Nz are discharged and charged to the ground potential and the power supply potential level, respectively). With the configuration shown in FIG. 18, it is possible to realize a drive amplifier that operates at high speed. Further, in order to hold sense drive signals SPD and SND at an intermediate potential during standby, for example, in the configuration shown in FIG. 10, a signal line 15 and 16 is used during standby by using a transistor similar to equalize transistor 25 shown in FIG. Equalize sense drive signal to intermediate potential during standby by electrically shorting
Can be precharged.

[Modification 7] FIG. 19 shows a structure of a seventh modification of the first embodiment of the present invention. In the configuration shown in FIG. 19, the bit lines do not have a hierarchical structure of sub bit lines and main bit lines. Bit line pair BL
A drive amplifier is provided between a and ZBLa and bit line pair BLb and ZBLb. The structure of this drive amplifier is the same as that shown in FIG. However, read gate transistors 15a and 15b receive a column selection signal YS instead of a read activation signal at their gates, and connect nodes Na and Nb to internal data bus lines 5a and 5b, respectively, when selected. That is, the read gate transistors 15a and 15b have a function of an IO gate. The operation of the configuration shown in FIG. 19 is almost the same as the operation waveform shown in FIG. Instead of the read activation signal RS in the operation waveform shown in FIG.
S is used, and internal read data bus lines 5a and 5a are used instead of the main bit lines MBL and ZMBL.
Only b is used.

In the structure shown in FIG. 19, word line W
When the potential of L (WLA or WLB) rises and the memory cell data is transmitted onto the corresponding bit line, the sensing operation can be immediately performed to read the data. Therefore, column selection signal YS can be raised at a fast timing, and data can be read at a high speed. Since internal data bus lines 5a and 5b are driven by p channel MOS transistors 20a and 20b and n channel MOS transistors 10 and 11, the potential difference between the internal read data bus lines is expanded at high speed and data is read at high speed. be able to.

The precharge potential of read data bus lines 5a and 5b is not the intermediate potential but the power supply potential Vcc.
It may be a level. At this time, read data bus lines 5a and 5b may be provided with a transistor element for limiting the amplitude (for example, a transistor element for pulling up to the power supply potential Vcc or the intermediate potential). This is achieved by activating transistors for precharging internal read data bus lines 5a and 5b to a predetermined potential during standby during data reading.

In the structure shown in FIG. 19, the circuit portion for performing the sensing operation is the first portion described above.
The configurations of the embodiment and the first to sixth modifications may be used.

[Second Embodiment] FIG. 20 shows a structure of a main portion of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 20, a pair of main bit lines MB
The structure of a portion related to two memory cell groups in L and ZMBL is shown. In FIG. 20, sub-bit lines SBLa and ZSBLa and sub-bit line SBLb
And drive amplifier 2 are arranged between ZSBLb and ZSBLb. Main bit lines MBL and ZMBL are connected to these sub bit lines SBLa, ZSBLa, SBLb and ZS.
It is arranged in parallel with BLb. Main bit lines MBL and ZMBL are connected to amplifier 4. This amplifier 4
It has a configuration of a read amplifier for data output and a write driver for data write. The amplifier 4 has the configuration shown in FIG. 7 or 8.

Drive amplifier 20 has its one conduction terminal connected to node Na, its control gate connected to node Nb, and the other conduction terminal connected to receive sense drive amplifier SND.
The OS transistor 102, one conduction terminal of which is connected to the node Nb, and its control gate is the node Na.
And the other conduction terminal is the sense drive signal S
An n-channel MOS transistor 104 connected to receive ND, one conduction terminal thereof is connected to node Na, its control gate is connected to node Nb, and the other conduction terminal thereof is connected to receive sense drive signal SPD. P-channel MOS transistor 1
06, a p-channel MOS transistor 108 having one conductive terminal connected to node Nb, its control gate connected to node Na, and the other conductive terminal connected to receive sense drive signal SPD. Transistors 102 and 104 form a cross-coupled sense amplifier, and transistors 106 and 1
08 constitutes a cross-coupled sense amplifier.

Drive amplifier 2 further includes read activation transistors 116a and 116b formed of n channel MOS transistors which are rendered conductive in response to read activation signal RG and transmit a signal at the ground potential level, and on node Na. Activation transistor 1 in response to the signal potential of
Read gate transistor 11 for transmitting the signal of the ground potential level transmitted from 16a to main bit line MBL
4a, a read gate transistor 114b transmitting the signal of the ground potential level transmitted from transistor 116b to main bit line ZMBL in response to the signal potential on node Nb, and conducting in response to write activation signal WG. It includes a write gate transistor 112a connecting main bit line MBL and node Na, and a write gate transistor 112b conductive in response to write activation signal WG and connecting node Nb and main bit line ZMBL.

A block select gate BGaa which is rendered conductive in response to a block select signal BSA is provided between the node Na and the sub bit line SBLa, and a block select signal BSA is provided between the node Nb and the sub bit line ZSBLa in response to the block select signal BSA. A block select gate BGab that is conductive is provided. A block select gate BGba which conducts in response to a block select signal BSB is provided between the node Na and the sub bit line SBLb, and the node Nb and the sub bit line Z are provided.
A block select gate BGbb which is rendered conductive in response to a block select signal BSB is provided between SBLb. The operation of the drive amplifier shown in FIG. 20 will now be described with reference to the operation waveform diagrams of FIGS. 21 and 22.

First, referring to FIG. 21, the operation at the time of reading data will be described. During standby, sub-bit lines SBLa, ZSBLa, SBLb and ZSBL
b is precharged to the intermediate potential, and sense drive signals SND and SPD are precharged to the intermediate potential. Main bit lines MBL and ZMBL are also precharged to a predetermined potential. The precharge potential of the main bit lines MBL and ZMBL is the power supply potential V
It may be either the cc level or the intermediate potential VBL. Both block selection signals BSA and BSB are at "H" level.

When the row address strobe signal / RAS falls to "L", one memory cycle starts.
In response to the fall of signal / RAS, an address signal from the outside is taken in and an internal row address and a block address signal are generated (the block address signal is formed of a predetermined number of bits of the external row address signal). According to this block address signal, the block selection signal for the non-selected memory cell block becomes "L". For example, if the selected word line is the sub bit lines SBLa and ZSBL
When it intersects a, the block selection signal BSB falls to "L". As a result, the nodes Na and Nb
Are disconnected from the sub-bit lines (for example, SBLb, ZSBLb) of the non-selected memory cell block. Then, the word line is selected according to the row address signal, and the potential of the selected word line WL rises. As the potential of the selected word line WL rises, the data in the memory cell connected to the selected word line is transmitted to the corresponding sub bit line (eg, sub bit line SBLa).

In FIG. 21, sub bit line SBLa is used.
Shows an operation waveform when "H" data is read. The "H" data read onto the sub-bit line SBLa is transmitted to the node Na. Sub-bit lines SBLb and ZSBLb in the non-selected memory cell block are at the potential level of precharged intermediate potential VBL. When the potentials of nodes Na and Nb increase, sense drive signals SND and SPD are activated, and the potential levels of nodes Na and Nb swing fully. That is, according to the example shown in FIG. 21, the potential level of node Na rises to the power supply potential Vcc level and the potential level of node Nb falls to the ground potential level.

Then, read activation signal RG is activated and transistors 116a and 116b are turned on. Now, when the potential level of node Na is "H" and the potential level of node Nb is "L", the potential of main bit line MBL is discharged through transistors 114a and 116a and lowered. The potential of the main bit line ZMBL hardly drops. In FIG. 21, the main bit line M
Although it is shown that the potentials of both BL and ZMBL decrease, this is because the read activation signal RG is activated before the potentials of the nodes Na and Nb fully swing. The write activation signal WG is at "L". The amount of decrease in the potential of the main bit line MBL is
It is determined by the ratio of the resistance of transistors 114a and 116a to the resistance of main bit line MBL. The minimum reaching potential of the main bit line MBL is 2 · Vth. Vth is the threshold voltage of transistors 114a and 116a. Therefore, the main bit line MBL
Is not discharged to the ground potential level, the potential difference between the main bit lines MBL and ZMBL can be reduced, and the main bit lines MBL and ZMBL can be reduced.
The discharge current at the time of data reading can be reduced, and the data can be read with low current consumption. Since the potential difference between main bit lines MBL and ZMBL is small, the potential level is stabilized at high speed and data can be read at high speed. Thereafter, when data reading is performed through amplifier 4 and IO gate, read activation signal RG falls to "L" and transistors 116a and 116b are turned off. Main bit line M
When read activation signal RG is inactivated, BL and ZMBL are precharged / equalized to a predetermined potential level by precharging / equalizing means (not shown).

On the other hand, at the time of this data reading, the restore operation of the memory cell data is executed for sub bit lines SBLa and ZSBLa. At this time, a configuration in which block selection signal BSA is boosted to a potential level higher than power supply potential Vcc may be used. Signal / RA
When S rises to "L", one memory cycle is completed, the potential of the selected word line WL falls to "L", then the sense drive signals SPD and SND are deactivated, and then a pre-illustrated The charge / equalize circuit operates to perform the precharge / equalize operation of sub-bit lines SBLa and ZSBLa. Further, the block selection signal (BSB) which has been in the non-selected state rises to "H", and the sub-bit lines SBLb and ZSBLb included in the non-selected memory cell block become the node Na.
And Nb.

Further, in the operation waveform diagram shown in FIG.
The read activation signal RG may be activated before the potential of the selected word line WL rises, as indicated by the broken line. In this case, read gate transistors 114a and 114b drive main bit lines MBL and ZMBL from the time when the potential difference between nodes Na and Nb occurs according to the rise of the potential of selected word line WL, so that main bit lines MBL and ZMBL are driven. The potential determination timing can be accelerated, and data can be read at higher speed.

Next, referring to FIG. 22, the operation of writing data will be described. Data sense drive signal SP
The operation until D and SND are generated is the same as that at the time of data reading. The read activation signal RG rises to "H". When writing data, follow the write instruction signal
This read activation signal RG is forcibly set to the inactive state of "L". Thereafter, the internal write data is transmitted to main bit lines MBL and ZMBL from a write circuit (write drive) not shown, and the potentials of main bit lines SBL and ZSBL attain the potential level corresponding to the internal write data. After that, the write activation signal WG becomes "H",
Sub-bit line SBL in the selected memory cell block
And the potential of ZSBL changes to the potential level corresponding to the internal write data. This write activation signal WG is "H"
The period during which the memory cell data is restored may be any period during which data is read. In addition, in FIG.
Main bit lines MBL and ZMBL are at intermediate potential VBL
As an example, the data write operation when precharged to is shown. However, main bit lines MBL and ZMBL may be precharged to the level of power supply potential Vcc.

[Modification 1] FIG. 23 shows a first modification of the semiconductor memory device of the second embodiment. Figure 2
3, drive amplifier 2 serves as a data reading means, p-channel MOS transistors 126a and 126b which conduct in response to read activation signal / RG and transmit power supply potential Vcc level, and signal potentials on nodes Na and Nb. In response to transistors 126a and 12
It includes p channel MOS transistors 124a and 124b transmitting the potential signal applied from 6b to main bit lines MBL and ZMBL, respectively. Other configurations are the same as the configurations shown in FIG. Waveform diagrams of data read operation and data write operation of the configuration shown in FIG. 23 are shown in FIGS. 24 and 25, respectively. 24 and 25
In the operation waveform diagram shown in FIG. 5, main bit lines MBL and ZMBL are precharged to intermediate potential VBL. When reading data, "H" data is read,
Further, operation waveforms at the time of the operation of writing "L" data are shown.

The operation waveforms shown in FIGS. 24 and 25 are substantially the same as the operation waveforms shown in FIGS. 21 and 22. The polarity of the read activation signal / RG is simply different from that of the read activation signal RG, and the main bit line MB
The only difference is that the potentials of L and ZMBL rise above the precharge potential VBL during data reading. In the structure shown in FIG. 23 as well, the potential amplitudes of main bit lines MBL and ZMBL can be similarly reduced, and data can be read at high speed with low current consumption.

[Modification 2] FIG. 26 shows a second modification of the semiconductor memory device according to the second embodiment. Figure 2
6, main bit lines MBL and ZMBL are provided with a precharge circuit 9 for precharging main bit lines MBL and ZMBL to an intermediate potential during standby. Precharge circuit 9 is rendered conductive in response to precharge activation signal φR, and precharge potential VP (power supply potential Vcc or intermediate potential VBL).
To the main bit lines MBL and ZMBL, respectively.
Including 9b. The drive amplifier 2 is shown in FIG.
The same configuration as that shown in FIG. Next, the operation of the configuration shown in FIG. 26 will be described with reference to the operation waveform diagram of FIG.

First, with reference to FIG. 27A, the operation at the time of reading data will be described. In standby mode,
The precharge activation signal φR is at “L”, the transistors 129a and 129b are both in the ON state,
Main bit lines MBL and ZMBL are precharged to a predetermined precharge potential VP. Signal / RAS
When it falls to "L", the read activation signal RG becomes "H".
Then, the potential of the selected word line WL rises to "H". As a result, the transistor 11 shown in FIG.
4a, 114b, 116a and 116b operate and the potentials of main bit lines MBL and ZMBL change.
At this time, precharge activation signal φR is still in the "L" state, and pulls up the potentials of main bit lines MBL and ZMBL to precharge potential VP. Therefore, read gate transistors 114a and 116a, 1
Even if the current driving capability of 14b and 116b is relatively large, the potential amplitudes of main bit lines MBL and ZMBL can be reliably reduced, and data can be read at high speed. In this case, the main bit line MBL
(Or ZMBL) potential is the transistor 129a.
(129b) and the resistance of the driving transistors 114a and 116a (or 114b and 116b).

Next, referring to FIG. 27B, the operation at the time of reading data will be described. Whether or not data is written is determined by the states of the column address strobe signal / CAS and the write enable signal / WE. In this case, when the column address strobe signal / CAS and the write enable signal / WE both attain "L", the write data is sampled in the dynamic random access memory. This signal / CAS
And / WE both go low, precharge activation signal φR goes high and transistor 129a
And 129b are both turned off. After that, the internal write instruction signal WG is set to "H" for a predetermined period. As a result, main bit lines MBL and ZMBL have their potential amplitudes fully swung, and attain the potential level corresponding to the internal write data. When the write activation signal WG becomes "L" and the data writing is completed, the precharge activation signal φR becomes "L" again, and the main bit lines MBL and ZMBL.
Pre-charge is executed.

Even if the structure shown in FIG. 26 is used, the potential amplitudes of main bit lines MBL and ZMBL can be surely reduced during data reading, and the potential difference between main bit lines ZMBL and MBL is determined at high speed. ,
Data can be read at high speed.

FIG. 28 shows the precharge activation signal φ.
It is a figure which shows the circuit structure which produces | generates R. In FIG. 28, the precharge activation signal generation system includes a column address strobe signal / CAS and a write enable signal / CAS.
A write detection circuit 142 that receives WE, a write pulse generation circuit 144 that generates a write activation signal WG in response to a write detection signal generated in the form of a one-shot pulse from the write detection circuit 142, The flip-flop (FF) 146 which is set in response to the write detection signal from the write detection circuit 142 and generates the precharge activation signal φR, and the write activation signal WG from the write pulse generation circuit 144 are inactivated. Reset pulse generation circuit 1 that responds and generates a reset pulse
Including 48. The reset pulse from the reset pulse generation circuit 148 is supplied to the reset input of the flip-flop 146 to R. By utilizing the structure shown in FIG. 28, precharge activation signal φR can be generated, and the potential amplitudes of main bit lines MBL and ZMBL can be reliably reduced during data reading.

[Overall Structure] FIG. 29 schematically shows a structure of a portion related to data reading of a semiconductor memory device according to a second embodiment of the present invention. In FIG. 29,
The structure of a portion related to memory cells arranged in two columns (not clearly shown) is shown. The memory cell column is divided into a plurality of blocks. Sub-bit lines SBL and ZSBL are arranged for each memory cell column block. 1 for two adjacent sub-bit line pairs in the same column
Two drive amplifiers 2 are provided. In FIG. 29, for example, sub-bit line pair SBL00 and ZSB.
L00 and sub-bit line pair SBL01 and ZSBL01
The drive amplifier 2-00 is arranged between the two. Similarly, drive amplifier 2-0m is arranged between sub bit line pair SBL0p and ZSBL0p and sub bit line pair SBL0q and ZSBL0q.

Main bit lines MBL (MBL0, MBL1) and ZMBL are provided corresponding to the respective memory cell columns.
(ZMBL0, ZMBL1) are provided. A block selection signal BS (block selection signals BS0 to BSr is generically defined between the sub bit lines SBL and ZSBL (generally shown sub bit lines are shown) and the drive amplifier 2 (generally shown drive amplifier shown in FIG. 29). A block select gate that conducts in response to The main bit lines MBL0 and ZMBL0 are provided with an amplifier 4-0, and the main bit lines MBL1 and ZMBL1 are provided with an amplifier 4-1. Amplifiers 4-0 and 4-
1 is connected to read data bus 5 via IO gates IG0 and IG1 which are rendered conductive in response to column selection signals YS0 and YS1, respectively. The read data appearing on the read data bus 5 is the preamplifier PA and the output circuit OB.
Is output as external read data Dout.

Control signal generation circuit 150 is provided for generating block select signal BS, read activation signal RG and write activation signal WG. Control signal generation circuit 150 receives signals / RAS, / CAS and / WE from the outside to activate address buffer 152 and generate an internal address signal. The control signal generation circuit 150 takes in an address signal designating a block among the internal address signals generated by the address buffer 152, generates the read activation signal RG and the write activation signal WG only for the selected block, and The selection signal BS is generated.

As a generation mode of the block selection signal BS, a configuration is used in which all the block selection gates are rendered conductive in the standby mode and only the memory cell column block paired with the selected block is disconnected from the drive amplifier only during the operation. May be. Also, instead of this,
In the standby mode, the block select gates are all non-conductive, the column select signal BS related to the selected memory cell column block is activated during the operation, and the drive amplifier and the selected memory cell block are connected. May be. As a result, only the drive amplifier provided for the selected memory cell column block operates, and the remaining drive amplifiers do not operate, so that the current consumption during operation is reduced. This block selection signal BS
Of the block address signal is used as a bit for identifying which of the left and right memory cell blocks of the pair of memory cell column blocks is designated by the least significant bit, and the remaining block address signal bits are used. Can be easily realized by using it as a bit indicating whether or not two adjacent memory cell blocks are designated.

[Equalize / Precharge Transistor] FIG. 30 shows an arrangement of precharge transistors. As described above, sub-bit line pair SBL and ZSBL are precharged to intermediate potential VBL during standby. A memory cell is directly connected to the sub bit line. Therefore, a transistor for precharging the sub-bit line is formed using the same transistor (plan layout, sectional structure and manufacturing process) as the transistor included in the memory cell. This makes it possible to efficiently arrange the precharge transistors and reduce the memory cell array area. As shown in FIG. 30, a precharge transistor Qa is provided in a portion near drive amplifier 2 and is turned on in response to equalize signal EQ to precharge sub-bit line SBL to intermediate potential VBL. Further, for sub bit line ZSBL, equalize transistor Qb is provided at the end opposite to the end where precharge transistor Qa is provided. The equalize transistor Qb is rendered conductive in response to the equalize signal EQ and precharges the sub-bit line ZSBL to a predetermined intermediate potential VBL. The precharge transistors Qa and Qb have the same transistors as the access transistor Ma included in the memory cell MC. The same transistor means a transistor having the same layout pattern and manufactured in the same manufacturing process. In this case, memory cell patterns are regularly arranged along the column direction (in FIG. 30, two memory cells are arranged so as to be alternately connected to sub bit lines SBL and ZSBL). Therefore, if the precharge transistors Qa and Qb are generated using this pattern, the precharge transistors can be efficiently arranged. In this case, the signal line transmitting the equalize signal EQ and the adjacent word line WL (WL0 or WL0
The pitch of n) is the same as the word line pitch (pitch between adjacent word lines), and the signal line transmitting the equalize signal EQ can be formed in the same manufacturing process as the word line WL, and the manufacturing process is efficient. The precharge transistors Qa and Qb can be arranged in a small occupied area without increasing

By providing precharge transistors Qa and Qb outside the memory cell column, memory cells MC connected to word lines WL0 and WLn are
The memory cell layout pattern is arranged apart from the end portion. Therefore, no pattern breakage or pattern shape change occurs at the end of the memory cell layout pattern, and all memory cells MC
Can be formed with the same layout pattern, and the shape of the memory cell can be stabilized. As a result, all the characteristics such as the data retention characteristics of the memory cells can be made the same, and the reliability of the device is improved. That is, the precharge transistors Qa and Qb
Are formed in the same layout pattern as the memory cell transistors in the memory cell array, the precharge transistors Qa and Qb are
It functions as a precharge transistor while having a function as a dummy memory cell transistor for shape stabilization.

FIG. 31 is a diagram showing a schematic sectional structure of a precharge transistor and a memory cell. In FIG. 31, the precharge transistor Qa is the semiconductor substrate 2
High concentration impurity regions 201 and 20 formed on
2 and an electrode layer 203 formed via a gate insulating film (not clearly shown) formed on the semiconductor substrate 200.
And a low resistance metal layer 205 disposed in parallel with the gate electrode layer 203. Electrode wiring layer 204 for transmitting precharge potential VBL is connected to high concentration impurity region 201.

The memory cell MC has a high-concentration impurity region 20.
2 and 212, a gate electrode layer 213 formed through a gate insulating film, a conductive layer 214 formed in the high-concentration impurity region 212, and an insulating film (not explicitly shown) on the conductive layer 214. Formed cell plate electrode layer 21
Including 7. Gate electrode layer 213 is made of doped polysilicon, for example, and is electrically connected to low resistance metal wiring layer 215 formed in parallel with gate electrode layer 213 at a predetermined interval. A wiring layer 220 forming a sub bit line is connected to the high concentration impurity region 202, and the sub bit line 220 and the low resistance metal wiring layers 205 and 215 are connected.
A wiring layer 222 which is made of, for example, aluminum and constitutes a main bit line is formed thereon.

Wiring layer 222 forming the main bit line and wiring layer 220 forming the sub bit line are arranged in parallel with each other. The electrode layer 204 is formed in the same manufacturing process as the electrode layer 217 that functions as a cell plate that applies a constant potential to the memory cell capacitor. The low resistance metal wiring layer 205 arranged in parallel on the gate electrode layer 203 of the precharge transistor Qa is electrically connected at a predetermined interval like the word line. As a result, the equalize signal E
Q can be transmitted at high speed to all the precharge transistors Qa. In particular, the word line drive signal is formed by forming the signal line transmitting the equalizing signal EQ and the word line WL in the same stake structure (a structure in which the low resistance metal wiring layer and the polysilicon gate electrode layer are connected at predetermined intervals). The propagation delay time of the equalize signal can be made the same, each sub-bit line can be left in a floating state at a high speed immediately after the start of the memory cell, and then the word line can be selected immediately. Moreover, the word line potential drops when the memory cycle is completed. Each sub-bit line pair can be precharged to a predetermined potential at a high speed afterwards, and the sub-bit line can be precharged to a predetermined potential at a stable and high speed.

Further, since the precharge transistor is formed by utilizing the layout pattern of the memory cell transistor, no additional process for forming the precharge transistor is required, so that the manufacturing process can be simplified.

[Modification 1] FIG. 32 is a diagram showing a first modification of the arrangement for precharging the sub-bit lines to a predetermined potential. In the structure shown in FIG. 32, transistor Qc is provided so as to electrically short sub-bit lines SBL and ZSBL in response to equalize signal EQ. In this case, the sub bit lines SBL and ZSBL
If the equalization signal EQ becomes "H" after the potential of the power supply potential Vcc level and the ground potential level have fully swung (after the sense operation and the restore operation are completed), the intermediate potential Vcc between the power supply potential Vcc and the ground potential GND. / 2
Therefore, sub bit lines SBL and ZSBL can be surely precharged. The transistor Qc may be provided at both ends of the sub bit line pair.

[Modification 2] FIG. 33 shows a second modification of the arrangement of the equalizing / precharging transistors. In FIG. 33, an equalize transistor Qc is provided between sub bit lines SBL and ZSBL in response to equalize signal EQ, and sub bit line SBL is activated when equalize signal EQ is activated (“H”).
A) is provided with a precharge transistor Qa transmitting an intermediate potential VBL, and a subcharge line ZSBL is provided with a precharge transistor Qb transmitting in response to an equalize signal EQ and transmitting an intermediate potential VBL. Also in the structure shown in FIG. 33, transistors Qc, Qa and Qb are arranged with the same regularity as the transistors included in memory cell MC (the same layout pattern is repeated). Therefore, also in the structure shown in FIG. 33, the precharge / equalize transistor can be generated without using an extra mask in the same manufacturing process as the memory cell fabrication without adding an extra step to the precharge / equalize transistor. You can In the structure shown in FIG. 33, sub-bit lines SBL and ZSBL are surely precharged to intermediate potential VBL, and equalized and held at the precharge potential.

[Modification 3] FIG. 34 shows a structure of a third modification of the precharge / equalize transistor. In the configuration shown in FIG. 34, sub bit line SBL
Further, no equalizing transistor for periodically short-circuiting ZSBL is provided. Even in this case,
The layout pattern of the precharge transistors Qa and Qb has the same layout pattern as the memory cell transistor included in the memory cell MC, and is created in the same manufacturing process as the memory cell transistor. Therefore, the precharge transistors can be efficiently arranged, and the area occupied by the memory cell array can be reduced.

In the above description, the structure for precharging / equalizing the sub-bit line to precharge potential VBL has been described. However, as a transistor for equalizing / precharging the main bit line, a transistor having the same layout pattern as the memory cell transistor may be provided at the outermost portion of the memory cell column and used as a transistor for precharging / equalizing the main bit line. Further, precharge potential VBL transmitted by the precharge transistor may be the power supply potential Vcc level instead of the intermediate potential.

Further, in the present invention, a dynamic random access memory (dynamic semiconductor memory device) of an address multiplex system in which row address signals and column address signals are time-division multiplexed and given is described. However, an address non-multiplex type semiconductor memory device in which a row address signal and a column address signal are simultaneously applied may be used. In the case of the address non-multiplex type semiconductor memory device, data can be read at a higher speed. Since it is determined whether data writing or reading is performed at the time when the address signal is applied, the read amplifier circuit and the read gate transistor can be reliably turned off during data writing. Current consumption can be reduced.

As described above, according to the present invention, it is possible to realize a semiconductor memory device capable of reading data at a high speed with low current consumption and having a small array occupation area.

[0203]

According to the first aspect of the invention, since the drive amplifier means suppresses the potential amplitude of the second conductive line during data reading, the charge / discharge current of the second conductive line is reduced. It is possible to reduce current consumption during data reading. Further, since the potential amplitude of the second conductive line is reduced, the timing of determining the potential of the second conductive line is accelerated, and data can be read at high speed.

According to the second aspect of the invention, the transistor element pair in which the one conduction terminal and the control gate are cross-coupled is separated from the one conduction terminal and the corresponding sub bit line by the isolation transistor to form the main bit line pair. Since the data signal is transmitted, the potential of the main bit line can be changed when the memory cell data appears on the sub bit line pair, and the data can be read at high speed.

According to the third aspect of the invention, since the amplifying means provided on the main bit line is composed of a cross-coupled pair of transistor elements, it is possible to reliably restore the memory cell data during data reading. it can.

In the invention of claim 4, the drive amplifier means has an additional amplifying means, and this potential difference can be increased at high speed while suppressing the potential amplitude of the main bit line pair, and data can be transmitted at high speed. Can be read. Further, the potential of the sub bit line pair can be fully swung without affecting the potential of the main bit line pair, and the memory cell data can be restored while reducing the current consumption.

In the invention according to claim 5, since the amplifying means performs the amplifying operation so that the potential of the second conductive line is not changed, it is possible to reliably suppress the potential amplitude of the second conductive line. Therefore, the current consumption can be surely suppressed. Since the small amplitude signal on the second conductive line is amplified and output, the data can be read at a fast timing.

In the semiconductor memory device according to the sixth aspect, since the amplifying means provided on the second conductive line is composed of the buffer amplifier having the high input impedance, the small amplitude signal on the second conductive line is transmitted. Amplification and reading can be performed at high speed without affecting the potential, and low current consumption and high-speed data reading are possible.

According to the seventh aspect of the present invention, the first sensing means for initially reading the memory cell data of the one sub-bit line pair and the first sense means operating during the initial reading of the memory cell data of the other sub-bit line pair. Two sense means are provided, and the first and second sense means are respectively provided with separation means to separate the sub-bit line pair from the signal read node during the sensing operation. Therefore, one and the other (first And in any part of the second part), the main bit line pair can be driven at high speed in accordance with the data of the selected memory cell, even if the memory cell is in the selected state. Further, by the first and second sense means, the potential of the sub-bit line pair can be fully swung without the potential change of the main bit line, and the memory cell data can be surely restored.

According to the eighth aspect of the present invention, since the block selection gate is provided between the one and the other portions of the first conductive line, the drive amplifier means operates during operation of the one first conductive line. Without having to drive only
It is possible to reduce current consumption during drive amplifier operation. In addition, the drive amplifier does not need to operate after the memory cell data is transmitted to the entire first conductive line,
Drive amplifier operation timing can be accelerated,
Data can be read at high speed. When the first conductive line is a sub-bit line pair, the drive amplifier needs to drive only one sub-bit line pair when restoring the memory cell data, so that the load capacitance of the drive amplifier when restoring the memory cell data is reduced. The restore operation can be performed at a reduced speed, and at the same time, only one sub-bit line pair needs to be driven, so that the current consumption during the restore operation can be reduced.

According to the invention of claim 9, the read gate means is configured to drive the second conductive line to the first potential level in accordance with the signal potential on the first conductive line. The potential of the second conductive line can be changed before the potential is sufficiently amplified by the sense means, and high-speed data reading can be performed.

According to the tenth aspect of the present invention, a sub-bit line pair is formed by using a cross-coupled first conductive type first transistor element pair and a cross-coupled second conductive type second transistor element pair. Since the read gate is driven according to this differentially amplified signal potential by differentially amplifying the upper signal potential, the data on the main bit line pair can be changed at a high speed by driving the read gate at high speed. Data can be read with.

In the eleventh aspect of the invention, since the read gate means is activated before the sense means is activated, the potential of the main bit line pair is changed immediately after the word line is selected according to the memory cell data. Therefore, the data read timing can be accelerated.

According to the twelfth aspect of the invention, since the initialization transistor has a transistor having the same layout pattern as the memory cell transistor,
An initialization transistor can be formed by repeating the layout pattern of the memory cell array, an initialization transistor for precharge / equalization can be efficiently arranged in the memory cell array, and the area occupied by the memory cell array can be reduced. It is possible to do, and it is not necessary to add an extra manufacturing process for the initialization transistor,
The manufacturing process can be simplified.

By arranging the initialization transistor in the periphery of the memory cell array, the transistor of the memory cell is not arranged at the end or the beginning of the pattern, and the initialization transistor is used for stabilizing the shape of the memory cell. The function as a dummy transistor can also be provided, the shape and characteristics of the memory cell can be stabilized, and the reliability of the device can be improved. According to the invention of claim 13,
The potential of the sub-bit line pair is differentially amplified by the first and second cross-coupled transistor element pairs, and the read gate means is driven according to the potential of the sub-bit line pair, so that the main bit line pair is driven at high speed. The potential of can be changed.

According to the invention of claim 14, the first, second,
Since the potential of the sub-bit line pair is driven for a predetermined period in accordance with the potential of the one conduction terminal, the potential of the sub-bit line pair is driven in a state where one conduction terminal of the third and fourth transistor elements is separated from the sub-bit line. , The potential of the main bit line pair can be changed immediately after the word line is selected, and the data can be read at high speed.
The potential amplitude of the main bit line pair can be suppressed, and the current consumption can be reduced.

According to the fifteenth aspect of the invention, the initialization transistor for setting the potential of the bit line pair to a predetermined potential has the same layout pattern as the memory cell transistor, and the layout pattern in the memory cell array is repeated to initialize these. It is possible to dispose the initialization transistor, efficiently arrange the initialization transistor in the memory cell array, and reduce the area occupied by the array. Also, by arranging this initialization transistor in the peripheral portion of the memory cell array, the dummy transistor for stabilizing the shape of the memory cell can function as an additional transistor, so that the shape of the memory cell transistor can be stabilized and the reliability can be improved. It is possible to obtain a semiconductor memory device having high efficiency.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 3 is a diagram showing a configuration of a main part of a first embodiment of a semiconductor memory device according to the present invention.

FIG. 4 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 5 is a diagram showing a first modification of the first embodiment.

FIG. 6 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 7 is a diagram showing an example of a configuration of the amplifier shown in FIG.

FIG. 8 is a diagram showing another configuration example of the amplifier shown in FIG.

FIG. 9 is a diagram schematically showing a circuit configuration for generating a control signal used in the semiconductor memory device of the first embodiment.

FIG. 10 is a diagram showing a second modification of the first embodiment of the present invention.

11 is a signal waveform diagram representing an operation of the semiconductor memory device shown in FIG.

FIG. 12 is a diagram showing a configuration when the first embodiment is applied to a block division array.

13 is a diagram showing a configuration of the drive amplifier shown in FIG.

FIG. 14 is a signal waveform diagram representing an operation of the device shown in FIG.

FIG. 15 is a diagram showing a configuration of a fourth modification of the first embodiment.

FIG. 16 is a diagram showing a configuration of a fifth modification of the first embodiment.

17 is a signal waveform diagram representing an operation of the apparatus shown in FIG.

FIG. 18 is a diagram showing a sixth modification of the first embodiment.

FIG. 19 is a diagram showing a seventh modification of the first embodiment.

FIG. 20 is a diagram showing a configuration of a main part of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 21 is a signal waveform diagram representing an operation of the device shown in FIG. 20 during data reading.

22 is a signal waveform diagram representing an operation of the device shown in FIG. 20 during data writing.

FIG. 23 is a diagram showing a first modification of the second embodiment.

FIG. 24 is a signal waveform diagram representing an operation of the device shown in FIG. 23 during data reading.

25 is a signal waveform diagram representing an operation of the device shown in FIG. 23 during data writing.

FIG. 26 is a diagram showing a second modification of the second embodiment.

27A is a signal waveform diagram showing an operation at the time of data reading of the configuration shown in FIG. 26, and FIG. 27B is a signal waveform diagram showing an operation at the time of data writing of the configuration shown in FIG. .

28 is a diagram showing an example of a configuration of a precharge circuit drive signal generation system shown in FIG.

FIG. 29 is a diagram schematically showing an overall configuration of a semiconductor memory device when a second embodiment is applied to a block division array.

FIG. 30 is a diagram showing an arrangement of sub-bit line precharge / equalize transistors.

FIG. 31 is a diagram schematically showing a cross-sectional structure of the precharge transistor and the memory cell transistor shown in FIG. 30.

FIG. 32 is a diagram showing a first modification of the precharge / equalize transistor.

FIG. 33 is a diagram showing a second modification of the precharge / equalize transistor.

FIG. 34 is a diagram showing a third modification of the precharge / equalize transistor.

FIG. 35 is a diagram schematically showing an overall configuration of a conventional semiconductor memory device having a hierarchical data line structure.

36 is a signal waveform diagram schematically showing an operation of the semiconductor memory device shown in FIG. 35 at the time of data reading.

[Explanation of symbols]

 1a, 1b, first conductive line 2, 2a, 2b drive amplifier 3a, 3b second conductive line 4, 4a, 4b amplifier 5 internal read data line 5a, 5b read data bus line IG0, IG1 IO gate WL word line MC memory cell 10a, 10b, 10 n-channel MOS transistor 11, 11a, 11b n-channel MOS transistor 12a, 12b isolation transistor 13a, 13b isolation transistor 14a, 14b read gate transistor 15a, 15b sense drive transmission line 16 sense drive signal transmission line 16 20a, 20b p-channel MOS transistor 40 read amplifier 60 write buffer amplifier 70 precharge / equalize circuit SBL, ZSBL sub bit line MBL, ZMBL main bit line 112a, 112b Write gate transistor 114a, 114b Read gate transistor 116a, 116b Read activation transistor BG Block selection gate Qa, Qb Precharge transistor Qc Equalize transistor

Claims (15)

[Claims] 1. A plurality of memory cells, each of which stores information, are connected to the plurality of memory cells, and a first memory cell for transmitting / receiving data to / from a selected memory cell of the plurality of memory cells is provided. A conductive line; a second conductive line provided in parallel with the first conductive line; and a second conductive line corresponding to a signal potential on the first conductive line according to a signal potential on the first conductive line. Drive amplifier means for driving to a potential level to be controlled, the drive amplifier means having a second power supply potential whose signal amplitude on the second conductive line is lower than the first power supply potential and the second power supply potential. Means for suppressing an amplitude change on the second conductive line so as to be smaller than a potential amplitude between power supply potentials, and for transmitting a data signal corresponding to a signal potential on the second conductive line. A data read line, In response to No. 択信 and a gate means for connecting said second conductive line to the data read line, the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the first conductive line includes a pair of sub-bit lines transmitting signals of complementary logics, and the second conductive line is complementary to each other. A pair of main bit lines for transmitting signals of different logic, the drive amplifier means has a control gate connected to one sub bit line of the pair of sub bit lines and one conduction terminal of the pair of sub bit lines. A first transistor element of the first conductivity type connected to the other sub-bit line of and a other conduction terminal connected to receive the sense drive signal, and one conduction terminal of which is connected to the one sub-bit line and its control A second of the first conductivity type, the gate of which is connected to the other sub-bit line and the other conduction terminal of which is connected to receive the sense drive signal. A transistor element and, in response to a separation instruction signal, connecting respective control gates of the first and second transistor elements to the one and the other sub-bit lines, respectively, of the first and second transistor elements. Separation element means for separating one conduction terminal from the other and one sub bit line, and connection for connecting one conduction terminal of each of the first and second transistor elements to one and the other main bit lines of the main bit line pair. Means are provided. 3. The semiconductor memory device according to claim 2, further comprising a pair of second conductivity type provided for said main bit line pair and having their respective one conduction terminals and control gates cross-coupled. Further comprising an amplifying means including the transistor element of No. 1 and differentially amplifying the signal potential on the main bit line pair in response to the amplifier drive signal. 4. The semiconductor memory device according to claim 2, wherein the drive amplifier means further includes a pair of second conductivity type transistor elements whose one conduction terminal and the other conduction terminal are cross-coupled. An amplifying means for differentially amplifying the signal potential on the sub-bit line pair is provided. 5. The semiconductor memory device according to claim 1, further comprising: the second conductive line which is provided for the second conductive line without causing a change in a signal potential on the second conductive line. Further includes amplifier means for amplifying the signal potential on the conductive line and transmitting it to the read data line via the gate means. 6. The semiconductor memory device according to claim 1, further comprising a high input impedance, amplifying a signal potential on said second conductive line, and amplifying said signal potential onto said read data line via said gate means. It further comprises buffer amplifier means for transmitting. 7. The semiconductor memory device according to claim 1, wherein the first conductive line includes a first sub-bit line pair for transmitting signals of complementary logics, and the drive amplifier means includes the first sub-bit line pair. The drive amplifier means includes a second sub-bit line pair provided to extend in the opposite direction to the first sub-bit line pair and transmitting complementary logic signals. Cross-coupled and connected to the first sub-bit line pair,
A first bias circuit for differentially amplifying the signal potential of the first sub-bit line pair in response to the first sense drive signal to generate a signal corresponding to the differentially amplified signal at each one conduction terminal; A pair of first conductivity type first transistor elements, and a first transistor element while connecting each control gate of the first pair of transistor elements and the first pair of sub-bit lines in response to a separation instruction signal. A first for separating each one conduction terminal of the pair from the first sub-bit line pair
Isolation means, one conduction terminal of each of them and the control gate are cross-coupled and connected to the second sub-bit line pair,
The second transistor element pair of the second conductivity type for differentially amplifying the signal potential of the second sub-bit line pair in response to the sense drive signal of the second sub-bit line pair; A second for disconnecting each one conduction terminal of the second transistor element pair from the second sub-bit line pair while connecting each control gate of the second transistor element pair and the second sub-bit line pair. Separation means, one conduction terminal of each of the first transistor element pair is interconnected with one conduction terminal of each of the second transistor element pair, and connected to the main bit line pair via connection means. To be done. 8. The semiconductor memory device according to claim 1, wherein the first conductive line has first and second portions arranged on opposite sides with respect to the drive amplifier means. First separation means for separating the first conductive line of the first portion and the drive amplifier means in response to a block selection signal, and the second separation means in response to a second block selection signal. It further comprises a second separating means for separating the first conductive line of the second portion and the drive amplifier means. 9. The semiconductor memory device according to claim 1, wherein said drive amplifier means is a sense means for amplifying a signal on said first conductive line in response to said sense drive signal, and a read active state. Read gate means for being activated in response to the activation signal and driving the second conductive line to the first power supply potential level in response to the output of the sensing means when activated. 10. The semiconductor memory device according to claim 1, wherein the first conductive line includes a pair of sub bit lines, and the second conductive line includes a pair of main bit lines. The drive amplifier means has one conductive terminal and each control gate cross-coupled to each other and connected to the pair of sub-bit lines, and outputs the signal potentials of the pair of sub-bit lines in response to a first sense drive signal. A first conductivity type first transistor element pair for differential amplification, one conduction terminal of each pair and each control gate are cross-coupled and connected to the sub-bit line pair to form a second sense drive signal. A second transistor element pair of a second conductivity type for differentially amplifying the signal potentials of the pair of sub-bit lines in response to Is provided between the main bit lines and one of the sub-bit line of the sub-bit line pair,
A first gate for transmitting the first power supply potential to the one main bit line in response to a signal potential on the one sub bit line; another main bit line of the main bit line pair and the sub bit Provided between the other sub-bit line of the line pair,
A second gate for transmitting the first power supply potential onto the other main bit line in response to a signal potential on the other sub bit line is included. 11. The semiconductor memory device according to claim 9, wherein the read activation signal is activated earlier than the activation of the first and second sense drive signals. 12. The semiconductor memory device according to claim 1, wherein said memory cell has a control gate for receiving a cell selection signal, and transmits information stored at the time of selection onto said first conductive line. A control gate including a transistor element, having the same size as the control gate formed in the same wiring layer as the control gate of the transistor element of the memory cell and the memory cell transistor element, and setting the first conductive line to a predetermined potential during standby. An initialization transistor for maintaining the level is provided. 13. A plurality of memory cells each storing information, a plurality of sub-bit line pairs connected to the plurality of memory cells and transmitting complementary logic signals, and arranged in parallel with the sub-bit line pair. , And a main bit line pair for transmitting signals of mutually complementary logics, each one conduction terminal and each control gate are cross-coupled and connected to the sub-bit line pair,
A first conductivity type first transistor element pair for differentially amplifying a signal potential on the sub-bit line pair, one conductive terminal of each of the first transistor element pair and each control gate are cross-coupled, and Connected,
A second conductivity type second transistor element pair for differentially amplifying a signal potential on the sub-bit line pair, and a read activation signal provided between the main bit line pair and the sub-bit line pair. A semiconductor memory device including a pair of read gates activated in response to an activation signal and driving a corresponding main bit line to a prescribed potential level in response to a signal potential on a corresponding sub bit line when activated. . 14. A plurality of memory cells each storing information, and a plurality of sub-bit line pairs connected to the plurality of memory cells for transmitting and receiving data to and from the selected memory cell,
The sub-bit line pair is divided into first and second portions for transmitting signals whose logics are complementary to each other.
And a second bit line, and a pair of signal lines for connecting the first and second sub-bit lines of the first and second portions, one conductive terminal of which has one of the signal line pairs. Is connected to the signal line of the first part, and its control gate is connected to the second part of the first part.
Connected to the sub-bit line and the other conduction terminal is the first
A first transistor element of the first conductivity type connected so as to receive the sense drive signal, and one conduction terminal of the first transistor element is connected to the other signal line of the signal line pair, and its control gate is connected to the first portion of the first portion. The other conduction terminal connected to the first sub-bit line is the first
A second transistor element of the first conductivity type connected to receive the sense drive signal of the second conductive element, a conductive terminal of the second conductive element is connected to the one signal line, and a control gate of the second transistor element of the second portion of the second portion. A third transistor element of the second conductivity type connected to the sub-bit line, the other conduction terminal of which is connected to receive the second sense drive signal, and one conduction terminal of which is connected to the other signal line, A fourth of the second conductivity type, the control gate being connected to the first sub-bit line of the second portion, and the other conducting terminal being connected to receive the second sense drive signal.
A pair of first separation transistors for separating the signal line pair from the first and second sub-bit lines of the first portion in response to a separation instruction signal; In response to the separation instruction signal, the signal line pair and the second line
And a second isolation transistor element pair for isolating the sub-bit line pair in the section of (1), and for connecting the signal line pair and the main bit line pair for a predetermined period when the isolation instruction signal is activated. A semiconductor memory device comprising a pair of transfer transistor elements. 15. A device for transmitting signals whose logics are complementary to each other.
A pair of bit lines, a plurality of word lines arranged so as to intersect the sub-bit line pair, a plurality of word lines arranged corresponding to the intersection of each of the plurality of word lines and the sub-bit line pair, each storing information A memory cell having an access transistor for coupling the capacitor to an associated sub-bit line in response to a signal potential on a word line corresponding to the capacitor and a memory cell having the same layout pattern as the access transistor; A semiconductor memory device, comprising: an initialization transistor for setting the sub-bit line pair to a predetermined potential level during activation.