CN110097907A - SRAM memory - Google Patents
SRAM memory Download PDFInfo
- Publication number
- CN110097907A CN110097907A CN201810083598.3A CN201810083598A CN110097907A CN 110097907 A CN110097907 A CN 110097907A CN 201810083598 A CN201810083598 A CN 201810083598A CN 110097907 A CN110097907 A CN 110097907A
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- bit line
- block
- sense bit
- control signal
- signal wire
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The present invention provides a kind of SRAM memory.The SRAM memory includes: multiple blocks, block number meets 2 exponential function, the storage unit of each block is single-ended eight pipes sram cell, the item number of the sense bit line of each block is identical, whole sense bit lines of each block are provided with corresponding control signal wire, each sense bit line respectively with corresponding control signal wire wiring when it is adjacent laying and direction it is parallel, so as to be coupled between corresponding sense bit line and control signal wire by line capacitance；Two adjacent blocks cooperate, mutually matched two blocks share one group of difference amplifier, the number of difference amplifier is identical as the item number of the sense bit line of each block, the first input end of difference amplifier is connected to a sense bit line of one of block, and the second input terminal is connected to the corresponding sense bit line of the read bit line position of another block connected with first input end.The present invention can be improved the data reading speed of SRAM.
Description
Technical field
The present invention relates to memory technology field more particularly to a kind of SRAM memories.
Background technique
The storage unit of SRAM memory includes the diversified forms such as 6 transistor memory units, 8 transistor memory units, wherein single-ended eight
Pipe sram cell is as shown in Figure 1, Read-write Catrol is separated, including a write word line WWL, two write bit lines BL and BLB, one
A readout word line RWL and sense bit line RBL.
For using for SRAM memory of the single-ended eight pipes sram cell as storage unit, as shown in Fig. 2, working as SRAM
When memory carries out read operation, it is only capable of being read out single-ended eight pipes sram cell by a sense bit line RBL, i.e., single-ended reading
It takes.Because referring to without contrast signal, when being read " 0 " operation to single-ended eight pipes sram cell, RBL needs under VDD
The trigging signal VDD/2 for drawing phase inverter, could read data；When the sram cell hung on sense bit line is more and more, read
Leakage current on bit line is increasing, and will result in data reading speed becomes slower and slower.
Summary of the invention
To solve the above-mentioned problems, the present invention provides a kind of SRAM memory, can eliminate the influence of leakage current, improves single
Hold the data reading speed of eight pipe sram cells.
The present invention provides a kind of SRAM memory, comprising: multiple blocks, block number meet 2 exponential function, Mei Gesuo
The storage unit for stating block is single-ended eight pipes sram cell, and the item number of the sense bit line of each block is identical, each described
Whole sense bit lines of block are provided with corresponding control signal wire, each sense bit line respectively with corresponding control signal wire
Wiring when it is adjacent laying and direction it is parallel, so as to carry out coupling by line capacitance between corresponding sense bit line and control signal wire
It closes；
Two adjacent blocks cooperate, and mutually matched two blocks share one group of difference amplifier, differential amplification
The number of device is identical as the item number of sense bit line of each block, and the first input end of the difference amplifier is connected to wherein
One sense bit line of one block, the second input terminal of the difference amplifier be connected to another block with it is described first defeated
Enter the connected corresponding sense bit line of read bit line position in end, when the difference amplifier is used for reading data, when with institute
The sram cell stated on a wherein sense bit line for difference amplifier connection is selected, exports the number of the sram cell storage
According to.
Optionally, the control signal wire and corresponding sense bit line are all disposed within metal layer in wiring.
Optionally, the control signal wire incoming control signal, under the influence of control signals, the control signal wire are logical
The line capacitance coupled relation between corresponding sense bit line is crossed, touches the current potential of the corresponding sense bit line when carrying out read operation
It is dealt into a voltage value.
Optionally, for mutually matched two blocks, the bit line conduct of the selected reading data of one of block
Work bit line, and the sense bit line in another block corresponding with the working position line position works as working position as reference bit lines
When line current potential is higher than reference bit lines current potential, difference amplifier exports high level, when work bit line potential is lower than reference bit lines current potential
When, difference amplifier exports low level.
Optionally, the line capacitance in each block between corresponding sense bit line and control signal wire is with the area
The size variation of storage array in block and change.
SRAM memory provided by the invention can provide a reference bit lines in reading data for work bit line, ginseng
The work bit line for examining bit line and reading data is separately connected two input terminals of difference amplifier, and passes through difference amplifier and export
The reading manner of single-ended eight pipes sram cell is designed to that difference is read by the data of reading, compared with prior art, the present invention, from
And the influence for eliminating leakage current can be reached, accelerate the data reading speed of single-ended eight pipes sram cell.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of single-ended eight pipes sram cell；
Fig. 2 is the structural schematic diagram of existing SRAM memory；
Fig. 3 is the structural schematic diagram of one embodiment of SRAM memory of the invention；
Fig. 4 is the SRAM memory of the invention working timing figure when reading " 0 " operates；
Fig. 5 is the SRAM memory of the invention working timing figure when reading " 1 " operates.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of SRAM memory, and the SRAM memory includes: multiple blocks, that is to say, that
SRAM uses the structure of Multi-Bank, such as SRAM may include 2,4 or 8 blocks, and block number meets 2 index
Function, the storage unit of each block are single-ended eight pipes sram cell, and the item number of the sense bit line RBL of each block is identical, often
The item number of the readout word line RWL of a block may be slightly different as needed, and whole sense bit line RBL of each block are provided with pair
The control signal wire answered, the adjacent laying and direction is flat in wiring with corresponding control signal wire respectively of each sense bit line
Row, so as to be coupled between corresponding sense bit line and control signal wire by line capacitance；
Two adjacent blocks cooperate, and mutually matched two blocks share one group of difference amplifier, differential amplification
The number of device is identical as the item number of sense bit line RBL of each block, and difference amplifier has there are two input terminal, difference amplifier
First input end is connected to a sense bit line of one of block, and the second input terminal of difference amplifier is connected to another area
The corresponding sense bit line of the read bit line position of block connected with first input end, the effect of difference amplifier are to read
When the data of sram cell, when the sram cell on the wherein sense bit line connecting with difference amplifier is selected, output should
The data of sram cell storage.
In general, control signal wire and corresponding sense bit line are all disposed within metal layer in wiring.It is accessed on control signal wire
One control signal, under the influence of control signals, control signal wire are coupled by the line capacitance between corresponding sense bit line
The current potential of corresponding sense bit line is triggered to a voltage value when carrying out read operation by relationship.In general, when reading the data,
For mutually matched two blocks, the bit line of the selected reading data of one of block is as work bit line, with work
Sense bit line in another corresponding block of bit line position is as reference bit lines, when work bit line potential is higher than reference bit lines electricity
When position, difference amplifier exports high level, and when the bit line potential that works is lower than reference bit lines current potential, difference amplifier exports low electricity
It is flat.
It is further to note that the line capacitance in each block between control signal wire and corresponding sense bit line be with
The size variation of storage array in each block and change, when storage array is big, line capacitance also with becoming larger, when
When storage array is small, line capacitance is also with becoming smaller, therefore no matter how storage array changes, and control signal wire can lead to
It crosses line capacitance coupling and reference bit lines is energized into a suitable current potential, rather than use fixed capacitive coupling, because using
Reference bit lines can be energized into a very low current potential, read by fixed capacitive coupling when storage array is small
When " 0 " operates, reading speed can not be effectively improved；When storage array is larger, reference bit lines can be energized into one
A higher current potential may will affect the correctness of function when being read " 1 " operation.
In order to clearer, to be illustrated for including a SRAM memory of two blocks.As shown in figure 3,
SRAM memory includes that the storage unit of two block BANK0 and BANK1, BANK0 and BANK1 are single-ended eight pipes SRAM mono-
The structure of member, BANK0 and BANK1 are identical, respectively contain N+1 sense bit line and m+1 readout word line, and N, m are positive integer, BANK0
Sense bit line be successively denoted as RBL0 [0]~RBL0 [N], the readout word line of BANK0 is successively denoted as RWL0 [0]~RWL0 [m], BANK1
Sense bit line be successively denoted as RBL1 [0]~RBL1 [N], the readout word line of BANK1 is successively denoted as RWL1 [0]~RWL1 [m], BANK0
A corresponding control signal wire, the corresponding control signal of RBL0 [0] are respectively provided with the BANK1 whole sense bit lines for respectively being included
Line is denoted as BSTB0 [0], and the corresponding control signal wire of RBL0 [1] is denoted as BSTB0 [1], and so on, the corresponding control of RBL0 [N]
Signal wire is denoted as BSTB0 [N], and similarly, the corresponding control signal wire of RBL1 [0] is denoted as BSTB1 [0], the corresponding control of RBL1 [1]
Signal wire processed is denoted as BSTB1 [1], and so on, the corresponding control signal wire of RBL1 [N] is denoted as BSTB1 [N], each sense bit line
Respectively with corresponding control signal wire wiring when it is adjacent laying and direction it is parallel so that corresponding sense bit line and control
Coupled between signal wire by line capacitance, i.e. there are line capacitance coupling between RBL0 [0] and BSTB0 [0], RBL0 [N] and
There are line capacitance couplings between BSTB0 [N], and there are line capacitance coupling, RBL1 [N] and BSTB1 between RBL1 [0] and BSTB1 [0]
There are line capacitance couplings between [N].
BANK0 and BANK1 cooperates, and shares one group of difference amplifier, if SRAM includes four block BANK0,
BANK1, BANK2, BANK3, then BANK0 and BANK1 cooperate, and BANK2 and BANK3 cooperate, due to BANK0 and
BANK1 respectively contains N+1 sense bit line, and therefore, SRAM memory further includes N+1 difference amplifier, be successively denoted as SA [0]~
SA [N], wherein the first input end of SA [0] is connected to the sense bit line RBL0 [0] of BANK0, the second input terminal connection of SA [0]
To the sense bit line RBL1 [0] of BANK1, SA [1] first input end is connected to the sense bit line RBL0 [1] of BANK0, and the second of SA [1]
Input terminal is connected to the sense bit line RBL1 [1] of BANK1, and so on, the first input end of SA [N] is connected to the read bit of BANK0
Line RBL0 [N], the second input terminal of SA [N] are connected to the sense bit line RBL1 [N] of BANK1, and each difference amplifier is respectively used to
When reading data, when the sram cell on the wherein sense bit line connecting with difference amplifier is selected, it is mono- to export the SRAM
The data of member storage.
Working principle of the SRAM memory shown in Fig. 3 when reading data is discussed in detail below.
Read operation is carried out when to a sense bit line in one of block BANK0, such as to the RBL0 [M] in BANK0
When, RBL0 [M] is the bit line that works, and makes full use of the corresponding read bit in position in the block BANK1 in off position
RBL1 [M] is used as reference bit lines, due to being equipped with one in the close position of RBL1 [M] by line, i.e. RBL1 [M] in BANK1
The control signal wire BSTB1 [M] parallel with its direction applies a control signal to BSTB1 [M], by BSTB1 [M] and
Line capacitance coupled relation between RBL1 [M], so that it may which RBL1 [M] is energized into some current potential VRef, difference amplifier SA
Two input terminals of [M] are respectively connected to RBL0 [M] and RBL1 [M], the difference between the current potential and current potential VRef on RBL0 [M]
When reaching certain threshold value, difference amplifier SA [M] is opened, and exports the data to be read.Current potential on RBL0 [M] is lower than VRef,
SA [M] exports low level, and the current potential on RBL0 [M] is higher than VRef, and SA [M] exports high level.Obviously, a kind of difference is employed herein
Divide the mode for reading data.
Specifically, before carrying out read operation, RBL0 [M] is first charged to high level in advance.
When being read " 0 " operation, as shown in figure 4, RBL0 [M] its waveform indicated by the solid line, RBL1 [M] are represented by dashed line
Its waveform, before RWL0 [m] unlatching, BSTB1 [M] becomes " 0 " from " 1 ", coupled by line capacitance RBL1 [M] is energized into it is a certain
Current potential, after opening RWL0 [m], RBL0 [M] current potential is pulled down to by sram cell less than the certain threshold value of this current potential, the threshold value
It is adjusted according to the design needs, if threshold value can be set to 100mV, difference amplifier is then opened by enable signal SAENI
SA [M], final OUTPUT export low level.
When being read " 1 " operation, as shown in figure 5, RBL0 [M] its waveform indicated by the solid line, RBL1 [M] are represented by dashed line
Its waveform, similarly, before RWL0 [m] unlatching, BSTB1 [M] becomes " 0 " from " 1 ", is swashed RBL1 [M] by line capacitance coupling
It is dealt into a certain current potential, after opening RWL0 [m], due to being to read " 1 ", RBL0 [M] does not need to pull down, and passes through enable signal SAENI
Difference amplifier SA [M] directly is opened, final OUTPUT exports high level.
Accordingly, if carry out read operation to the RBL1 [M] in BANK1, RBL1 [M] is the bit line that works, sufficiently benefit
With the corresponding sense bit line in position in the block BANK0 in off position, i.e. RBL0 [M] in BANK0, by RBL0
[M] is used as reference bit lines, due to being equipped with a control signal wire parallel with its direction in the close position of RBL0 [M]
BSTB0 [M] applies a control signal to BSTB0 [M], couples pass by the line capacitance between BSTB0 [M] and RBL0 [M]
System, so that it may RBL0 [M] is energized into some current potential VRef, two input terminals of difference amplifier SA [M] are respectively connected to
RBL0 [M] and RBL1 [M], when the difference between the current potential and current potential VRef on RBL1 [M] reaches certain threshold value, differential amplification
Device SA [M] is opened, and exports the data to be read.Specific working sequence is similar with RBL0 [M] is read, and details are not described herein.
It can thus be seen that SRAM memory provided in an embodiment of the present invention, can be work bit line in reading data
A reference bit lines are provided, reference bit lines and the work bit line for reading data are respectively connected to two inputs of difference amplifier
End carries out difference reading by difference amplifier, can eliminate the influence of leakage current, reading speed is faster.Further, this hair
The bright reference bit lines used are not to increase additional reference bit lines, but take full advantage of existing in off position
Sense bit line does not need to increase too many peripheral circuit as reference bit lines, therefore does not need to increase too many area.Meanwhile this
Reference bit lines used in inventing are to follow the variation of work bit line and change, and the load that the two bit lines are born is the same
, therefore this two comparison bit lines are quite matched.Further, the present invention by control signal wire and reference bit lines it
Between line capacitance coupling mode deexcitation reference bit lines to certain current potential, since line capacitance is the size with storage array
Variation and change, no matter storage array is big or small, and reference bit lines can be excited to a suitable current potential, therefore
The memory of arbitrary size is applicable to using the design that line capacitance couples.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (5)
1. a kind of SRAM memory characterized by comprising multiple blocks, block number meet 2 exponential function, Mei Gesuo
The storage unit for stating block is single-ended eight pipes sram cell, and the item number of the sense bit line of each block is identical, each described
Whole sense bit lines of block are provided with corresponding control signal wire, each sense bit line respectively with corresponding control signal wire
Wiring when it is adjacent laying and direction it is parallel, so as to carry out coupling by line capacitance between corresponding sense bit line and control signal wire
It closes；
Two adjacent blocks cooperate, and mutually matched two blocks share one group of difference amplifier, difference amplifier
Number is identical as the item number of sense bit line of each block, and the first input end of the difference amplifier is connected to one of them
One sense bit line of block, the second input terminal of the difference amplifier are being connected to another block with the first input end
The corresponding sense bit line of the read bit line position connected, the difference amplifier be used for reading data when, when with the difference
Divide the sram cell on a wherein sense bit line for amplifier connection selected, exports the data of the sram cell storage.
2. SRAM memory according to claim 1, which is characterized in that the control signal wire and corresponding sense bit line exist
Metal layer is all disposed within when wiring.
3. SRAM memory according to claim 1, which is characterized in that the control signal wire incoming control signal,
Under the action of controlling signal, the control signal wire is being carried out by the line capacitance coupled relation between corresponding sense bit line
The current potential of the corresponding sense bit line is triggered to a voltage value when read operation.
4. SRAM memory according to claim 1, which is characterized in that for mutually matched two blocks, wherein one
The bit line of the selected reading data of a block is as work bit line, another block corresponding with the working position line position
In sense bit line as reference bit lines, when the bit line potential that works is higher than reference bit lines current potential, difference amplifier exports high level,
When the bit line potential that works is lower than reference bit lines current potential, difference amplifier exports low level.
5. SRAM memory according to claim 1, which is characterized in that in each block corresponding sense bit line and
Line capacitance between control signal wire changes with the size variation of the storage array in the block.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810083598.3A CN110097907B (en) | 2018-01-29 | 2018-01-29 | SRAM memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810083598.3A CN110097907B (en) | 2018-01-29 | 2018-01-29 | SRAM memory |
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| CN110097907A true CN110097907A (en) | 2019-08-06 |
| CN110097907B CN110097907B (en) | 2021-03-19 |
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| CN1750171A (en) * | 2004-09-15 | 2006-03-22 | 株式会社瑞萨科技 | Semiconductor integrated circuite device |
| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102637448A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Amplifier sensing |
| US8345469B2 (en) * | 2010-09-16 | 2013-01-01 | Freescale Semiconductor, Inc. | Static random access memory (SRAM) having bit cells accessible by separate read and write paths |
| US8848474B2 (en) * | 2013-01-22 | 2014-09-30 | Lsi Corporation | Capacitive coupled sense amplifier biased at maximum gain point |
| CN106558336A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | For the negative voltage bit line compensation circuit and its method of work of SRAM circuit |
-
2018
- 2018-01-29 CN CN201810083598.3A patent/CN110097907B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1750171A (en) * | 2004-09-15 | 2006-03-22 | 株式会社瑞萨科技 | Semiconductor integrated circuite device |
| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| US8345469B2 (en) * | 2010-09-16 | 2013-01-01 | Freescale Semiconductor, Inc. | Static random access memory (SRAM) having bit cells accessible by separate read and write paths |
| CN102637448A (en) * | 2011-02-14 | 2012-08-15 | 台湾积体电路制造股份有限公司 | Amplifier sensing |
| US8848474B2 (en) * | 2013-01-22 | 2014-09-30 | Lsi Corporation | Capacitive coupled sense amplifier biased at maximum gain point |
| CN106558336A (en) * | 2015-09-30 | 2017-04-05 | 展讯通信（上海）有限公司 | For the negative voltage bit line compensation circuit and its method of work of SRAM circuit |
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| CN110097907B (en) | 2021-03-19 |
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