CN110071542B

CN110071542B - Charging circuit, charging method and terminal

Info

Publication number: CN110071542B
Application number: CN201910286304.1A
Authority: CN
Inventors: 范建功
Original assignee: Dongguan Ronpin Electronic Technology Co ltd
Current assignee: Dongguan Ronpin Electronic Technology Co ltd
Priority date: 2019-04-10
Filing date: 2019-04-10
Publication date: 2023-01-13
Anticipated expiration: 2039-04-10
Also published as: CN110071542A

Abstract

The embodiment of the invention provides a charging circuit, a charging method and a terminal, wherein the charging circuit comprises: a normal charging circuit and a standby charging circuit; the normal charging circuit consists of a USB female socket, a common mode inductor, a first switching circuit, a second switching circuit and a charging management chip PMIC, wherein the common mode inductor, the first switching circuit, the second switching circuit and the charging management chip PMIC are sequentially connected with a connecting wire led out from a D + pin and a D-pin of the USB female socket; the standby charging circuit consists of a VBUS contact, a timer and an inverter I0, one end of the VBUS contact is connected with the PMIC, the other end of the VBUS contact comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the first switch circuit, and the second branch circuit is sequentially connected with the timer, the inverter I0 and the second switch circuit; when the normal charging circuit fails, a low level is input to a VBUS contact of the standby charging circuit to activate the standby charging circuit to charge the terminal, and the problem that the terminal cannot be temporarily charged after the normal charging circuit fails is solved.

Description

Charging circuit, charging method and terminal

Technical Field

The present invention relates to the field of charging terminals, and in particular, to a charging circuit, a charging method, and a terminal.

Background

Along with the popularization of various intelligent terminals such as smart phones and the like and the higher integration level of various intelligent terminals, the functions carried on the intelligent terminals are richer and stronger, for example, along with the improvement of the shooting level of the smart phones, people finish most of video shooting and daily photo shooting through the mobile phones, and along with the popularization of social software such as WeChat and the like, people store some important information on the smart phones more and more. There are also smart wearable devices that are becoming more and more popular, and these wearable devices can detect the physical condition of a user by monitoring the daily activity and various physical signs of the user, and as these smart devices become more and more popular, the personal important information stored therein becomes more and more important.

Most of current intelligent devices are driven by electric energy stored in a battery carried by the intelligent devices, and along with the more abundant functions of the intelligent terminal, the power consumption speed of the intelligent terminal is higher and higher, so that the electric energy needs to be frequently supplemented for the intelligent terminal, along with the more and more personal information stored in the intelligent terminal, the information becomes more and more important for users, and meanwhile, due to the fact that frequent charging easily causes charging faults of the intelligent terminal, the situation that the intelligent terminal cannot be started and user data is lost due to the charging faults on the intelligent terminal is increased and more, and therefore the situation that another charging method is provided for the intelligent terminal is very important when the charging faults occur on the intelligent terminal.

Disclosure of Invention

The invention aims to solve the technical problem that when an intelligent terminal has a charging fault, an additional charging circuit is provided to ensure that the intelligent terminal can be temporarily charged for use, and provides a charging circuit, a charging method and a terminal aiming at the technical problem.

In order to solve the above technical problem, the present invention provides a charging circuit, which is suitable for a terminal carrying a high-pass charging solution, and the charging circuit includes: a normal charging circuit and a standby charging circuit;

the normal charging circuit consists of a USB female socket, a common mode inductor, a first switch circuit, a second switch circuit and a charging management chip PMIC, wherein the common mode inductor, the first switch circuit, the second switch circuit and the charging management chip PMIC are sequentially connected with a connecting wire led out from a D + pin and a D-pin of the USB female socket;

the standby charging circuit consists of a VBUS contact, a timer and an inverter I0, one end of the VBUS contact is connected with a charging management chip PMIC, the other end of the VBUS contact comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the first switch circuit, and the second branch circuit is sequentially connected with the timer, the inverter I0 and the second switch circuit;

when the D + and D-pin paths of the USB female socket are abnormal, a low level is input to the VBUS contact through the VBUS pin of the USB male socket, the first switch circuit is disconnected, the second switch circuit is connected, and charging is carried out through the standby circuit.

Optionally, the charging circuit further includes: and the central processing unit is connected with the charging management chip PMIC.

Optionally, the first switch circuit is composed of two NMOS transistors, gates of the two NMOS transistors are connected to each other, sources of the two NMOS transistors are connected to a connection line led out from a D + pin and a D-pin of the USB female socket, respectively, and a drain of the two NMOS transistors is connected to the PMIC.

Optionally, the second switch circuit is disposed between the first switch circuit and the charging management chip PMIC, and the second switch circuit is as close to the charging management chip PMIC as possible.

Optionally, the second switch circuit is a PMOS transistor, a gate of the PMOS transistor is connected to the inverter I0 of the standby circuit, a source of the PMOS transistor is connected to a connection line led out from the D-pin of the USB socket, and a drain of the PMOS transistor is connected to a connection line led out from the D + pin of the USB socket.

Further, the invention also provides a charging method, which is suitable for a terminal carrying a high-pass charging solution, and the charging method comprises the following steps: charging under normal conditions and charging under abnormal conditions;

the VBUS contact of the standby charging circuit is input with high potential or suspended, the D + and D-connecting wires of the normal charging circuit are normally conducted, and charging is carried out under normal conditions;

when the paths of the D + and D-connecting lines of the normal charging circuit are abnormal, a VBUS contact of the standby charging circuit inputs a low level, and the standby charging circuit is adopted to carry out charging under the abnormal condition.

Optionally, the normal charging circuit includes: the charging management circuit comprises a USB female socket comprising a D + pin and a D-pin, and a common mode inductor first switch circuit, a second switch circuit and a charging management chip PMIC which are sequentially connected through a D + connecting wire and a D-connecting wire; the first switch circuit is composed of two NMOS transistors with mutually connected grids, and the second open-tube circuit is a PMOS transistor;

the backup charging circuit includes: and a VBUS contact, wherein one end of the VBUS contact is connected with the PMIC through a lead wire, a first branch at the other end of the VBUS contact is connected with the grid electrode of the first switch circuit, and a second branch is connected with a timer and an inverter I0 at a time and is connected with the grid electrode of the second switch.

Optionally, in normal charging, the VBUS contact of the standby charging circuit inputs a high potential or is floating, the two NMOS transistors of the first switching circuit are turned on, the timer does not operate and the voltage level at the merchant is low, so that the timer I0 outputs a high potential, thereby turning off the PMOS transistor of the second switching circuit, and at this time, the D + and D-connection lines of the normal charging circuit are normally connected.

Optionally, when a path of a D + and a D-connection line of the normal charging circuit is abnormal, a low level is input to a VBUS contact of the standby charging circuit, the timer starts to operate to time and output a high level, so that the timer I0 outputs a low level, the PMOS transistor of the second switching circuit is turned on, two NMOS transistors of the first switching circuit are short-circuited, and thus the second switching circuit is turned off, and the standby charging circuit is used for charging.

Furthermore, the invention also provides a terminal, which comprises a battery and the charging circuit, wherein the battery is charged through the charging circuit.

Advantageous effects

The embodiment of the invention provides a charging circuit, a charging method and a terminal, aiming at the problem that the existing terminal can not be charged after charging failure occurs, the charging circuit is designed, and comprises: a normal charging circuit and a standby charging circuit; the normal charging circuit consists of a USB female socket, a common mode inductor, a first switch circuit, a second switch circuit and a charging management chip PMIC, wherein the common mode inductor, the first switch circuit, the second switch circuit and the charging management chip PMIC are sequentially connected with a connecting line led out from a D + pin and a D-pin of the USB female socket; the standby charging circuit consists of a VBUS contact, a timer and an inverter I0, one end of the VBUS contact is connected with the PMIC, the other end of the VBUS contact comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the first switch circuit, and the second branch circuit is sequentially connected with the timer, the inverter I0 and the second switch circuit; when the normal charging circuit fails, a low level is input to a VBUS contact of the standby charging circuit to activate the standby charging circuit to charge the terminal, and the problem that the terminal cannot be charged after charging failure occurs is solved.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

fig. 1 is a schematic diagram of a hardware structure of an optional mobile terminal for implementing various embodiments of the present invention.

FIG. 2 is a diagram of a wireless communication system for the mobile terminal shown in FIG. 1;

fig. 3 is a schematic diagram of a charging circuit according to a first embodiment of the invention;

fig. 4 is a flowchart of a charging method according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a terminal according to a third embodiment of the present invention.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.

The terminal may be implemented in various forms. For example, the terminal described in the present invention may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and a fixed terminal such as a Digital TV, a desktop computer, and the like.

The following description will be given by way of example of a mobile terminal, and it will be understood by those skilled in the art that the construction according to the embodiment of the present invention can be applied to a fixed type terminal, in addition to elements particularly used for mobile purposes.

Referring to fig. 1, which is a schematic diagram of a hardware structure of a mobile terminal for implementing various embodiments of the present invention, the mobile terminal 100 may include: an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an a/V (audio/video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and a power supply 111. Those skilled in the art will appreciate that the mobile terminal architecture shown in fig. 1 is not intended to be limiting of mobile terminals, which may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

The following describes each component of the mobile terminal in detail with reference to fig. 1:

the radio frequency unit 101 may be configured to receive and transmit signals during information transmission and reception or during a call, and specifically, receive downlink information of a base station and then process the downlink information to the processor 110; in addition, uplink data is transmitted to the base station. Typically, radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with a network and other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to GSM (Global System for Mobile communications), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000 ), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division duplex Long Term Evolution), and TDD-LTE (Time Division duplex Long Term Evolution).

WiFi belongs to short-distance wireless transmission technology, and the mobile terminal can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 102, and provides wireless broadband internet access for the user. Although fig. 1 shows the WiFi module 102, it is understood that it does not belong to the essential constitution of the mobile terminal, and may be omitted entirely as needed within the scope not changing the essence of the invention.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output as sound when the mobile terminal 100 is in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the mobile terminal 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 may include a speaker, a buzzer, and the like.

The a/V input unit 104 is used to receive audio or video signals. The a/V input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, the Graphics processor 1041 Processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphic processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 can receive sounds (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, or the like, and can process such sounds into audio data. The processed audio (voice) data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 101 in case of the phone call mode. The microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the course of receiving and transmitting audio signals.

The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor that can adjust the brightness of the display panel 1061 according to the brightness of ambient light, and a proximity sensor that can turn off the display panel 1061 and/or a backlight when the mobile terminal 100 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the gesture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.

The display unit 106 is used to display information input by a user or information provided to the user. The Display unit 106 may include a Display panel 1061, and the Display panel 1061 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 107 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the mobile terminal. Specifically, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, can collect touch operations of a user (e.g., operations of a user on the touch panel 1071 or near the touch panel 1071 using a finger, a stylus, or any other suitable object or accessory) thereon or nearby and drive the corresponding connection device according to a predetermined program. The touch panel 1071 may include two parts of a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 110, and can receive and execute commands sent by the processor 110. In addition, the touch panel 1071 may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may include other input devices 1072. In particular, other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like, and are not limited to these specific examples.

Further, the touch panel 1071 may cover the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or nearby, the touch panel 1071 transmits the touch operation to the processor 110 to determine the type of the touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of the touch event. Although the touch panel 1071 and the display panel 1061 are shown in fig. 1 as two separate components to implement the input and output functions of the mobile terminal, in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated to implement the input and output functions of the mobile terminal, and is not limited herein.

The interface unit 108 serves as an interface through which at least one external device is connected to the mobile terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from external devices and transmit the received input to one or more elements within the mobile terminal 100 or may be used to transmit data between the mobile terminal 100 and external devices.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 109 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The processor 110 is a control center of the mobile terminal, connects various parts of the entire mobile terminal using various interfaces and lines, and performs various functions of the mobile terminal and processes data by operating or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby performing overall monitoring of the mobile terminal. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The mobile terminal 100 may further include a power supply 111 (e.g., a battery) for supplying power to various components, and preferably, the power supply 111 may be logically connected to the processor 110 via a power management system, so as to manage charging, discharging, and power consumption management functions via the power management system.

Although not shown in fig. 1, the mobile terminal 100 may further include a bluetooth module or the like, which is not described in detail herein.

In order to facilitate understanding of the embodiments of the present invention, a communication network system on which the mobile terminal of the present invention is based is described below.

Referring to fig. 2, fig. 2 is an architecture diagram of a communication Network system according to an embodiment of the present invention, the communication Network system is an LTE system of a universal mobile telecommunications technology, and the LTE system includes a UE (User Equipment) 201, an e-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an epc (Evolved Packet Core) 203, and an IP service 204 of an operator, which are in communication connection in sequence.

Specifically, the UE201 may be the terminal 100 described above, and is not described herein again.

The E-UTRAN202 includes eNodeB2021 and other eNodeBs 2022, among others. Among them, the eNodeB2021 may be connected with other eNodeB2022 through backhaul (e.g., X2 interface), the eNodeB2021 is connected to the EPC203, and the eNodeB2021 may provide the UE201 with access to the EPC 203.

The EPC203 may include an MME (Mobility Management Entity) 2031, an hss (Home Subscriber Server) 2032, other MMEs 2033, an SGW (Serving gateway) 2034, a pgw (PDN gateway) 2035, and a PCRF (Policy and Charging Rules Function) 2036, and the like. The MME2031 is a control node for processing signaling between the UE201 and the EPC203, and provides bearer and connection management. HSS2032 is used to provide registers to manage functions such as home location register (not shown) and holds subscriber specific information about service characteristics, data rates, etc. All user data may be sent through SGW2034, PGW2035 may provide IP address assignment for UE201 and other functions, and PCRF2036 is a policy and charging control policy decision point for traffic data flow and IP bearer resources, which selects and provides available policy and charging control decisions for a policy and charging enforcement function (not shown).

The IP services 204 may include the internet, intranets, IMS (IP Multimedia Subsystem), or other IP services, among others.

Although the LTE system is described as an example, it should be understood by those skilled in the art that the present invention is not limited to the LTE system, but may also be applied to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems.

Based on the above mobile terminal hardware structure and communication network system, the present invention provides various embodiments of the method.

First embodiment

In the high-pass mobile phone charging scheme, the charging-related signals comprise VBUS, D +, D-and GND signals, the charging speed is determined by the D + and D-signals, and the charging failure is generally caused by D + and D-line abnormity (such as short circuit, impedance abnormity, common-mode inductance abnormity and the like).

Fig. 3 is a schematic diagram of a charging circuit provided in this embodiment, the charging circuit is suitable for a terminal carrying a high-pass charging solution, and the charging circuit includes: a normal charging circuit 1 and a backup charging circuit 2; the normal charging circuit 1 consists of a USB female socket, a common mode inductor, a first switch circuit 101, a second switch circuit 102 and a charging management chip PMIC, wherein the common mode inductor, the first switch circuit 101, the second switch circuit 102 and the charging management chip PMIC are sequentially connected with a connecting line led out from a D + pin and a D-pin of the USB female socket; the standby charging circuit 1 consists of a VBUS contact, a timer and an inverter I0, one end of the VBUS contact is connected with the PMIC, the other end of the VBUS contact comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the first switch circuit 101, and the second branch circuit is sequentially connected with the timer, the inverter I0 and the second switch circuit 102; when the D + and D-pin paths of the USB female socket are abnormal, a low level is input to the VBUS contact through the VBUS pin of the USB male socket, the first switch circuit is disconnected, the second switch circuit is connected, and charging is carried out through the standby circuit.

It should be noted that the USB interface in fig. 3 adopts TYPE-C interface standard, the TYPE-C interface belongs to one of USB interfaces, and in practical application, USB interfaces of other standards can be adopted according to situations, for example, the USB interface can be changed into ase:Sub>A micro-USB interface, ase:Sub>A USB-ase:Sub>A interface, etc., in some embodiments, the USB interface can be replaced by another standard interface, only corresponding D-, D + and VBUS pins need to be provided in the interface, and the scheme provided by the embodiment of the present invention also belongs to the protection scope of the present invention.

As shown in fig. 3, the charging circuit of the present invention further includes a central processing unit, and the central processing unit is connected to the charging management chip PMIC. The PMIC is a power management unit, and a highly integrated power management scheme for portable applications is that a plurality of traditional discrete power management chips, such as a low dropout regulator (LDO) and a direct current/direct current converter (DC/DC), are integrated into a Power Management Unit (PMU) of a mobile phone at present, so that higher power conversion efficiency and lower power consumption can be realized, fewer components are required to adapt to a reduced board level space, and the cost is lower; the PMIC is used as a power management integrated unit matched with a specific main chip of consumer electronics (such as a mobile phone, an MP4, a GPS, a PDA and the like), can provide all power supplies with different voltages of multiple grades and different levels required by the main chip, and supplies energy with the same voltage to different mobile phone working units, an image processor, a radio frequency device, a camera module and the like, so that the units can work normally.

The PMIC of the charging management chip is generally bound and customized with the main chip, because the PMIC is matched with the power-on sequence of the CPU, and the power-on sequence of certain voltages and the time interval between the certain voltages have precedence relation and time requirement. This is well masked. A PMU is in fact a dedicated power controller with a masking procedure. 32.768KHZ crystals and 19.2M crystals the standby mode is 32.768KHZ crystals operating and the normal operation is 19.2M primary crystals operating. The PMIC enters a standby state after the battery is attached, the PMU is clocked by a 32.768KHZ crystal, after the POWER is triggered to start according to a POWER key, the corresponding LDO and DC-DC are turned on according to a customized starting sequence, the 19.2M main clock works, after the POWER supply of the CPU is normal, the output is set to the CPU, a reset signal is output to the CPU, the reset signal is released, and the CPU starts to start. The CPU outputs a PS _ HOLD signal to enable the PMIC to be in an operating state. (when the CPU is shut down, the PS _ HOLD is pulled down, the PMIC is shut down and enters a shutdown state) after the CPU works normally, each module of the PMIC can be controlled through the I2C interface. For example, when the system is frequency-converted, the core voltage is adjusted to a corresponding voltage at different operating frequencies. The setting of RTC time and the clock of ALARM. Meanwhile, the PMIC can generate an interrupt signal to the CPU when the abnormal event occurs, and the CPU then carries out interrupt processing.

As shown in fig. 3, the first switch circuit 101 is composed of two NMOS transistors, gates of the two NMOS transistors are connected to each other, sources of the two NMOS transistors are connected to the connection lines led out from the D + and D-pins of the USB socket, respectively, and drains of the two NMOS transistors are connected to the PMIC. The second switch circuit 102 is disposed between the first switch circuit 101 and the charging management chip PMIC, and the second switch circuit 102 is as close to the charging management chip PMIC as possible. The second switch circuit 102 is a PMOS transistor, a gate of the PMOS transistor is connected with the inverter I0 of the standby circuit, a source of the PMOS transistor is connected with a connection line led out from a D-pin of the USB female socket, and a drain of the PMOS transistor is connected with a connection line led out from a D + pin of the USB female socket.

The charging circuit in this embodiment is divided into a normal operating state and an abnormal operating state when operating. In a normal working state (namely, the mobile phone has no abnormality): VBUS inputs high potential or is suspended, the NMOS transistors N1 and N2 are started at the moment, the timer does not work and outputs low level, therefore, the inverter I0 outputs high potential to further close the PMOS transistor P1, the D + and D-paths are normal at the moment, and the charger can be inserted to charge according to normal high-pass logic; in an abnormal working state (namely when the mobile phone cannot be charged): when the D + and D-channels are abnormal, a low level is input at the VBUS position of the TYPE-C public seat, the low level can close the NMOS transistors N1 and N2, meanwhile, a timer is triggered to start timing (timing time can be set to be 2 hours or set according to actual conditions), the timer outputs a high level in the timing process, and therefore the inverter I0 outputs a low level to conduct the PMOS transistor P1, the conduction of the PMOS transistor means that D + and D-are directly short-circuited, and the timing period D + and D-of the timer are always in a short-circuit state, at the moment, if the charger is inserted again, charging is conducted according to the BC1.2 standard according to a high-pass charging logic, and when the timing of the timer is ended, an output signal is inverted, and therefore the charging is ended.

This embodiment (advantageous effect).

The present embodiment provides a charging circuit, including: a normal charging circuit and a standby charging circuit; the normal charging circuit consists of a USB female socket, a common mode inductor, a first switch circuit, a second switch circuit and a charging management chip PMIC, wherein the common mode inductor, the first switch circuit, the second switch circuit and the charging management chip PMIC are sequentially connected with a connecting line led out from a D + pin and a D-pin of the USB female socket; the standby charging circuit consists of a VBUS contact, a timer and an inverter I0, one end of the VBUS contact is connected with the PMIC, the other end of the VBUS contact comprises a first branch circuit and a second branch circuit, the first branch circuit is connected with the first switch circuit, and the second branch circuit is sequentially connected with the timer, the inverter I0 and the second switch circuit; when the D + and D-pin paths of the USB female socket are abnormal, a low level is input to the VBUS contact through the VBUS pin of the USB male socket, the first switch circuit is disconnected, the second switch circuit is connected, and charging is carried out through the standby circuit. When the normal charging circuit is abnormal and charging cannot be carried out, a low level is input into a VBUS contact of the standby charging circuit to enable the standby charging circuit to work, so that the mobile terminal is charged temporarily, a user can conveniently carry out data backup when the mobile terminal breaks down, and partial loss of the user can be recovered.

Second embodiment

Fig. 4 is a flowchart of a charging method according to a second embodiment of the present invention, where the charging method includes:

s401, when charging is started, a high potential is input or suspended at a VBUS contact of the standby charging circuit.

In this embodiment, the charging start refers to that a USB male connector on a charger is inserted into a USB female connector on a terminal, and signals related to charging in the high-pass mobile phone charging scheme include VBUS, D +, D-, and GND signals, so that pins of the VBUS, D +, D-, and GND signals are all present on the charger and the terminal supporting the high-pass charging scheme, and when the USB male connector on the charger is inserted into the USB female connector on the terminal, pins corresponding to the USB male connector and the USB female connector will contact with each other to perform signal detection and input of electric energy.

S402, detecting whether a D + connecting line and a D-connecting line in a normal charging circuit are normally conducted or not; when the D + and D-connection lines are normally conducted, the step S403 is carried out; when the D + and D-connection lines are not normally conducted, the process proceeds to step S404.

In the terminal adopting the high-pass charging protocol standard, the connection line of the D + pin and the connection line of the D-pin are used for charging as default standards, and the high-pass specifies the charging protocol, the charging interface and the corresponding pins, for example, the charging protocol of QC2.0, QC3.0 and QC4.0 definitely specifies that the charging interface must contain four pins including VBUS, D +, D and GND, so that the mutual compatibility of the charging interfaces among various protocols of the high-pass can be facilitated, and the universality and the adaptability of the terminal and the charger are enhanced.

And S403, when the D + and the D-connecting lines are normally conducted, a normal charging circuit is adopted to carry out charging under normal conditions.

The normal charging circuit is the charging circuit according to the design of the high-pass protocol standard that charges, and the high-pass protocol standard that charges is in order to satisfy the demand of filling soon now, adopts the more refined control strategy that charges, and the more refined control strategy that charges just requires the voltage gear and the electric current gear that the charging circuit can pass through to become more, and the charging circuit needs voltage and the electric current through more gears will lead to the rise of circuit design degree of difficulty and design cost, therefore normal charging circuit can only design a charging circuit in present terminal usually. This results in the terminal not being charged when the normal charging circuit in the terminal fails.

And S404, inputting a low level at a VBUS contact of the standby charging circuit when the D + and D-connecting lines are not normally conducted.

And S405, charging in an abnormal condition by adopting a standby charging circuit.

When the normal charging line of the terminal breaks down, the terminal cannot be charged, a consumer can generally send the terminal to an after-sale maintenance part corresponding to a brand for processing, the after-sale maintenance part can utilize a standby charging circuit of the terminal to temporarily charge the terminal, a user can conveniently perform data backup on data in the terminal after the terminal is started again, and the situation that personal data is leaked or the personal data is removed in the maintenance process due to the fact that the terminal breaks down is avoided.

The charging circuit used in the charging method in this embodiment may refer to the circuit in fig. 3, and the normal charging circuit in fig. 3 includes: the charging management circuit comprises a USB female socket comprising a D + pin and a D-pin, and a common mode inductor first switch circuit, a second switch circuit and a charging management chip PMIC which are sequentially connected through a D + connecting wire and a D-connecting wire; the first switch circuit is composed of two NMOS transistors with mutually connected grids, and the second open circuit is a PMOS transistor; the backup charging circuit includes: and a VBUS contact, wherein one end lead of the VBUS contact is connected with the PMIC, the first branch at the other end is connected with the grid electrode of the first switch circuit, and the second branch is connected with the timer and the reverser I0 at one time and is connected with the grid electrode of the second switch.

In this embodiment, in the normal charging, a VBUS contact of the standby charging circuit inputs a high potential or is floating, the two NMOS transistors of the first switch circuit are turned on, the timer does not operate and the merchant is at a low level, so that the timer I0 outputs a high potential, thereby turning off the PMOS transistor of the second switch circuit, and at this time, the D + and D-connection line paths of the normal charging circuit are normal.

When the access of the D + and D-connecting lines of the normal charging circuit is abnormal, a low level is input into a VBUS contact of the standby charging circuit, the timer starts to work to time and outputs a high level, so that the timer I0 outputs a low level, the PMOS transistor of the second switching circuit is conducted, the two NMOS transistors of the first switching circuit are short-circuited, the second switching circuit is turned off, and the standby circuit is used for charging. Because the embodiment of the invention adopts the high-pass charging standard protocol, when the charging method adopts the standby circuit for charging, the charging is carried out according to the BC1.2 standard. In the charging under the abnormal condition, the timer needs to output high potential to enable the two NMOS transistors in the first switch circuit to be short-circuited and simultaneously to conduct the PMOS transistor of the second switch circuit, so that the set time of the timer determines the service time of the standby charging point circuit, and the set time of the timer can be set according to actual conditions.

This embodiment (advantageous effects).

The embodiment provides a charging method, which comprises the following steps: charging under normal conditions and charging under abnormal conditions; a VBUS contact of the standby charging circuit is input with a high potential or is suspended, a D + connecting wire and a D-connecting wire of the normal charging circuit are normally conducted, and the normal charging circuit is adopted for charging under normal conditions; when the D + of the normal charging circuit and the path of the D-connecting line are abnormal, a low level is input into a VBUS contact of the standby charging circuit, and the standby charging circuit is adopted to carry out charging under the abnormal condition. Through setting up a normal charging circuit and a reserve charging circuit, when normal charging circuit breaks down, adopt reserve charging circuit to carry out interim charging for the terminal to guaranteed that the user has the personal data on the backup terminal that can be timely under the circumstances that the terminal breaks down, avoided because the loss of user's guest data that the terminal fault leads to in the maintenance process.

Third embodiment

The present embodiment also provides a terminal, which, referring to fig. 5, comprises a battery 51 and a charging circuit 52 embodying the proposed charging circuit, wherein the battery 51 is charged by the charging circuit 52.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A charging circuit adapted for use with a terminal carrying a high-pass charging solution, the charging circuit comprising: a normal charging circuit and a standby charging circuit;

the normal charging circuit consists of a USB female socket, a common mode inductor, a first switch circuit, a second switch circuit and a charging management chip PMIC, wherein the common mode inductor, the first switch circuit, the second switch circuit and the charging management chip PMIC are sequentially connected with a connecting line led out from a D + pin and a D-pin of the USB female socket;

when the D + and D-pin paths of the USB female socket are abnormal, a low level is input to the VBUS contact through the VBUS pin of the USB male socket, the first switch circuit is switched off, the second switch circuit is switched on, and charging is carried out through the standby charging circuit.

2. The charging circuit of claim 1, further comprising: and the central processing unit is connected with the charging management chip PMIC.

3. The charging circuit of claim 1, wherein the first switch circuit is composed of two NMOS transistors, gates of the two NMOS transistors are connected to each other, sources of the two NMOS transistors are connected to the connection lines led out from the D + and D-pins of the USB socket, respectively, and drains of the two NMOS transistors are connected to a PMIC of a charging management chip.

4. The charging circuit of claim 1, wherein the second switching circuit is disposed between the first switching circuit and the charge management chip PMIC, and the second switching circuit is proximate to the charge management chip PMIC.

5. The charging circuit according to claim 4, wherein the second switch circuit is a PMOS transistor, a gate of the PMOS transistor is connected to the inverter I0 of the backup charging circuit, a source of the PMOS transistor is connected to a connection line led out from the D-pin of the USB socket, and a drain of the PMOS transistor is connected to a connection line led out from the D + pin of the USB socket.

6. A charging method is suitable for a terminal carrying a high-pass charging solution, and is characterized by comprising the following steps: charging under normal conditions and charging under abnormal conditions;

a VBUS contact of the standby charging circuit is input with a high potential or is suspended, a D + connecting wire and a D-connecting wire of the normal charging circuit are normally conducted, and the normal charging circuit is adopted for charging under normal conditions;

when the paths of the D + and D-connecting lines of the normal charging circuit are abnormal, a VBUS contact of the standby charging circuit inputs a low level, and the standby charging circuit is adopted to charge under the abnormal condition;

the normal charging circuit includes: the USB socket comprises a D + pin and a D-pin, and a common mode inductor, a first switch circuit, a second switch circuit and a charging management chip PMIC which are sequentially connected through a D + connecting wire and a D-connecting wire; the first switch circuit is composed of two NMOS transistors with mutually connected grids, and the second switch circuit is a PMOS transistor;

the backup charging circuit includes: and a VBUS contact, wherein a lead at one end of the VBUS contact is connected with the PMIC, a first branch at the other end of the VBUS contact is connected with a grid electrode of the first switch circuit, and a second branch is connected with a timer and an inverter I0 at a time and is connected with a grid electrode of the second switch.

7. The charging method of claim 6, wherein in normal charging, the VBUS contact of the backup charging circuit is input high or floating, the two NMOS transistors of the first switching circuit are turned on, the timer is not operated and is at low level, so that the timer I0 outputs high, thereby turning off the PMOS transistor of the second switching circuit, when the D + and D-connection paths of the normal charging circuit are normal.

8. The charging method as claimed in claim 6, wherein when the path of the D + and D-connection lines of the normal charging circuit is abnormal, a low level is inputted to the VBUS contact of the standby charging circuit, the timer starts to operate to time and output a high level, so that the timer I0 outputs a low level, the PMOS transistor of the second switching circuit is turned on, so that the two NMOS transistors of the first switching circuit are short-circuited, thereby turning off the second switching circuit, and the standby charging is performed using the standby circuit.

9. A terminal, characterized in that the terminal comprises a battery and a charging circuit according to any of claims 1-5, the battery being charged by the charging circuit.