CN109192152B

CN109192152B - LCD control circuit and terminal

Info

Publication number: CN109192152B
Application number: CN201810995822.6A
Authority: CN
Inventors: 蒋权
Original assignee: Nubia Technology Co Ltd
Current assignee: Nubia Technology Co Ltd
Priority date: 2018-08-29
Filing date: 2018-08-29
Publication date: 2021-01-01
Anticipated expiration: 2038-08-29
Also published as: CN109192152A

Abstract

An LCD control circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit; the logic judgment circuit comprises a first input end, a second input end and an output end; the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit; the output end of the LCD panel is connected with the input end of the high-level holding circuit; the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit; the input end of the execution circuit is connected with the output end of the logic judgment circuit, and the output end of the execution circuit is connected with the input end of the LCD panel. In addition, the embodiment of the invention also provides a terminal.

Description

LCD control circuit and terminal

Technical Field

The invention relates to the field of Liquid Crystal Display (LCD) control, in particular to an LCD control circuit and a terminal.

Background

There are two main types of Liquid Crystal Displays (LCD) on the market, one is an Organic Light-Emitting Diode (OLED) LCD, and the other is a Thin Film Transistor (TFT) LCD. The OLED LCD is a self-luminous LCD, and does not need an additional backlight source, while the TFT LCD needs an additional backlight source. In the TFT LCD display technology, in order to reduce power consumption of a Backlight Light Emitting Diode (LED), a Content Adaptive Backlight Control (CABC) technology is introduced, that is, Backlight brightness is adjusted according to the Content of an image. In the existing TFT LCD display scheme, when a user causes LCD black screen due to Electro-Static discharge (ESD) problem during the use process, the situation needs to manually press a power key twice to restore normal display, or if the ESD restoration function is integrated by software, the state of the LCD is detected every 5s, data is transmitted through a Mobile Industrial Processor Interface (MIPI) of the LCD, the function is effective only when the software is normally opened, but the phenomenon that the LCD display is stuck due to the fact that the function normally opens occupies MIPI resource of the LCD is required.

Disclosure of Invention

The invention mainly aims to provide an LCD control circuit which can automatically restart an LCD and has low system power consumption, and aims to solve the existing problems.

To achieve the above object, the present invention provides an LCD control circuit, comprising: the circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit; the logic judgment circuit comprises a first input end, a second input end and an output end; the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit; the output end of the LCD panel is connected with the input end of the high-level holding circuit; the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit; the input end of the execution circuit is connected with the output end of the logic judgment circuit, and the output end of the execution circuit is connected with the input end of the LCD panel.

In the above solution, the LCD control circuit further includes a rectifying diode located between the input terminal of the high level holding circuit and the output terminal of the LCD panel; the anode of the rectifier diode is connected with the output end of the LCD panel; and the cathode of the rectifier diode is connected with the input end of the high-level holding circuit.

In the above scheme, the high-level holding circuit includes a voltage holding capacitor, one end of the voltage holding capacitor is connected to the output end of the LCD panel, and the other end of the voltage holding capacitor is connected to ground.

In the above scheme, the high-level holding circuit further includes a discharge resistor, and the discharge resistor is connected in parallel with the voltage holding capacitor.

In the above scheme, the execution circuit includes a processor, a first input/output port of the processor is connected to the output terminal of the logic determination circuit, and a second input/output port of the processor is connected to the input terminal of the LCD panel.

In the above scheme, the execution circuit includes a power management unit, an input end of the power management unit is connected to an output end of the logic judgment circuit, and an output end of the power management unit is connected to an input end of the LCD panel.

In the above scheme, the execution circuit includes a power management unit and a processor; the input end of the power management unit is connected with the output end of the logic judgment circuit, the output end of the power management unit is connected with the first input/output port of the processor, and the second input/output port of the processor is connected with the input end of the LCD panel.

In the above scheme, the oscillation circuit includes a power management interface unit, and an output end of the power management interface unit is connected to the second input end of the logic judgment circuit.

In the above scheme, the logic judgment circuit is an or gate.

In addition, to achieve the above object, the present invention provides a terminal including an LCD control circuit, the LCD control circuit including: the circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit; the logic judgment circuit comprises a first input end, a second input end and an output end; the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit; the output end of the LCD panel is connected with the input end of the high-level holding circuit; the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit; the input end of the execution circuit is connected with the output end of the logic judgment circuit, and the output end of the execution circuit is connected with the input end of the LCD panel.

In the above scheme, the logic judgment circuit is an or gate.

Therefore, compared with the prior art, an embodiment of the present invention provides an LCD control circuit and a terminal, including: the circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit; the logic judgment circuit comprises a first input end and a second input end; the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit; the output end of the LCD panel is connected with the input end of the high-level holding circuit; the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit; the input end of the execution circuit is connected with the output end of the logic judgment circuit, the output end of the execution circuit is connected with the input end of the LCD panel, and therefore, the high level of the level signal of the LCD panel is kept and the level signal and the signal of the oscillation circuit are jointly logically judged, automatic restarting of the LCD is achieved according to a logic judgment result, system resources are saved, the performance of the LCD is guaranteed, system power consumption is reduced, and user experience is improved.

Drawings

Fig. 1 is a schematic diagram of a hardware structure of a terminal including an LCD control circuit, which is optional in implementing various embodiments of the present invention;

FIG. 2 is a schematic diagram of a wireless communication system of the terminal shown in FIG. 1 including an LCD control circuit;

FIG. 3 is a circuit diagram of an LCD control circuit according to an alternative embodiment of the present invention;

FIG. 4 is a circuit diagram of an LCD control circuit according to an alternative embodiment of the present invention;

FIG. 5 is a circuit diagram of an LCD control circuit according to an alternative embodiment of the present invention;

FIG. 6 is a circuit diagram of an LCD control circuit according to an alternative embodiment of the present invention;

FIG. 7 is a detailed circuit diagram of an LCD control circuit according to an alternative embodiment of the present invention.

Reference numerals:

the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.

The terminal may be implemented in various forms. For example, the terminal described in the present invention may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and a fixed terminal such as a Digital TV, a desktop computer, and the like.

The following description will be given by way of example of a mobile terminal, and it will be understood by those skilled in the art that the construction according to the embodiment of the present invention can be applied to a fixed type terminal, in addition to elements particularly used for mobile purposes.

Referring to fig. 1, which is a schematic diagram of a hardware structure of a mobile terminal for implementing various embodiments of the present invention, the mobile terminal 100 may include: RF (Radio Frequency) unit 101, WiFi module 102, audio output unit 103, a/V (audio/video) input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, processor 110, and power supply 111. Those skilled in the art will appreciate that the mobile terminal architecture shown in fig. 1 is not intended to be limiting of mobile terminals, which may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

The following describes each component of the mobile terminal in detail with reference to fig. 1:

the radio frequency unit 101 may be configured to receive and transmit signals during information transmission and reception or during a call, and specifically, receive downlink information of a base station and then process the downlink information to the processor 110; in addition, the uplink data is transmitted to the base station. Typically, radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with a network and other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to GSM (Global System for Mobile communications), GPRS (General Packet Radio Service), CDMA2000(Code Division Multiple Access2000 ), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division duplex Long Term Evolution), and TDD-LTE (Time Division duplex Long Term Evolution).

WiFi belongs to short-distance wireless transmission technology, and the mobile terminal can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 102, and provides wireless broadband internet access for the user. Although fig. 1 shows the WiFi module 102, it is understood that it does not belong to the essential constitution of the mobile terminal, and may be omitted entirely as needed within the scope not changing the essence of the invention.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output as sound when the mobile terminal 100 is in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the mobile terminal 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 may include a speaker, a buzzer, and the like.

The a/V input unit 104 is used to receive audio or video signals. The a/V input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, the Graphics processor 1041 Processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphic processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 may receive sounds (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, or the like, and may be capable of processing such sounds into audio data. The processed audio (voice) data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 101 in case of a phone call mode. The microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the course of receiving and transmitting audio signals.

The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor that can adjust the brightness of the display panel 1061 according to the brightness of ambient light, and a proximity sensor that can turn off the display panel 1061 and/or a backlight when the mobile terminal 100 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.

The display unit 106 is used to display information input by a user or information provided to the user. The Display unit 106 may include a Display panel 1061, and the Display panel 1061 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 107 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the mobile terminal. Specifically, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, may collect a touch operation performed by a user on or near the touch panel 1071 (e.g., an operation performed by the user on or near the touch panel 1071 using a finger, a stylus, or any other suitable object or accessory), and drive a corresponding connection device according to a predetermined program. The touch panel 1071 may include two parts of a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 110, and can receive and execute commands sent by the processor 110. In addition, the touch panel 1071 may be implemented in various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may include other input devices 1072. In particular, other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like, and are not limited to these specific examples.

Further, the touch panel 1071 may cover the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or nearby, the touch panel 1071 transmits the touch operation to the processor 110 to determine the type of the touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of the touch event. Although the touch panel 1071 and the display panel 1061 are shown in fig. 1 as two separate components to implement the input and output functions of the mobile terminal, in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated to implement the input and output functions of the mobile terminal, and is not limited herein.

The interface unit 108 serves as an interface through which at least one external device is connected to the mobile terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from external devices and transmit the received input to one or more elements within the mobile terminal 100 or may be used to transmit data between the mobile terminal 100 and external devices.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 109 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The processor 110 is a control center of the mobile terminal, connects various parts of the entire mobile terminal using various interfaces and lines, and performs various functions of the mobile terminal and processes data by operating or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby performing overall monitoring of the mobile terminal. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The mobile terminal 100 may further include a power supply 111 (e.g., a battery) for supplying power to various components, and preferably, the power supply 111 may be logically connected to the processor 110 via a power management system, so as to manage charging, discharging, and power consumption management functions via the power management system.

Although not shown in fig. 1, the mobile terminal 100 may further include a bluetooth module or the like, which is not described in detail herein.

In order to facilitate understanding of the embodiments of the present invention, a communication network system on which the mobile terminal of the present invention is based is described below.

Referring to fig. 2, fig. 2 is an architecture diagram of a communication Network system according to an embodiment of the present invention, where the communication Network system is an LTE system of a universal mobile telecommunications technology, and the LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203, and an IP service 204 of an operator, which are in communication connection in sequence.

Specifically, the UE201 may be the terminal 100 described above, and is not described herein again.

The E-UTRAN202 includes eNodeB2021 and other eNodeBs 2022, among others. Among them, the eNodeB2021 may be connected with other eNodeB2022 through backhaul (e.g., X2 interface), the eNodeB2021 is connected to the EPC203, and the eNodeB2021 may provide the UE201 access to the EPC 203.

The EPC203 may include an MME (Mobility Management Entity) 2031, an HSS (Home Subscriber Server) 2032, other MMEs 2033, an SGW (Serving GateWay) 2034, a PGW (PDN GateWay) 2035, and a PCRF (Policy and Charging Rules Function) 2036, and the like. The MME2031 is a control node that handles signaling between the UE201 and the EPC203, and provides bearer and connection management. HSS2032 is used to provide registers to manage functions such as home location register (not shown) and holds subscriber specific information about service characteristics, data rates, etc. All user data may be sent through SGW2034, PGW2035 may provide IP address assignment for UE201 and other functions, and PCRF2036 is a policy and charging control policy decision point for traffic data flow and IP bearer resources, which selects and provides available policy and charging control decisions for a policy and charging enforcement function (not shown).

The IP services 204 may include the internet, intranets, IMS (IP Multimedia Subsystem), or other IP services, among others.

Although the LTE system is described as an example, it should be understood by those skilled in the art that the present invention is not limited to the LTE system, but may also be applied to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems.

Based on the above mobile terminal hardware structure and communication network system, the present invention provides various embodiments of the method.

Referring to fig. 3, an embodiment of the invention provides an LCD control circuit, including: a logic determination circuit 301, a high-level holding circuit 302, an LCD panel 303, an oscillation circuit 304, and an execution circuit 305; the logic judgment circuit 301 comprises a first input end, a second input end and an output end; the output end of the high-level holding circuit 302 is connected with the first input end of the logic judgment circuit 301; the output end of the LCD panel 303 is connected with the input end of the high-level holding circuit 302; the output end of the oscillating circuit 304 is connected with the second input end of the logic judgment circuit 301; the input end of the execution circuit 305 is connected to the output end of the logic judgment circuit 301, and the output end of the execution circuit 305 is connected to the input end of the LCD panel 303. Specifically, the LCD panel 303 may be an LCD, and may also be a circuit including an LCD for receiving or transmitting an electrical signal to or from an external device. The high level holding circuit 302 is configured to hold a received high level signal output by the LCD panel 303 to a high level for a specific time, which may be 5ms, 10ms, 20ms, or the like, and send the high level signal to the logic determining circuit 301. The oscillation circuit may include a sine wave oscillation circuit outputting a sine wave or a cosine wave, or may include a non-sine wave oscillation circuit outputting a square wave, a rectangular wave, or a sawtooth wave. The oscillation circuit 304 may include a quartz crystal oscillation circuit, an LC oscillation circuit, or an RC oscillation circuit. Optionally, the output of the oscillation circuit is a Pulse Width Modulation (PWM) signal, the frequency may be 10Hz, 50Hz, or 100Hz, the corresponding period may be 100ms, 20ms, or 10ms, and the duty ratio may be 10%, 20%, or 50%, and in practical applications, the frequency, the period, and the duty ratio of the oscillation circuit may be set accordingly according to actual situations. The logic judgment circuit can comprise an OR gate, a NOR gate, an AND gate or a NAND gate. If an or gate is used, a first input terminal of the or gate is connected to the output terminal of the high level holding circuit 302, a second input terminal of the or gate is connected to the output terminal of the oscillating circuit 304, and an output terminal of the or gate is connected to the input terminal of the execution circuit 305; when the high-level holding circuit 302 outputs a high level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the or gate outputs a high-level signal; when the oscillation circuit 304 outputs the PWM signal while the high-level holding circuit 302 outputs the low level, the output terminal of the or gate outputs the PWM signal. If a nor gate is used, a first input terminal of the nor gate is connected to the output terminal of the high level holding circuit 302, a second input terminal of the nor gate is connected to the output terminal of the oscillating circuit 304, and an output terminal of the nor gate is connected to the input terminal of the execution circuit 305; when the high-level holding circuit 302 outputs a high level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the nor gate outputs a low-level signal; when the high holding circuit 302 outputs a low level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the nor gate outputs the PWM signal. If an and gate is adopted, a first input end of the and gate is connected with the output end of the high level holding circuit 302, a second input end of the and gate is connected with the output end of the oscillating circuit 304, and an output end of the and gate is connected with the input end of the execution circuit 305; when the high level holding circuit 302 outputs a high level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the and gate outputs the PWM signal; when the high holding circuit 302 outputs a low level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the and gate outputs a low level signal. If a nand gate is adopted, a first input end of the nand gate is connected with the output end of the high-level holding circuit 302, a second input end of the nand gate is connected with the output end of the oscillating circuit 304, and an output end of the nand gate is connected with the input end of the execution circuit 305; when the high level holding circuit 302 outputs a high level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the nand gate outputs the PWM signal; when the high-level holding circuit 302 outputs a low level and the oscillation circuit 304 outputs a PWM signal, the output terminal of the nand gate outputs a high-level signal. The execution circuit 305 may control the power of the LCD panel 303 to be turned on or off according to the electric signal output from the logic determination circuit 301. Therefore, the high level of the level signal of the LCD panel 303 is kept, the level signal and the signal of the oscillating circuit 304 are logically judged together, automatic restarting of the LCD is achieved according to a logical judgment result, system resources are saved, the performance of the LCD is guaranteed, the power consumption of a system is reduced, and user experience is improved.

Here, referring to fig. 4, the LCD control circuit further includes a rectifying diode D1 between the input terminal of the high level holding circuit 302 and the output terminal of the LCD panel 303; the anode of the rectifying diode D1 is connected to the output end of the LCD panel 303; the cathode of the rectifier diode D1 is connected to the input of the high-level holding circuit 302. Specifically, the rectifier diode D1 is used to limit the current flowing direction between the LCD panel 303 and the high-level holding circuit 302, so that current can only flow from the LCD panel 303 to the high-level holding circuit 302, and the current at the input terminal of the high-level holding circuit 302 is prevented from affecting the level of the output terminal of the LCD panel 303. Alternatively, since the low dropout diode is a low power consumption, ultra high speed semiconductor device, and the most significant characteristic is that the reverse recovery time is extremely short, the rectifying diode D1 can be selected as a low dropout diode with a voltage drop not exceeding 0.3V, such as a schottky diode and a germanium diode.

Here, referring to fig. 5, the high-level holding circuit 302 includes a voltage holding capacitor C1, and one end of the voltage holding capacitor C1 is connected to the output terminal of the LCD panel 303, and the other end is connected to ground GND. Specifically, the voltage holding capacitor C1 is charged when the output terminal of the LCD panel 303 outputs a high level, so that the level of the connection point of the voltage holding capacitor C1 and the LCD panel 303 is a high level; when the output terminal of the LCD panel 303 outputs a low level, the discharge is performed so that the level of the connection point between the voltage holding capacitor C1 and the LCD panel 303 changes from a high level to a low level. If the high level output from the output terminal of the LCD panel 303 is 1.8V, in order to enable the voltage holding capacitor C1 to be still in the high level state when the low level is output from the output terminal of the LCD panel 303, the voltage holding capacitor C1 needs to be kept above 0.9V for a certain time, where the 0.9V is the high level threshold voltage of the system, the certain time may be 5ms, 10ms, or 20ms, etc., and when the low level is continuously input from the output terminal of the LCD panel 303, the voltage holding capacitor C1 needs to fall below 0.2V for 2s, and the 0.2V is the low level threshold voltage of the system. The aforementioned 1.8V, 0.9V, 2s and 0.2V are all examples of the switching of the operating state of the voltage holding capacitor C1, and are not used to specifically define the operating parameters of the voltage holding capacitor C1, and the operating parameters of the voltage holding capacitor C1 may be selected accordingly according to actual conditions. By the provision of the voltage holding capacitor C1, high-level holding of the connection point of the voltage holding capacitor C1 and the LCD panel 303 is realized.

Here, referring to fig. 6, the high-level holding circuit 302 further includes a discharge resistor R1, and the discharge resistor R1 is connected in parallel with the voltage holding capacitor C1. Specifically, one end of the discharge resistor R1 is connected to the output terminal of the LCD panel 303, and the other end is connected to ground GND. The discharge resistor R1 is connected in parallel with the voltage holding capacitor C1, and when the output end of the LCD panel 303 outputs a high level, the voltage holding capacitor C1 is charged; when the output end of the LCD panel 303 outputs a low level, the voltage holding capacitor C1 discharges through the discharge resistor R1, the discharge resistor R1 and the voltage holding capacitor C1 work together, and it is guaranteed that when the output end of the LCD panel 303 continuously inputs the low level, the voltage holding capacitor C1 discharges through the discharge resistor R1 to drop below 0.2V within 2s, and the 0.2V is the low level threshold voltage of the system. The aforementioned 2s and 0.2V are examples of the switching of the operating state of the voltage holding capacitor C1 when the voltage holding capacitor C1 works together with the discharge resistor R1, and are not used to specifically limit the operating parameters of the discharge resistor R1 and the voltage holding capacitor C1, and the operating parameters of the discharge resistor R1 and the voltage holding capacitor C1 may be selected accordingly according to actual situations. By setting the discharge resistor R1, the discharge of the electric quantity of the voltage holding capacitor C1 is realized, and the level change of the connection point of the voltage holding capacitor C1 and the LCD panel 303 is realized.

Here, the execution circuit 305 includes a processor, a first input/output port of which is connected to the output terminal of the logic determination circuit 301, and a second input/output port of which is connected to the input terminal of the LCD panel 303. In particular, the processor may be an integrated circuit chip having signal processing capabilities. The processor executes a corresponding program according to the signal sent by the logic judgment circuit 301, and controls the on and off of the LCD panel 303, so as to realize the power-on and power-off of the LCD panel 303. Alternatively, the Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components. Here, the program executed by the processor may be stored in a memory connected to the processor through a bus, and the memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced Synchronous Dynamic Random Access Memory), Synchronous linked Dynamic Random Access Memory (DRAM, Synchronous Link Dynamic Random Access Memory), Direct Memory (DRmb Random Access Memory). The described memory for embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory. The memory in embodiments of the present invention is used to store various types of data to support the operation of the processor. Examples of such data include: any computer program for operation by the processor, such as operating systems and application programs; contact data; telephone book data; a message; a picture; video, etc. The operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is used for implementing various basic services and processing hardware-based tasks.

Here, the execution circuit 305 includes a power management unit, an input terminal of which is connected to the output terminal of the logic judgment circuit 301, and an output terminal of which is connected to the input terminal of the LCD panel 303. Specifically, the Power Management unit (PM) may be a Power Management chip, which implements input and output Power Management, controls connection and disconnection between the LCD panel 303 and the Power supply of the LCD panel 303, and an input end of the Power Management unit is connected to an output end of the logic determination circuit 301, receives an electrical signal sent by the logic determination circuit 301, and connects and disconnects the Power supply of the LCD panel 303 according to the electrical signal, thereby implementing Power-on and Power-off of the LCD panel 303.

Here, the execution circuit 305 includes a power management unit and a processor; the input end of the power management unit is connected with the output end of the logic judgment circuit 301, the output end of the power management unit is connected with the first input/output port of the processor, and the second input/output port of the processor is connected with the input end of the LCD panel 303. Specifically, the power management unit receives the electrical signal sent by the logic determination circuit 301, and forwards or processes the electrical signal sent by the logic determination circuit 301 and sends the electrical signal to the processor, and the processor receives the electrical signal sent by the power management unit and turns on or off the power supply of the LCD panel 303 according to the electrical signal sent by the power management unit, thereby implementing power-on and power-off of the LCD panel 303.

Here, the oscillation circuit 304 includes a power management interface unit, an output terminal of which is connected to a second input terminal of the logic judgment circuit 301. Specifically, the Power Management Interface unit (PMI) may be a Power Management chip, which implements Input/Output Power Management to provide a backlight voltage of the LCD panel 303 and a bias voltage of the LCD panel 303, the Power Management Interface unit has a General Purpose Input/Output Interface (GPIO), and may Output a PWM signal through the GPIO, where the frequency may be 10Hz, 50Hz, or 100Hz, the corresponding period may be 100ms, 20ms, or 10ms, and the duty ratio may be 10%, 20%, or 50%, and in actual application, the frequency, the period, and the duty ratio of the oscillation circuit may be set accordingly according to an actual situation.

Here, the logic determination circuit 301 is an or gate. Specifically, the logic judgment circuit 301 is a two-input or gate, one input terminal of the or gate is connected to the output terminal of the high-level holding circuit 302, the other input terminal of the or gate is connected to the output terminal of the oscillation circuit 304, and the output terminal of the or gate is connected to the input terminal of the execution circuit 305, so that a high-level signal is output when the output of any one of the high-level holding circuit 302 and the oscillation circuit 304 is high, and a low-level signal is output when the outputs of both the high-level holding circuit 302 and the oscillation circuit 304 are low.

Therefore, the high level of the level signal of the LCD panel 303 is kept, the level signal and the signal of the oscillating circuit 304 are logically judged together, automatic restarting of the LCD is achieved according to a logical judgment result, system resources are saved, the performance of the LCD is guaranteed, the power consumption of a system is reduced, and user experience is improved.

The present invention further provides a terminal, including an LCD control circuit, where the LCD control circuit includes: the circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit; the logic judgment circuit comprises a first input end, a second input end and an output end; the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit; the output end of the LCD panel is connected with the input end of the high-level holding circuit; the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit; the input end of the execution circuit is connected with the output end of the logic judgment circuit, and the output end of the execution circuit is connected with the input end of the LCD panel.

Here, the LCD control circuit further includes a rectifying diode between the input terminal of the high level holding circuit and the output terminal of the LCD panel; the anode of the rectifier diode is connected with the output end of the LCD panel; and the cathode of the rectifier diode is connected with the input end of the high-level holding circuit.

Here, the high level holding circuit includes a voltage holding capacitor having one end connected to an output terminal of the LCD panel and the other end connected to ground.

Here, the high-level holding circuit further includes a discharge resistor connected in parallel with the voltage holding capacitor.

Here, the execution circuit includes a processor, a first input/output port of the processor is connected to the output terminal of the logic determination circuit, and a second input/output port of the processor is connected to the input terminal of the LCD panel.

Here, the execution circuit includes a power management unit, an input terminal of the power management unit is connected to an output terminal of the logic judgment circuit, and an output terminal of the power management unit is connected to an input terminal of the LCD panel.

Here, the execution circuit includes a power management unit and a processor; the input end of the power management unit is connected with the output end of the logic judgment circuit, the output end of the power management unit is connected with the first input/output port of the processor, and the second input/output port of the processor is connected with the input end of the LCD panel.

Here, the oscillation circuit includes a power management interface unit, and an output terminal of the power management interface unit is connected to the second input terminal of the logic determination circuit.

Here, the logic determination circuit is an or gate.

In order to facilitate the understanding of the technical solution of the present invention, the following description is made with an alternative embodiment:

referring to FIG. 7, the CPU is a Central Processing Unit (Central Processing Unit), MIPI _ DSI0_ CLK _ P/N is the display serial interface clock pin No. 0 of the Mobile industry processor interface, MIPI _ DSI0_ LANE1_ P/N is the display serial interface channel No. 0 of the Mobile industry processor interface, MIPI _ DSI0_ LANE2_ P/N is the display serial interface channel No. 0 of the Mobile industry processor interface, MIPI _ DSI0_ LANE3_ P/N is the display serial interface channel No. 0 of the Mobile industry processor interface, MIPI _ DSI1_ CLK _ P/N is the display serial interface pin No. 1 of the Mobile industry processor interface, MIPI _ DSI1_ LANE1_ P/N is the display serial interface channel pin No. 1 of the Mobile industry processor interface, MIPI _ DSI1_ LANE2 is the display serial interface channel pin No. 1/P of the Mobile industry processor interface The MIPI _ DSI1_ LANE3_ P/N is the No. 1 display serial interface channel No. 3 pin of the mobile industry processor interface, GPIO _6 is the No. 6 general purpose input/output interface, GPIO _10 is the No. 10 general purpose input/output interface; k1 is a switch, the power key is closed, the active Low pin PWR _ KY _ N is connected to ground, the LDO is a Low Dropout Regulator pin (Low drop out Regulator); VDISP _ P _ OUT is a positive bias voltage output, VDISP _ M _ OUT is a negative bias voltage output, White LED driver is White LED drive, VREG _ WLED is a regulated power supply output, WLED _ SINK1 is the 1 st communication pin, WLED _ SINK2 is the 2 nd communication pin, WLED _ SINK3 is the 3 rd communication pin, WLED _ SINK4 is the 4 th communication pin; the displayon connector is a display interface, RST is reset, TE is frame synchronization feedback (framing Effect), IO is an input/output pin, VSP is a positive bias voltage, VSN is a negative bias voltage, and LCD WLED is a white LED of the LCD.

When a power supply exists and the LCD control circuit is not electrified, the PMI GPIO power supply always outputs 1.8V voltage, namely high level; when the LCD control circuit is powered on, the PMI GPIO outputs a PWM signal, the frequency of the PWM signal is 100Hz, the period of the PWM signal is 10ms, and the duty ratio of the PWM signal is 50%.

When the LCD displays normally, the CABC base pin of the LCD panel outputs a PWM signal with the frequency of 60Hz and the period of 16.67ms according to the display content, and the corresponding LCD display refresh rate is 60 Hz; when the PWM signal output by the LCD panel CABC is at a high level in a single period, the rectifier diode D1 is turned on to charge the voltage holding capacitor C1, so the high level signal and the signal output by the pin GPIO of the PMI are processed by the or gate X and output as a high level H1, the PWR _ KY _ N of the PM receives the high level signal, and since the PWR _ KY _ N is a power key and the low level is active, no key event occurs; when the PWM signal output by the LCD panel CABC is at a low level in a single period, the rectifier diode D1 is turned off, the voltage holding capacitor C1 holds the voltage due to the existence of the charge, so that the CABC signal is still at a high level after passing through the unidirectional conducting diode and the capacitor during normal operation, the high level signal and the PMI GPIO signal are processed by the or gate X and then output as a high level H1, the PWR _ KY _ N of the PM receives the high level signal, and no key event occurs because the PWR _ KY _ N is a power key and the low level is active.

When the LCD abnormally displays a black screen, the CABC pin output of the LCD panel is changed into a low level, at the moment, the rectifier diode D1 is cut off, and the voltage holding capacitor C1 holds the voltage because of the existence of the electric charges; the energy stored in the voltage holding capacitor C1 is slowly discharged through the discharging resistor R1 as time increases, and the level at the connection point of the rectifier diode D1 and the voltage holding capacitor C1 becomes a low level L1, which is classified into the following two cases according to the level of the PWM signal output from the pin GPIO of the PMI:

in the first situation, if the PWM signal output by the pin GPIO of the PMI is a low level signal in a single period, and is output as a low level after being processed by the or gate X with the low level L1, the pin PWR _ KY _ N of the PM receives the low level signal, a power key event is generated, the LCD control circuit enters a sleep state, and the LCD power timing enters a power-off timing; after time T0 (the period of the PWM signal output from the pin GPIO of the PMI is 10ms, and the duty ratio is 50%, so T0 is less than 5ms), the PWM signal output from the pin GPIO of the PMI is inverted to a high level, so that the PWM signal is processed by an or gate X with a low level L1 and then output to a high level, the pin PWR _ KY _ N of the PM receives the high level signal, and the power key event is released; after time T1 (the period of the PWM signal output by the pin GPIO of the PMI is 10ms, the duty ratio is 50%, so T1 is equal to 5ms), the PWM signal output by the pin GPIO of the PMI is inverted to low level, so the PWM signal is output to low level after being processed by an OR gate X with low level L1, the pin PWR _ KY _ N of the PM receives the low level, a power supply key event is generated, an LCD control circuit is awakened, the LCD power supply time sequence is reproduced to enter a power-on time sequence, the CABC signal of the LCD panel is recovered to be normal, namely the PWM signal with the frequency of 60Hz and the period of 16.67ms is output, and the LCD displays normally. After time T2 (the period of the PWM signal output from the GPIO pin of the PMI is 10ms, and the duty ratio is 50%, so T2 is equal to 5ms), the PWM signal output from the GPIO pin of the PMI flips to a high level, so that the PWM signal is output to a high level after being processed by an or gate X with a low level L1, and the PWR _ KY _ N pin of the PM receives a high level signal, so that the power key event is released.

In the second case, if the PWM signal output from the pin GPIO of the PMI is at a high level, so that the PWM signal is output as a high level after being processed by the or gate X with the low level L1, the pin PWR _ KY _ N of the PM is input as a high level signal, and no power key event occurs; after time T (the period of the PWM signal output by the pin GPIO of the PMI is 10ms, the duty ratio is 50%, so T is less than 5ms), the PWM signal output by the pin GPIO of the PMI is inverted to be low level, so the PWM signal is processed by an OR gate X with the low level L1 and then output to be low level, the pin PWR _ KY _ N of the PM receives the low level signal, a power supply key event is generated, an LCD control circuit enters a sleep state, and the LCD power supply time sequence enters a power-off time sequence; after time T0 (the period of the PWM signal output from pin GPIO of PMI is 10ms, the duty ratio is 50%, so T0 is equal to 5ms), the PWM signal output from pin GPIO of PMI is inverted to high level, so that the PWM signal output from pin GPIO of PMI is processed by or gate X with low level L1 and then output to high level, pin PWR _ KY _ N of PM receives the high level signal, and the power key event is released; after time T1(PMI GPIO PWM period is 10ms, so T1 equals 5ms), the PWM signal output by the pin GPIO of the PMI is inverted to low level, so that the PWM signal is output to low level after being processed by an OR gate X with low level L1, the pin PWR _ KY _ N of the PM receives the low level signal, a power supply key event is generated, the LCD control circuit is awakened, the LCD power supply time sequence is reproduced to enter a power-on time sequence, the CABC signal of the LCD panel is recovered to be normal, namely the PWM signal with 16.67ms of frequency of 60Hz is output, and the LCD displays normally. After time T2 (the PWM period of PMI GPIO is 10ms, so T2 is equal to 5ms), the PWM signal output from pin GPIO of PMI is inverted to a high level signal, so that the PWM signal output from pin L1 is output to a high level after being processed by or gate X, and pin PWR _ KY _ N of PM receives the high level signal, and the power key event is released.

So, keep through carrying out the high level with the CABC level signal of LCD panel to carry out logic judgement jointly with the PWM signal of the GPIO output of PMI, realized LCD's automation according to logic judgement result and restarted, practiced thrift system resource, guaranteed the LCD performance, reduced system's consumption, promoted user experience.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An LCD control circuit, comprising: the circuit comprises a logic judgment circuit, a high level holding circuit, an LCD panel, an oscillation circuit and an execution circuit;

the logic judgment circuit comprises a first input end, a second input end and an output end;

the output end of the high level holding circuit is connected with the first input end of the logic judgment circuit;

the output end of the LCD panel is connected with the input end of the high-level holding circuit;

the output end of the oscillating circuit is connected with the second input end of the logic judgment circuit;

the input end of the execution circuit is connected with the output end of the logic judgment circuit, the output end of the execution circuit is connected with the input end of the LCD panel, and the input end of the LCD panel is a power supply end of the LCD panel.

2. The LCD control circuit of claim 1, further comprising a rectifying diode between the input of the high-level holding circuit and the output of the LCD panel;

the anode of the rectifier diode is connected with the output end of the LCD panel;

and the cathode of the rectifier diode is connected with the input end of the high-level holding circuit.

3. The LCD control circuit of claim 1, wherein the high-level holding circuit comprises a voltage holding capacitor having one end connected to the output terminal of the LCD panel and the other end connected to ground.

4. The LCD control circuit of claim 3, wherein the high-level hold circuit further comprises a discharge resistor connected in parallel with the voltage holding capacitor.

5. The LCD control circuit of claim 1, wherein the execution circuit comprises a processor, a first input/output port of the processor is connected to the output of the logic determination circuit, and a second input/output port of the processor is connected to the input of the LCD panel.

6. The LCD control circuit of claim 1, wherein the execution circuit comprises a power management unit, an input of the power management unit is connected to an output of the logic determination circuit, and an output of the power management unit is connected to an input of the LCD panel.

7. The LCD control circuit of claim 1, wherein the execution circuit comprises a power management unit and a processor;

the input end of the power management unit is connected with the output end of the logic judgment circuit, the output end of the power management unit is connected with the first input/output port of the processor, and the second input/output port of the processor is connected with the input end of the LCD panel.

8. The LCD control circuit of claim 1, wherein the oscillating circuit comprises a power management interface unit, an output of the power management interface unit being coupled to the second input of the logic determining circuit.

9. The LCD control circuit of any of claims 1 to 8, wherein the logic decision circuit is an OR gate.

10. A terminal, characterized by comprising an LCD control circuit according to any one of claims 1 to 9.