CN110068755B - Method and device for optimizing test in three-dimensional system-on-chip circuit binding - Google Patents
Method and device for optimizing test in three-dimensional system-on-chip circuit binding Download PDFInfo
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- CN110068755B CN110068755B CN201810065666.3A CN201810065666A CN110068755B CN 110068755 B CN110068755 B CN 110068755B CN 201810065666 A CN201810065666 A CN 201810065666A CN 110068755 B CN110068755 B CN 110068755B
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Abstract
The invention provides a method and a device for optimizing a test in three-dimensional system-on-chip circuit binding, which determine a first quantity by sequencing hardcores in a test group of a test stage in the test group to be bound in an ascending order of test duration, ensure that all through silicon vias in the test group can be tested when the hardcores of the first quantity are tested, increase the hardcores one by one from the hardcores of the first quantity according to the ascending order, form test sets, calculate the test cost corresponding to each test set, determine the lowest test cost, and use the hardcore in the test set corresponding to the lowest test cost as the hardcore for testing in the test stage in the test group; the invention optimizes the test stage in binding independently, fully considers the test time of the three-dimensional system-on-chip circuit in the optimization process, determines the hardcores tested in the test stage in binding in the test group on the premise of minimizing the test time, and achieves the purpose of reducing the test cost.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to a method and a device for optimizing testing in three-dimensional system-on-chip circuit binding.
Background
Along with moore's law, the semiconductor industry has increasing requirements for System-on-chip (SoC) circuit performance, and needs to limit power consumption and cost within a range, and three-dimensional stacking becomes an effective solution for the SoC circuit, and the three-dimensional stacking binding technology includes wire binding, contactless binding and through silicon via connection, wherein the through silicon via connection becomes the best binding scheme for the three-dimensional SoC circuit by virtue of its maturity and high efficiency. Typically, through-silicon vias are typically formed of a cylindrical body of copper material 5 microns in diameter and 50 microns high. The three-dimensional system-on-chip circuit provides many advantages, firstly, the connection distance between the hardcores in the circuit is greatly shortened, thereby reducing the transmission time; secondly, the power consumption is also reduced due to the shortened connection distance; in addition, the three-dimensional stacking technology also supports circuits of hybrid technology.
Despite the above advantages of three-dimensional system-on-a-chip circuits, however, there are many new challenges to overcome in the art before they can be mass produced. Among these challenges, the most critical one is the test problem of the three-dimensional system-on-chip circuit, especially the test cost is high, which results in delay and inability to mass-produce, and the test time directly determines the test cost. The method for reducing the test cost of the three-dimensional system-on-chip circuit and optimizing the test strategy has some existing solutions in the industry and academia.
However, none of these existing efforts is optimized for testing in binding alone, and in addition, the testing time of the three-dimensional system-on-chip circuitry in the actual stack is not fully considered, which directly impacts the final testing cost. Therefore, how to design an optimized test method and further reduce the test cost is very important.
Disclosure of Invention
To overcome the above problems or to at least partially solve the above problems, the present invention provides a method and apparatus for optimizing testing in three-dimensional system-on-chip circuit bonding.
According to one aspect of the invention, a method for optimizing a test in a three-dimensional system-on-chip circuit binding is provided, which comprises the following steps: for any test group in the layer to be tested in the test stage in binding, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group; sorting hardcores in the target test group in an ascending order according to the test duration to form a set as an ascending order sorting set; determining a first number of hard cores in a minimum hard core set according to the ascending sorting set, wherein when the minimum hard core set is used for testing the hard cores in the minimum hard core set, a test path can pass through all silicon through holes in a target test group; acquiring a test cost corresponding to each test set, wherein each test set is a set formed by a second number of hard cores in the ascending sorting set, the second number is obtained from a first number until a first total number is obtained one by one, the first total number is the total number of through silicon vias in a target test group, and the test cost corresponding to each test set is the cost for testing the hard cores in each test set; and determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in the binding.
Wherein determining a first number of hardcores in the minimum set of hardcores according to the ascending sorted set comprises: determining a second total number of through silicon vias in the target test set; determining the number of newly added through silicon vias connected with each hard core one by one according to the sequence from front to back in the ascending sorting set; the first number is determined based on the second total number and the number of newly added through silicon vias connected to each of the hardmac.
The method for determining the number of the newly added through silicon vias connected with each hard core one by one according to the sequence from front to back in the ascending sorting set comprises the following steps: for any hard core in the ascending sorting set, taking a set formed by silicon through holes connected with the hard core before the hard core in the ascending sorting set as a silicon through hole set; determining a through silicon via connected with any hard core; and determining a third number of through silicon holes which do not belong to the through silicon hole set in the through silicon holes connected with any one of the hardcores, and taking the third number as the number of the newly added through silicon holes connected with any one of the hardcores.
Wherein determining the first number according to the second total number and the number of the newly added through silicon vias connected with each hardmac comprises: according to the sequence from the front to the back in the ascending sorting set, subtracting the number of newly added through silicon vias connected with each hard core from the second total number one by one to obtain a difference value, and adding one to the count each time the number of newly added through silicon vias connected with each hard core is subtracted; when the difference is zero, the count is taken as the first number.
Obtaining a test cost corresponding to each test set, including: for any inspection set, acquiring the total test duration of the hardcores in the any inspection set; determining the yield of each hard core; determining hard cores which do not participate in the test, wherein the hard cores which do not participate in the test are the hard cores in the target test group except the hard cores in any test set; and taking the ratio of the total test time length of the hard cores in any inspection set to the product of the yield of the hard cores not participating in the test as the test cost corresponding to any inspection set.
Wherein, obtaining the total test duration of the hardcores in any inspection set comprises: acquiring the test duration of each hard core in any inspection set; and taking the sum of the test time lengths of each hard core in any check set as the total test time length of the hard cores in any check set.
Wherein, confirm the yields of each hardcore, include: determining a preset value according to historical data; the preset value is used as the yield of each hard core.
In another aspect of the present invention, an apparatus for optimizing a test in three-dimensional system-on-chip circuit bonding is provided, including: at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, which invokes the program instructions to perform the methods described above.
In yet another aspect of the invention, a computer program product is provided, the computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method described above.
In yet another aspect of the present invention, a non-transitory computer-readable storage medium is provided, which stores a computer program that causes a computer to perform the above-described method.
The invention provides a method and a device for optimizing the test in the circuit binding of a three-dimensional system on chip, which determine a first quantity by sequencing the hardcores in a test group of a test stage in the to-be-bound process in an ascending order of test duration, the first number is the first number of hardcores in ascending order, which can be connected to all of the through silicon vias in the test set, to ensure that all through-silicon vias in the test set can be tested while testing the first number of hardmac, then, starting from the first number of hard cores in ascending order, adding one hard core each time, using the set formed by all the hard cores after the hard cores are added as a check set, calculating the test cost corresponding to each check set, determining the lowest test cost in all the obtained test costs, and taking the hardcores in the inspection set corresponding to the lowest test cost as the hardcores to be tested in the binding test stage in the test group; the invention optimizes the test stage in binding independently, fully considers the test time of the three-dimensional system-on-chip circuit in the optimization process, determines the hardcores tested in the test stage in binding in the test group on the premise of minimizing the test time, and achieves the purpose of reducing the test cost.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for optimizing testing in three-dimensional system-on-chip circuit bonding according to an embodiment of the present invention;
FIG. 2 is a flow chart of three-dimensional system-on-chip circuit testing based on through-silicon-via connections;
FIG. 3 is a flow diagram of hardmac selection in three-dimensional system-on-chip circuit binding according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment of the present invention, referring to fig. 1, there is provided a method for optimizing a test in a three-dimensional system-on-chip circuit binding, including: s11, regarding any test group in the layers to be tested in the test stage in the binding process, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group; s12, sorting the hardcores in the target test group in ascending order according to the test duration to form a set as an ascending order set; s13, determining the first number of the hardcores in the minimum hardcore set according to the ascending sorting set, wherein when the minimum hardcore set is used for testing the hardcores in the minimum hardcore set, the testing path can pass through all the silicon through holes in the target testing group; s14, obtaining the testing cost corresponding to each testing set, wherein each testing set is a set formed by the first second number of hardcores in the ascending sorting set, the second number is taken from the first number until the first total number is taken one by one, the first total number is the total number of the through silicon vias in the target testing set, and the testing cost corresponding to each testing set is the cost for testing the hardcores in each testing set; and S15, determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in the binding.
Specifically, the testing of the three-dimensional system-on-chip circuit needs to ensure whether the stacked through-silicon vias are fault-free, and in addition, the Hard Core (Hard Core) on each testing layer is also fault-free, so that a more complicated testing procedure is required compared with the conventional two-dimensional system-on-chip circuit. As shown in fig. 2, firstly, before each Test layer is bound, the three-dimensional system-on-chip circuit needs to be tested separately for each Test layer circuit, so as to ensure that the hardmac on each Test layer is fault-free, the Test is similar to the conventional two-dimensional system-on-chip circuit Test and is called a Pre-bond Test (Pre-bond Test), the first leftmost column in fig. 2 represents the Pre-bond Test, and if the circuit contains n Test layers, n times of Pre-bond tests are needed; subsequently, in the process of three-dimensional stacking, the Test layer 1 and the Test layer 2 need to be tested, and after the two Test layers are bound, the through-silicon-via connection between the two Test layers is fault-free, similarly, after the Test layer 3 is bound to the Test layer 2, the three Test layers need to be tested again, and so on, the Test layer n-1 is tested, n-1 tests are performed in total to ensure the through-silicon-via connection, and the Test is called as a Mid-bound Test (Mid-bound Test) and also called as a kgd (known Good die) Test; after the last layer, layer n, is bound, the three-dimensional system-on-chip circuit has completed stacking, and the Test performed is called Post-bound Test (Post-bound Test).
In the above test flow, the purpose of the test in the binding is to ensure that the through-silicon-via connection is faultless, however, the test in the current binding can test each hardmac of the test layer again, so that the test time is greatly increased, and the test time is positively correlated with the test cost, so that the time waste can be caused by repeated tests.
In this embodiment, from the purpose of testing in binding, the purpose of testing in binding is to ensure that there is no fault in the through-silicon via connections, so that this embodiment should ensure that all through-silicon via connections can be tested on one hand, and should ensure that the test duration is minimized on the other hand, and the test cost is calculated on the above two premises, and the test scheme corresponding to the lowest test cost is selected, so as to ensure that the test scheme is optimal.
More specifically, hard cores in a test group to be tested in binding are sorted, the hard cores are sorted in an ascending order of test duration, from a first hard core, through silicon vias connected to each hard core are determined one by one, after all the through silicon vias in the test group are determined to have the hard cores connected with the through silicon vias, the connection condition of all the through silicon vias in the test group can be determined to be tested, the set formed by the determined hard cores is the minimum hard core set, the number of the hard cores in the minimum hard core set is a first number, the first number is the minimum number which ensures that the connection condition of all the through silicon vias in the test group can be tested, then on the basis of the first number, one hard core is added from the hard cores of the first number each time in the ascending order, the combination formed by all the hard cores with the hard cores added is used as a test set, and calculating the test cost corresponding to each check set, determining the lowest test cost in all the obtained test costs, and taking the hardcores in the check sets corresponding to the lowest test costs as the hardcores for testing in the binding test stage in the test group.
The embodiment optimizes the testing stage in binding independently, fully considers the testing time of the three-dimensional system-on-chip circuit in the optimization process, determines the hardcores tested in the testing stage in binding in the testing group on the premise of minimizing the testing time, and achieves the purpose of reducing the testing cost.
Based on the above embodiment, determining the first number of hardcores in the minimum set of hardcores according to the ascending sorted set comprises: determining a second total number of through silicon vias in the target test set; determining the number of newly added through silicon vias connected with each hard core one by one according to the sequence from front to back in the ascending sorting set; the first number is determined based on the second total number and the number of newly added through silicon vias connected to each of the hardmac.
The method for determining the number of the newly added through silicon vias connected with each hard core one by one according to the sequence from front to back in the ascending sorting set comprises the following steps: for any hard core in the ascending sorting set, taking a set formed by silicon through holes connected with the hard core before the hard core in the ascending sorting set as a silicon through hole set; determining a through silicon via connected with any hard core; and determining a third number of through silicon holes which do not belong to the through silicon hole set in the through silicon holes connected with any one of the hardcores, and taking the third number as the number of the newly added through silicon holes connected with any one of the hardcores.
Wherein determining the first number according to the second total number and the number of the newly added through silicon vias connected with each hardmac comprises: according to the sequence from the front to the back in the ascending sorting set, subtracting the number of newly added through silicon vias connected with each hard core from the second total number one by one to obtain a difference value, and adding one to the count each time the number of newly added through silicon vias connected with each hard core is subtracted; when the difference is zero, the count is taken as the first number.
Specifically, for the hard cores in the test group, according to the ascending order of the test duration, starting from the first hard core, determining the through silicon vias connected with the first hard core, determining the number of the through silicon vias connected with the first hard core, subtracting the number of the through silicon vias connected with the first hard core from the total number of the through silicon vias in the test group to obtain a difference value, and counting and adding one; for each hard core behind the first hard core, determining the number of newly-added through silicon vias connected with each hard core one by one according to an ascending sorting sequence, subtracting the number of newly-added through silicon vias connected with each hard core one by one from the total number of the through silicon vias in the test group to obtain a difference value, adding one to the count when subtracting the number of newly-added through silicon vias connected with each hard core once, and when the difference value is zero, indicating that all the through silicon vias in the test group have hard cores connected with the through silicon vias, and taking the count as the first number; the newly added through silicon vias connected with the hardmac are through silicon vias connected with the hardmac, and the through silicon vias connected with the hardmac do not belong to through silicon vias having a connection relationship with any hardmac before the hardmac.
Based on the above embodiments, obtaining the test cost corresponding to each inspection set includes: for any inspection set, acquiring the total test duration of the hardcores in the any inspection set; determining the yield of each hard core; determining hard cores which do not participate in the test, wherein the hard cores which do not participate in the test are the hard cores in the target test group except the hard cores in any test set; and taking the ratio of the total test time length of the hard cores in any inspection set to the product of the yield of the hard cores not participating in the test as the test cost corresponding to any inspection set.
Specifically, as shown in fig. 3, the unselected cores Cu are the hard cores other than the hard cores in the inspection set, for the unselected cores Cu, the hard cores with the shortest test duration are selected one by one from the unselected cores Cu, the selected hard cores are added to the hard cores that need to be tested in the binding process in the test group, a set formed by the hard cores that need to be tested in the binding process is used as the inspection set, on this basis, the test duration of the hard cores in the test inspection set is obtained, the test cost is calculated according to the test cost model, after all the hard cores in the unselected cores Cu perform the above process, a plurality of test costs are obtained, the minimum test cost is selected from the plurality of test costs, and the hard core in the inspection set corresponding to the minimum test cost is used as the final hard core that is tested in the binding process in the test group.
Based on the above optimization method, some hardcores in the test group may not be tested in the testing stage during binding, and if the hardcores themselves fail due to the yield of stacking, the circuit cannot pass the test after binding. Therefore, the test cost in the binding is not only related to the test time, but also related to the yield of each hard core after stacking; therefore, the yield of the hard core is introduced into the test cost model, and the calculation formula of the test cost is as follows:
wherein, CSmidtime is the total test duration, YiAnd n is the number of the hardcores which are not tested in the binding testing stage in the testing group.
In the embodiment, the yield of the hard core is introduced into the test cost model, and the influence on the test after binding is also considered in the optimization process of the test in binding, so that the test cost model is more consistent with the actual test condition, and the test cost can be further reduced.
Based on the above embodiment, obtaining the total test duration of the hardcores in any inspection set includes: acquiring the test duration of each hard core in any inspection set; and taking the sum of the test time lengths of each hard core in any check set as the total test time length of the hard cores in any check set.
Based on the above embodiments, determining the yield of each hard core includes: determining a preset value according to historical data; the preset value is used as the yield of each hard core.
Specifically, because the yield of each hard core is very high, and the distance between the hard cores is very short, the number of the hard cores is huge, for convenience of calculation, the yield of each hard core is assumed to be the same, a preset value is determined based on historical data, and the preset value is used as the yield of each hard core.
As another embodiment of the present invention, an apparatus for optimizing a test in three-dimensional system-on-chip circuit bonding is provided, including: at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the methods provided by the method embodiments, for example, the method includes: for any test group in the layer to be tested in the test stage in binding, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group; sorting hardcores in the target test group in an ascending order according to the test duration to form a set as an ascending order sorting set; determining a first number of hard cores in a minimum hard core set according to the ascending sorting set, wherein when the minimum hard core set is used for testing the hard cores in the minimum hard core set, a test path can pass through all silicon through holes in a target test group; acquiring a test cost corresponding to each test set, wherein each test set is a set formed by a second number of hard cores in the ascending sorting set, the second number is obtained from a first number until a first total number is obtained one by one, the first total number is the total number of through silicon vias in a target test group, and the test cost corresponding to each test set is the cost for testing the hard cores in each test set; and determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in the binding.
As yet another embodiment of the present invention, there is provided a computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the methods provided by the above-described method embodiments, for example, including: for any test group in the layer to be tested in the test stage in binding, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group; sorting hardcores in the target test group in an ascending order according to the test duration to form a set as an ascending order sorting set; determining a first number of hard cores in a minimum hard core set according to the ascending sorting set, wherein when the minimum hard core set is used for testing the hard cores in the minimum hard core set, a test path can pass through all silicon through holes in a target test group; acquiring a test cost corresponding to each test set, wherein each test set is a set formed by a second number of hard cores in the ascending sorting set, the second number is obtained from a first number until a first total number is obtained one by one, the first total number is the total number of through silicon vias in a target test group, and the test cost corresponding to each test set is the cost for testing the hard cores in each test set; and determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in the binding.
As yet another embodiment of the present invention, there is provided a non-transitory computer-readable storage medium storing a computer program that causes a computer to perform the methods provided by the above-described method embodiments, including, for example: for any test group in the layer to be tested in the test stage in binding, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group; sorting hardcores in the target test group in an ascending order according to the test duration to form a set as an ascending order sorting set; determining a first number of hard cores in a minimum hard core set according to the ascending sorting set, wherein when the minimum hard core set is used for testing the hard cores in the minimum hard core set, a test path can pass through all silicon through holes in a target test group; acquiring a test cost corresponding to each test set, wherein each test set is a set formed by a second number of hard cores in the ascending sorting set, the second number is obtained from a first number until a first total number is obtained one by one, the first total number is the total number of through silicon vias in a target test group, and the test cost corresponding to each test set is the cost for testing the hard cores in each test set; and determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in the binding.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to computer program instructions, where the computer program may be stored in a computer readable storage medium, and when executed, the computer program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, the description is as follows: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A method for optimizing testing in three-dimensional system-on-chip circuit binding is characterized by comprising the following steps:
for any test group in the layer to be tested in the test stage in binding, taking the test group as a target test group, and determining a hard core and a through silicon via in the target test group;
sorting the hardcores in the target test group in an ascending order according to the test duration to form a set as an ascending order set;
determining a first number of hardcores in a minimum hardcore set according to the ascending sorting set, wherein when the hardcores in the minimum hardcore set are tested, a test path can pass through all through silicon vias in the target test group;
acquiring a test cost corresponding to each test set, wherein each test set is a set formed by the first second number of hardcores in the ascending sorting set, the second number is obtained from the first number until the first total number is obtained one by one, the first total number is the total number of through silicon vias in the target test group, and the test cost corresponding to each test set is the cost for testing the hardcores in each test set;
and determining the lowest test cost, and determining the hardcores in the check set corresponding to the lowest test cost as the hardcores tested by the target test group in the test stage in binding.
2. The method of claim 1, wherein determining the first number of hardcores in the minimum set of hardcores according to the ascending ordered set comprises:
determining a second total number of through silicon vias in the target test set;
determining the number of newly added through silicon vias connected with each hard core one by one according to the sequence from front to back in the ascending sorting set;
and determining the first number according to the second total number and the number of the newly added through silicon vias connected with each hard core.
3. The method of claim 2, wherein determining the number of newly added through-silicon vias connected to each hardmac one by one in the ascending sorted set from front to back comprises:
for any hard core in the ascending sorting set, taking a set formed by through silicon vias connected with a hard core before the hard core in the ascending sorting set as a through silicon via set;
determining a through silicon via connected with any hard core;
and determining a third number of through silicon holes which do not belong to the through silicon hole set in the through silicon holes connected with any one of the hardcores, and taking the third number as the number of the newly added through silicon holes connected with any one of the hardcores.
4. The method of claim 2, wherein determining the first number based on the second total number and the number of newly added through silicon vias connected to each of the hardmac comprises:
according to the sequence from the front to the back in the ascending sorting set, subtracting the number of newly added through silicon vias connected with each hard core from the second total number one by one to obtain a difference value, and adding one to the count each time the number of newly added through silicon vias connected with each hard core is subtracted;
when the difference is zero, the count is taken as the first number.
5. The method of claim 1, wherein obtaining the test cost corresponding to each verification set comprises:
for any inspection set, acquiring the total test duration of the hardcores in the any inspection set;
determining the yield of each hard core;
determining hard cores not participating in testing, wherein the hard cores not participating in testing are the hard cores in the target testing group except the hard cores in any testing set;
and taking the ratio of the total test time length of the hard cores in any inspection set to the product of the yield of the hard cores not participating in the test as the test cost corresponding to any inspection set.
6. The method of claim 5, wherein said obtaining a total test duration for hardcores in any of said inspection sets comprises:
acquiring the test duration of each hard core in any inspection set;
and taking the sum of the test time lengths of each hard core in any check set as the total test time length of the hard cores in any check set.
7. The method of claim 5, wherein said determining a yield of each hard core comprises:
determining a preset value according to historical data;
and taking the preset value as the yield of each hard core.
8. An apparatus for optimizing testing in three-dimensional system-on-chip circuit bonding, comprising:
at least one processor; and at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor calling the program instructions to perform the method of any of claims 1 to 7.
9. A non-transitory computer-readable storage medium storing a computer program that causes a computer to perform the method according to any one of claims 1 to 7.
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Citations (4)
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|---|---|---|---|---|
| CN102654561A (en) * | 2012-04-17 | 2012-09-05 | 清华大学 | Scanning and testing method based on three-dimensional chips |
| CN103390205A (en) * | 2013-07-31 | 2013-11-13 | 哈尔滨工业大学 | Method for testing and scheduling soft-core-based three-dimensional SoC (system on chip) under constraint of power consumption |
| CN103560097A (en) * | 2013-11-20 | 2014-02-05 | 中国科学院深圳先进技术研究院 | Wiring path optimization method for three-dimensional chip |
| CN104007383A (en) * | 2014-03-07 | 2014-08-27 | 合肥工业大学 | Method for optimizing test wrapper scan chains of three-dimensional IP core |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7356745B2 (en) * | 2004-02-06 | 2008-04-08 | Texas Instruments Incorporated | IC with parallel scan paths and compare circuitry |
-
2018
- 2018-01-23 CN CN201810065666.3A patent/CN110068755B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102654561A (en) * | 2012-04-17 | 2012-09-05 | 清华大学 | Scanning and testing method based on three-dimensional chips |
| CN103390205A (en) * | 2013-07-31 | 2013-11-13 | 哈尔滨工业大学 | Method for testing and scheduling soft-core-based three-dimensional SoC (system on chip) under constraint of power consumption |
| CN103560097A (en) * | 2013-11-20 | 2014-02-05 | 中国科学院深圳先进技术研究院 | Wiring path optimization method for three-dimensional chip |
| CN104007383A (en) * | 2014-03-07 | 2014-08-27 | 合肥工业大学 | Method for optimizing test wrapper scan chains of three-dimensional IP core |
Non-Patent Citations (2)
| Title |
|---|
| "基于TSV 绑定的三维芯片测试优化策略";神克乐 等;《电子学报》;20160131;第44卷(第1期);第458-462页 * |
| "基于硅通孔绑定后三维芯片测试调度优化方案";聂牧;《计算机工程与科学》;20170331;第39卷(第3期);第155-159页 * |
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