CN106371957B - A kind of determination method of PCIe bus, witness plate and verifying system - Google Patents
A kind of determination method of PCIe bus, witness plate and verifying system Download PDFInfo
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- CN106371957B CN106371957B CN201610767511.5A CN201610767511A CN106371957B CN 106371957 B CN106371957 B CN 106371957B CN 201610767511 A CN201610767511 A CN 201610767511A CN 106371957 B CN106371957 B CN 106371957B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000012360 testing method Methods 0.000 claims abstract description 210
- 238000003475 lamination Methods 0.000 claims abstract description 27
- 238000001514 detection method Methods 0.000 claims description 62
- 238000013100 final test Methods 0.000 claims description 19
- 238000009826 distribution Methods 0.000 claims description 3
- 235000013399 edible fruits Nutrition 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
Abstract
The present invention provides a kind of determination method of PCIe bus, witness plate and verifying systems, and witness plate includes: at least one lamination and at least one line group；At least one line group is corresponded at least one practical PCIe bus；Each of at least one line group line group, comprising: at least two test PCIe buses；At least two test PCIe bus arrangements that each line group includes are at least one lamination；At least two test PCIe buses that each line group includes correspond to different length；The attribute for at least two test PCIe buses that each line group includes, the attribute of practical PCIe bus corresponding with the line group are identical；Each tests PCIe bus, and one end receives the test signal of signal emitting plate input, the other end exports test signal to signal-testing apparatus for connecting external signal test equipment for connecting external signal expelling plate.This programme can determine that the length of PCIe bus can guarantee signal integrity.
Description
Technical field
The present invention relates to the field of test technology, in particular to a kind of PCIe (Peripheral Component
Interconnect Express, Peripheral Component Interconnect standard interface) the determination method of bus, witness plate and verifying system.
Background technique
With the arrival of cloud computing era, server quickly grows emergence, in the motherboard design of server, signal speed
Rate is higher and higher, and demand of the high speed signal to signal integrity is also constantly being promoted.
In server master board design, the length for generally requiring PCIe bus guarantees within the scope of SPEC, can so protect
It can satisfy the demand of signal integrity in card PCIe bus when transmitting signal.
However, the length for generally requiring PCIe bus is more than SPEC in the actual design of the boards such as mainboard, backboard, network interface card
How range determines the length of PCIe bus, can guarantee signal integrity, become urgent problem.
Summary of the invention
The embodiment of the invention provides a kind of determination method of PCIe bus, witness plate and verifying systems, to determine
The length of PCIe bus can guarantee signal integrity.
A kind of witness plate, comprising: at least one lamination and at least one line group；
At least one practical PCIe bus at least one described line group and external board to be built corresponds；
Each of at least one line group line group, comprising: at least two test PCIe buses；
At least two test PCIe bus arrangements that each line group includes are at least one described lamination；
At least two test PCIe buses that each line group includes correspond to different length；
The parameter for at least two test PCIe buses that each line group includes, practical PCIe corresponding with the line group are total
The parameter of line is identical；
Each tests PCIe bus, and one end receives the signal emitting plate input for connecting external signal expelling plate
Test signal, the test signal exports and set to the signal testing for connecting external signal test equipment by the other end
It is standby.
Preferably,
The number of at least one lamination is identical as the lamination number of the board to be created；
Arrangement of at least two test PCIe buses that each line group includes at least one described lamination, with
Arrangement of the corresponding practical PCIe bus of the line group on the board to be created is identical.
Preferably, the length of include at least two test PCIe buses of each line group are according to corresponding length threshold
Gradient distribution.
Preferably,
Difference cabling clock synchronization is corresponded in the practical PCIe bus, the attribute includes: the line width and difference of difference cabling pair
Divide the line spacing of cabling pair；
When the practical PCIe bus corresponds to single cabling, the attribute includes: the line width of single cabling.
A kind of verifying system, comprising: signal emitting plate, signal-testing apparatus and the witness plate as described in any of the above-described；Its
In,
The signal emitting plate is connect with the target detection PCIe bus on the witness plate, for generating test signal,
And the test signal of generation is exported to the target detection PCIe bus；
The signal-testing apparatus is connect with the target detection PCIe bus, for receiving the target detection PCIe
The test signal of bus output, and the signal integrity of the test signal received is tested.
Preferably, the signal-testing apparatus includes: oscillograph；Wherein,
The oscillograph is connect with the target detection PCIe bus, defeated for receiving the target detection PCIe bus
Test signal out, and according to the test signal received, generate corresponding eye figure.
Preferably, the signal-testing apparatus, comprising: comparator；Wherein,
The comparator connect with the target detection PCIe bus, and connect with the signal emitting plate, for connecing
The test signal of the target detection PCIe bus output is received, and receives the test signal of the signal emitting plate output, and
The test signal of target detection PCIe bus output is compared with the test signal that the signal emitting plate exports, and
Export comparison result.
Preferably, the verifying system further comprises: display equipment；Wherein,
The display equipment, connect with the signal-testing apparatus, for receiving the survey of the signal-testing apparatus output
Test result, and show the test result.
A kind of determination method of the PCIe bus based on any of the above-described verifying system, comprising:
S1: the parameter that the practical PCIe bus of target of arrangement is needed in board to be built is determined；
S2: according to the parameter of the practical PCIe bus of the target, determining corresponding score group in the witness plate, and
Selection target tests PCIe bus in the score group；
S3: the target detection bus is connect with the signal emitting plate and the signal-testing apparatus；
S4: test signal is generated using the signal emitting plate, the test signal of generation is exported to the target detection
PCIe bus, the target detection PCIe bus export the test signal received to the signal-testing apparatus, utilize institute
Signal-testing apparatus is stated to test the signal integrity of the test signal received；
S5: according to the test result of the signal-testing apparatus, a test is reselected in the score group
This reselected is tested PCIe bus as target detection PCIe bus, S3 is continued to execute, until determination by PCIe bus
Execute S6 when final test PCIe bus out, the length of the final test PCIe bus be in the score group,
Meet the maximum length of signal integrity；
S6: according to the length of the final test PCIe bus, determine that the practical PCIe bus of the target is corresponding most
Long length.
It preferably, include the connection PCIe bus being connect with the target detection PCIe bus on the signal emitting plate
When, the length according to the final test PCIe bus determines that the practical PCIe bus of the target is corresponding and most greatly enhances
Degree, comprising: calculate the corresponding maximum length of the practical PCIe bus of target using the first formula；
First formula includes:
Lmax=L1+L2
Wherein, LmaxFor characterizing the corresponding maximum length of the practical PCIe bus of the target；L1It is described final for characterizing
Test PCIe bus length；L2For characterizing the length of the connection PCIe bus.
The embodiment of the invention provides a kind of determination method of PCIe bus, witness plate and verifying systems, by verifying
At least one line group is set in plate, at least one practical PCIe bus of arrangement is needed at least one line group and board to be built
It include at least two test PCIe buses of different length in one-to-one correspondence and each line group, in board to be built
It, can be according to target corresponding with the practical PCIe bus of target when the length of the practical PCIe bus of the target that need to be arranged is determined
At least two test PCIe buses that line group includes transmit the test signal of signal emitting plate output, to utilize signal
Test equipment tests the signal integrity of test signal, and determines in score group to include most according to test result
Whole test PCIe bus, so as to determine to need cloth on board to be built according to the length of final test PCIe bus
The practical PCIe bus of the target set is under the premise of meeting signal integrity, the maximum length that can choose.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of witness plate floor map provided by one embodiment of the present invention；
Fig. 2 is a kind of verifying system construction drawing provided by one embodiment of the present invention；
Fig. 3 is another verifying system construction drawing provided by one embodiment of the present invention；
Fig. 4 is another verifying system construction drawing provided by one embodiment of the present invention；
Fig. 5 is another verifying system construction drawing provided by one embodiment of the present invention；
Fig. 6 is a kind of method flow diagram provided by one embodiment of the present invention；
Fig. 7 is another method flow diagram provided by one embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of witness plates, comprising: at least one lamination and at least one line group；
At least one practical PCIe bus at least one described line group and external board to be built corresponds；
Each of at least one line group line group, comprising: at least two test PCIe buses；
At least two test PCIe bus arrangements that each line group includes are at least one described lamination；
At least two test PCIe buses that each line group includes correspond to different length；
The parameter for at least two test PCIe buses that each line group includes, practical PCIe corresponding with the line group are total
The parameter of line is identical；
Each tests PCIe bus, and one end receives the signal emitting plate input for connecting external signal expelling plate
Test signal, the test signal exports and set to the signal testing for connecting external signal test equipment by the other end
It is standby.
Wherein, which at least may include: at least one of mainboard, backboard and network interface card.
If in the prior art, guaranteeing that board to be built after building is completed, constructs on the board of completion to determine
For the practical PCIe bus of arrangement when transmitting signal, length can guarantee that the signal integrity of the signal of transmission is met the requirements,
It needs to construct the board of the practical PCIe bus of corresponding different length respectively, and carries out signal for each board constructed
Test result is met the length of corresponding practical PCIe bus on the board of signal integrity as determination by the test of transmission
Length, the higher cost of the prior art.
Utilize above-mentioned witness plate provided in an embodiment of the present invention, it is ensured that a witness plate only need to be produced, it can be right
The length of the practical PCIe bus of each item of required arrangement is verified on board to be built, only need to be according to required on board to be built
The parameter of the practical PCIe bus of the target of arrangement is determined corresponding score group on witness plate, can be selected in score group
A test PCIe bus is selected as target detection PCIe bus, by target detection PCIe bus and external signal emitting plate,
The test signal that signal emitting plate exports can be exported to signal-testing apparatus, be utilized by external signal-testing apparatus connection
Signal-testing apparatus determines that the practical PCIe bus correspondence of target is optionally most greatly enhanced to the integrity test result of test signal
Degree, not only can quickly determine the length of the practical PCIe bus of target, can also reduce cost, it is accurate that raising length determines
Rate.
Referring to FIG. 1, being a kind of floor map of witness plate.Assuming that on board to be built required arrangement practical PCIe
Bus is 4, and the parameter of the practical PCIe bus of each is different, such as this 4 practical PCIe buses are respectively practical PCIe
Bus 1, practical PCIe bus 2, practical PCIe bus 3 and practical PCIe bus 4, therefore, in the Fig. 1, which includes 4
A line group is respectively as follows: A line group, B line group, C line group and D line group, the corresponding practical PCIe bus of each line group.Each
It include that n item tests PCIe bus in line group, n is the integer not less than 2.
In Fig. 1, each test PCIe bus for including in each line group corresponds to an input end interface and one
A output end interface, wherein input end interface is used to connect with external signal emitting plate, and output end interface is used for and outside
Signal-testing apparatus connection.
It, can will be corresponding defeated in each line group in order to guarantee that verifying workload can be reduced to the greatest extent in verification process
Enter end interface and be integrated into a connector, alternatively, being a connector by the output end Interface integration in each line group.Example
Such as, corresponding input end interface in each line group is integrated into a connector by the present embodiment, then in verification process, it can
It is connect with the connector for the score group that will be determined with external signal emitting plate, the target detection that will be selected in score group
The output end interface of PCIe bus is connect with external signal-testing apparatus, when replacing next target detection PCIe bus,
The output end interface of current target detection PCIe bus directly can be disconnected into the connection with signal-testing apparatus, and will replacement
The output end interface of next target detection PCIe bus be connected to signal-testing apparatus.So as to reduce current mesh
The input end interface of mapping examination PCIe bus and signal emitting plate disconnect and next target detection PCIe bus
Input end interface is connected to the workload of signal emitting plate.
In an embodiment of the invention, the lamination number of witness plate can be at least one, for example, the witness plate includes
One lamination, the test PCIe bus that each line group includes are arranged on a lamination, are treated using each line group
The length of the practical PCIe bus of each item of required arrangement is verified on building board.
In an embodiment of the invention, due to the signal transmission effect for the PCIe bus arranged on the same lamination,
The signal transmission effect of PCIe bus on laminations different from being arranged in is different, therefore, in order to improve practical PCIe bus length
The accuracy rate of verifying, the number of at least one lamination are identical as the lamination number of the board to be created；For example, to be built
The lamination number of board is 8 layers, then the witness plate includes 8 laminations.
In order to further increase the accuracy rate of practical PCIe bus length verifying, at least two surveys that each line group includes
Arrangement of the PCIe bus at least one described lamination is tried, practical PCIe bus corresponding with the line group is described to be created
Arrangement on board is identical.
For example, arrangement of the practical PCIe bus 1 on board to be built is the first floor for being arranged in board to be built, that
The arrangement of n item test PCIe bus on line group A corresponding with practical PCIe bus 1, is similarly and is arranged in verifying
The first floor of plate.Since the signal transmission effect for being arranged in the first floor with being arranged in bottom is identical, then can also be by the n on line group A
Item tests PCIe bus arrangement in the bottom of witness plate.
For another example, arrangement of the practical PCIe bus 2 on board to be built is the second layer for being arranged in board to be built,
And the layer 5 of board to be built is further arranged in by via hole, then, on line group B corresponding with practical PCIe bus 2
N item test PCIe bus arrangement, be similarly and be arranged in the witness plate second layer, and be further arranged in and tested by via hole
Demonstrate,prove the layer 5 of plate.
It in an embodiment of the invention, can will be in witness plate in order to determine the maximum length of practical PCIe bus
The length for at least two test PCIe buses that each line group includes, according to corresponding length threshold distribution gradient.
Corresponding length threshold can be equal in not collinear group, can also be unequal.The present embodiment is carried out for equal
Explanation.
The length threshold can be configured before witness plate production.Wherein, length threshold setting is bigger, verifies
When obtain practical PCIe bus maximum length speed it is also faster；Length threshold setting it is smaller, when verifying, obtains reality
The maximum length of PCIe bus is more accurate.For example, the length threshold is 1mil.
For including 20 test PCIe buses in line group A, in order to which guarantee can be according to this 20 test PCIe buses
The maximum length for determining practical PCIe bus needs in the length range of this 20 test PCIe buses to include SPEC range.
For example, SPEC range provide the PCIe bus on the boards such as mainboard, backboard, network interface card length need to no more than 15mil, then this 20
Item tests the corresponding length of PCIe bus can be with are as follows: 10mil, 11mil, 12mil ..., 29mil.
In an embodiment of the invention, it in order to further increase the accuracy that the length of practical PCIe bus is verified, needs
Guarantee that the parameter of each test PCIe bus in line group is identical as the parameter of corresponding practical PCIe bus.Wherein, in board
The bus of upper arrangement may include two types: the first seed type is difference cabling pair, and second of type is single cabling.Its
In:
Difference cabling clock synchronization is corresponded in the practical PCIe bus, the attribute includes: the line width and difference of difference cabling pair
Divide the line spacing of cabling pair；
When the practical PCIe bus corresponds to single cabling, the attribute includes: the line width of single cabling.
For further increase the accuracy rate that length determines, the laminated thickness of witness plate, shape, size and used material
It can also be identical as board to be built.
Referring to FIG. 2, one embodiment of the invention provides a kind of verifying system, which may include: signal
Expelling plate 201, signal-testing apparatus 202 and the witness plate 203 as described in any of the above-described；Wherein,
The signal emitting plate 201 is connect with the target detection PCIe bus on the witness plate 203, is surveyed for generating
Trial signal, and the test signal of generation is exported to the target detection PCIe bus；
The signal-testing apparatus 202 is connect, for receiving the target detection with the target detection PCIe bus
The test signal of PCIe bus output, and the signal integrity of the test signal received is tested.
As it can be seen that the verifying system provided according to embodiments of the present invention, can use signal emitting plate and generates test signal, by
The target detection PCIe bus connect in witness plate with signal emitting plate, connecting with signal-testing apparatus is transmitted, and is utilized
Signal-testing apparatus tests the integrality of the test signal of transmission, can determine that practical PCIe is total according to test result
The maximum length of line.
It wherein, can shape after the target detection PCIe bus of witness plate is connect with signal emitting plate, signal-testing apparatus
At complete signal circuit.
In an embodiment of the invention, in order to realize the signal integrity for testing signal, following two can at least be passed through
Kind of mode is realized:
Mode 1: it is tested using oscillograph.
Mode 2: it is tested using comparator.
It is directed to above two mode separately below, verifying system provided in an embodiment of the present invention is illustrated.
For mode 1:
In mode 1, referring to FIG. 3, the signal-testing apparatus may include: oscillograph 2021.Wherein, the oscillograph
2021, it is connect with the target detection PCIe bus, for receiving the test signal of the target detection PCIe bus output, and
According to the test signal received, corresponding eye figure is generated.
Eye figure is will to scan each resulting symbol waveform since the twilight sunset of oscillograph acts on and overlap and formed
Figure, refer to benefit experimentally estimate and improve (by adjusting) Transmission system performance when observed on oscillograph
A kind of figure.Wherein, information abundant is contained in eye figure, it can be observed how the shadow of intersymbol interference and noise from eye figure
It rings, embodies the feature of digital signal entirety, so as to estimating system superiority and inferiority degree, therefore, can be generated according to oscillograph
Eye figure determine whether the signal of target detection PCIe bus transfer meets integrity demands.
For mode 2: in mode 2, referring to FIG. 4, the signal-testing apparatus may include: comparator 2022.Wherein,
The comparator 2022 connect with the target detection PCIe bus, and connect with the signal emitting plate, for receiving
The test signal of target detection PCIe bus output is stated, and receives the test signal of the signal emitting plate output, and to institute
The test signal for stating the output of target detection PCIe bus is compared with the test signal that the signal emitting plate exports, and is exported
Comparison result.
Wherein, which, which can also be arranged, compares threshold value, if signal emitting plate is exported to the test signal 1 of comparator,
It exports with target detection PCIe bus to the intensity difference of the test signal 2 of comparator, has been greater than and has compared threshold value, then output signal is complete
Whole property is unsatisfactory for desired comparison result；If intensity difference is not more than and compares threshold value, the ratio that output signal integrality is met the requirements
Relatively result.
In an embodiment of the invention, in order to know the test result of signal-testing apparatus, referring to FIG. 5, the verifying
System may further include: display equipment 501；Wherein,
The display equipment 501, connect with the signal-testing apparatus, for receiving the signal-testing apparatus output
Test result, and show the test result.
Wherein, when showing that equipment is connected with oscillograph, which also needs to be schemed according to eye, determines that test signal is
The test result of the no requirement for meeting signal integrity.When showing that equipment is connected with comparator, which can be direct
Display includes the test result of the comparison result.
Referring to FIG. 6, one embodiment of the invention additionally provide it is a kind of based on any of the above-described verifying system
The determination method of PCIe bus, this method may comprise steps of:
Step 601: determining the parameter that the practical PCIe bus of target of arrangement is needed in board to be built；
Step 602: according to the parameter of the practical PCIe bus of the target, corresponding score is determined in the witness plate
Group, and selection target tests PCIe bus in the score group；
Step 603: the target detection bus is connect with the signal emitting plate and the signal-testing apparatus；
Step 604: generating test signal using the signal emitting plate, the test signal of generation is exported to the target
PCIe bus is tested, the target detection PCIe bus exports the test signal received to the signal-testing apparatus, benefit
It is tested with signal integrity of the signal-testing apparatus to the test signal received；
Step 605: according to the test result of the signal-testing apparatus, a survey is reselected in the score group
PCIe bus is tried, this reselected is tested into PCIe bus as target detection PCIe bus, continues to execute step 603,
Step 606 is executed when determining final test PCIe bus, the length of the final test PCIe bus is in institute
It states in score group, meets the maximum length of signal integrity；
Step 606: according to the length of the final test PCIe bus, determining that the practical PCIe bus of the target is corresponding
Maximum length.
As it can be seen that according to that above embodiment of the present invention, by the way that at least one line group is arranged in witness plate, at least one line
It include difference in group and at least one practical PCIe bus one-to-one correspondence and each line group that need arrangement on board to be built
At least two test PCIe buses of length need the length of the practical PCIe bus of target of arrangement to carry out in board to be built
When determining, at least two test PCIe buses that can include according to score group corresponding with the practical PCIe bus of target are right
The test signal of signal emitting plate output is transmitted, to be carried out using signal integrity of the signal-testing apparatus to test signal
Test, and determine according to test result the final test PCIe bus for including in score group, so as to according to final
Test PCIe bus length, determine to need the practical PCIe bus of target of arrangement meeting signal integrity on board to be built
Under the premise of property, the maximum length that can choose.
It in an embodiment of the invention, can be direct when target detection PCIe bus is connected with signal emitting plate
Target detection PCIe bus is connected on the signal transmitting terminal of signal emitting plate, if on witness plate each line group input terminal
Interface integration is a connector, then a connection PCIe bus can be drawn in the signal transmitting terminal of signal emitting plate, it will
Connection PCIe bus is connected with connector, therefore, in order to guarantee the practical PCIe bus of determining target maximum length standard
Exactness, when on the signal emitting plate including the connection PCIe bus connecting with the target detection PCIe bus, described
According to the length of the final test PCIe bus, the corresponding maximum length of the practical PCIe bus of the target is determined, comprising: benefit
The corresponding maximum length of the practical PCIe bus of target is calculated with formula (1)；
Lmax=L1+L2(1)
Wherein, LmaxFor characterizing the corresponding maximum length of the practical PCIe bus of the target；L1It is described final for characterizing
Test PCIe bus length；L2For characterizing the length of the connection PCIe bus.
It is right for online group of witness plate of input end interface integrated connector below using signal-testing apparatus as oscillograph
The determination method of PCIe bus provided in an embodiment of the present invention is further described, referring to FIG. 7, this method may include:
Step 701: determining the item number that the practical PCIe bus of arrangement is needed in board to be built, and according to board to be built
Produce witness plate.
For example, the item number of the practical PCIe bus of the required arrangement is 4.That is: practical PCIe bus 1, practical PCIe are total
Line 2, practical PCIe bus 3 and practical PCIe bus 4.
Step 702: in several practical PCIe buses for not being determined length, select a practical PCIe bus as
The practical PCIe bus of target.
Can be selected in sequence, for example, first select practical PCIe bus 1, the practical PCIe bus 2 of selection,
Practical PCIe bus 3 is selected, practical PCIe bus 4 is finally selected.
Step 703: determining the parameter of the practical PCIe bus of target, and according to the parameter of the practical PCIe bus of target, testing
It demonstrate,proves and determines corresponding score group in plate, and the connection PCIe bus of the connector of score group and signal emitting plate is connected；
Select a test PCIe bus as target detection PCIe bus in score group.
Wherein, by taking practical PCIe bus corresponds to difference cabling pair as an example, which includes: the line width and difference of difference cabling
The spacing of cabling pair.
For example, practical PCIe bus 1 is corresponding with line group A, practical PCIe bus 2 is corresponding with line group B, and practical PCIe is total
Line 3 is corresponding with line group C, and practical PCIe bus 4 is corresponding with line group D.
In the present embodiment, it when PCIe bus is tested in selection for the first time in score group, can be provided according to SPCE range
Maximum length selected, for example, for maximum length as defined in the PCIe bus SPEC range on mainboard be 15mil, that
When selecting in score group, the test PCIe bus close or equal with 15mil can choose as target detection PCIe
Bus.
Step 704: the output end interface of target detection PCIe bus is connect with oscillograph.
Step 705: generating test signal using the signal transmitting terminal of signal emitting plate, and the test signal of generation is exported
Target detection PCIe bus is given, target detection PCIe bus exports the test signal received to the signal-testing apparatus.
Step 706: it is tested using signal integrity of the signal-testing apparatus to the test signal received, if
Test result is that signal integrity is unsatisfactory for requiring, then length is selected to be less than the length of target detection PCIe bus in score group
The test PCIe bus of degree executes step 704 for the test PCIe bus selected as target detection PCIe bus, until true
Until making final test PCIe bus；If test result meets the requirements for signal integrity, selected in score group
Length is greater than the test PCIe bus of the length of target detection PCIe bus, surveys the test PCIe bus selected as target
It tries PCIe bus and executes step 704, until determining final test PCIe bus.
Wherein, which is that the integrality of the signal of transmission is enabled to meet integrity demands
Maximum length.
Step 707: according to the length for connecting PCIe bus on the length of final test PCIe bus and signal emitting plate
Degree, determines the corresponding maximum length of the practical PCIe bus of target, and execute step 702, until needing to arrange in board to be built
The maximum length of the practical PCIe bus of each item be determined finishing, execute step 708.
Wherein, the corresponding maximum length of the practical PCIe bus of the target are as follows: the length of final test PCIe bus and company
Connect the sum of the length of PCIe bus.
Step 708: according to the maximum length of the practical PCIe bus of each determined, constructing corresponding board.
To sum up, each embodiment of the present invention it is at least specific as follows the utility model has the advantages that
1, in embodiments of the present invention, by the way that at least one line group is arranged in witness plate, at least one line group with to
It needs in at least one practical PCIe bus one-to-one correspondence and each line group of arrangement to include different length on building board
At least two test PCIe buses need the length of the practical PCIe bus of target of arrangement to be determined in board to be built
When, at least two test PCIe buses that can include according to score group corresponding with the practical PCIe bus of target, to signal
The test signal of expelling plate output is transmitted, to be surveyed using signal integrity of the signal-testing apparatus to test signal
Examination, and determine according to test result the final test PCIe bus for including in score group, so as to according to final
The length for testing PCIe bus determines that the practical PCIe bus of target that arrangement is needed on board to be built is meeting signal integrity
Under the premise of, the maximum length that can choose.
2, in embodiments of the present invention, it is ensured that a witness plate only need to be produced, it can be to institute on board to be built
The length of the practical PCIe bus of each item that need to be arranged is verified, and the witness plate not only can quickly determine target reality
The length of PCIe bus can also reduce cost, improve the accuracy rate that length determines.
3, in embodiments of the present invention, by the way that corresponding input end interface in each line group is integrated into a connection
Device can realize test alternatively, being a connector by the output end Interface integration in each line group in verification process
When the replacement of PCIe bus, the one end for not being connector need to only be plugged, so as to reduce verifying workload.
4, in embodiments of the present invention, by setting the lamination number of witness plate to and board same number to be built
Lamination, and the arrangement by include at least two test PCIe buses of line group on witness plate lamination, with the line group phase
It answers arrangement of the practical PCIe bus on board to be built identical, determines practical PCIe bus length so as to improve
Accuracy rate.
5, in embodiments of the present invention, by by the length of at least two in each line group test PCIe buses according to
Corresponding length threshold carries out gradient setting, thereby may be ensured that length definitive result is more accurate.
The contents such as the information exchange between each unit, implementation procedure in above-mentioned apparatus, due to implementing with the method for the present invention
Example is based on same design, and for details, please refer to the description in the embodiment of the method for the present invention, and details are not described herein again.
It should be noted that, in this document, such as first and second etc relational terms are used merely to an entity
Or operation is distinguished with another entity or operation, is existed without necessarily requiring or implying between these entities or operation
Any actual relationship or order.Moreover, the terms "include", "comprise" or its any other variant be intended to it is non-
It is exclusive to include, so that the process, method, article or equipment for including a series of elements not only includes those elements,
It but also including other elements that are not explicitly listed, or further include solid by this process, method, article or equipment
Some elements.In the absence of more restrictions, the element limited by sentence " including one ", is not arranged
Except there is also other identical factors in the process, method, article or apparatus that includes the element.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light
In the various media that can store program code such as disk.
Finally, it should be noted that the foregoing is merely presently preferred embodiments of the present invention, it is merely to illustrate skill of the invention
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made all within the spirits and principles of the present invention,
Equivalent replacement, improvement etc., are included within the scope of protection of the present invention.
Claims (10)
1. a kind of witness plate characterized by comprising at least one lamination and at least one line group；
At least one practical PCIe bus at least one described line group and external board to be built corresponds；
Each of at least one line group line group, comprising: at least two test PCIe buses；
At least two test PCIe bus arrangements that each line group includes are at least one described lamination；
At least two test PCIe buses that each line group includes correspond to different length；
The parameter for at least two test PCIe buses that each line group includes, practical PCIe bus corresponding with the line group
Parameter is identical；
Each tests PCIe bus, and one end receives the survey of the signal emitting plate input for connecting external signal expelling plate
Trial signal, the other end export the test signal to the signal-testing apparatus for connecting external signal test equipment.
2. witness plate according to claim 1, which is characterized in that
The number of at least one lamination is identical as the lamination number of board to be built；
Arrangement of at least two test PCIe buses that each line group includes at least one lamination, it is corresponding with line group
Arrangement of the practical PCIe bus on board to be created it is identical.
3. witness plate according to claim 1, which is characterized in that at least two test PCIe that each line group includes are total
The length of line is according to corresponding length threshold distribution gradient.
4. witness plate according to claim 1 to 3, which is characterized in that
Difference cabling clock synchronization is corresponded in the practical PCIe bus, the parameter includes: that the line width of difference cabling pair and difference are walked
The line spacing of line pair；
When the practical PCIe bus corresponds to single cabling, the parameter includes: the line width of single cabling.
5. a kind of verifying system characterized by comprising appoint in signal emitting plate, signal-testing apparatus and such as claim 1-4
Witness plate described in one；Wherein,
The signal emitting plate is connect with the target detection PCIe bus on the witness plate, for generating test signal, and will
The test signal of generation is exported to the target detection PCIe bus；
The signal-testing apparatus is connect with the target detection PCIe bus, for receiving the target detection PCIe bus
The test signal of output, and the signal integrity of the test signal received is tested.
6. verifying system according to claim 5, which is characterized in that the signal-testing apparatus includes: oscillograph；Its
In,
The oscillograph is connect with the target detection PCIe bus, for receiving the target detection PCIe bus output
Signal is tested, and according to the test signal received, generates corresponding eye figure.
7. verifying system according to claim 5, which is characterized in that the signal-testing apparatus, comprising: comparator；Its
In,
The comparator connect with the target detection PCIe bus, and connect with the signal emitting plate, for receiving
The test signal of target detection PCIe bus output is stated, and receives the test signal of the signal emitting plate output, and to institute
The test signal for stating the output of target detection PCIe bus is compared with the test signal that the signal emitting plate exports, and is exported
Comparison result.
8. according to the verifying system any in claim 5-7, which is characterized in that the verifying system further comprises:
Show equipment；Wherein,
The display equipment, connect with the signal-testing apparatus, for receiving the test knot of the signal-testing apparatus output
Fruit, and show the test result.
9. a kind of determination method of the PCIe bus based on the verifying system as described in any in claim 5-8, feature exist
In, comprising:
S1: the parameter that the practical PCIe bus of target of arrangement is needed in board to be built is determined；
S2: according to the parameter of the practical PCIe bus of the target, corresponding score group is determined in the witness plate, and in institute
It states selection target in score group and tests PCIe bus；
S3: the target detection bus is connect with the signal emitting plate and the signal-testing apparatus；
S4: test signal is generated using the signal emitting plate, the test signal of generation is exported to the target detection PCIe
Bus, the target detection PCIe bus export the test signal received to the signal-testing apparatus, utilize the letter
Number test equipment tests the signal integrity of the test signal received；
S5: according to the test result of the signal-testing apparatus, it is total that a test PCIe is reselected in the score group
This reselected is tested PCIe bus as target detection PCIe bus, continues to execute S3 by line, final until determining
Test PCIe bus when execute S6, the length of the final test PCIe bus is to meet letter in the score group
The maximum length of number integrality；
S6: it according to the length of the final test PCIe bus, determines that the practical PCIe bus of the target is corresponding and most greatly enhances
Degree.
10. the determination method of PCIe bus according to claim 9, which is characterized in that wrapped on the signal emitting plate
It is described according to the final test PCIe bus when including the connection PCIe bus connecting with the target detection PCIe bus
Length determines the corresponding maximum length of the practical PCIe bus of the target, comprising: it is practical to calculate the target using the first formula
The corresponding maximum length of PCIe bus；
First formula includes:
Lmax=L1+L2
Wherein, LmaxFor characterizing the corresponding maximum length of the practical PCIe bus of the target；L1For characterizing the final survey
Try the length of PCIe bus；L2For characterizing the length of the connection PCIe bus.
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| CN102650677A (en) * | 2011-02-25 | 2012-08-29 | 鸿富锦精密工业（深圳）有限公司 | Peripheral component interconnect-express (PCI-E) signal testing device |
| CN104133117A (en) * | 2014-08-08 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | Design for high-speed signal loss testing |
| CN105185414A (en) * | 2015-09-15 | 2015-12-23 | 北京京存技术有限公司 | Test method and test device |
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| US10162786B2 (en) * | 2014-12-01 | 2018-12-25 | SK Hynix Inc. | Storage node based on PCI express interface |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650677A (en) * | 2011-02-25 | 2012-08-29 | 鸿富锦精密工业（深圳）有限公司 | Peripheral component interconnect-express (PCI-E) signal testing device |
| CN104133117A (en) * | 2014-08-08 | 2014-11-05 | 浪潮电子信息产业股份有限公司 | Design for high-speed signal loss testing |
| CN105185414A (en) * | 2015-09-15 | 2015-12-23 | 北京京存技术有限公司 | Test method and test device |
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