CN105679690B - The method for improving test wafer service life - Google Patents
The method for improving test wafer service life Download PDFInfo
- Publication number
- CN105679690B CN105679690B CN201610056903.0A CN201610056903A CN105679690B CN 105679690 B CN105679690 B CN 105679690B CN 201610056903 A CN201610056903 A CN 201610056903A CN 105679690 B CN105679690 B CN 105679690B
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- test
- wafer
- service life
- test wafer
- probe station
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention proposes a kind of methods for improving test wafer service life, test wafer is subjected to region and partial region is tested, after relevance verification test wafer is tested multiple, partial region needle tracking, which becomes larger, to be deepened, when can not carry out relevance verification next time, region can be replaced and carry out relevance verification, to increase the service life of test wafer, since institute's quantity to be tested reduces in domain test, testing efficiency can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of methods for improving test wafer service life.
Background technique
It is testing in factory, it usually needs relevance verification is carried out to DC (direct current) parameter of a product, such as is kept
Test machine is constant, changes different probe cards to examine whether this probe card meets test request, can also keep probe card not
Become, examines whether this test machine can test this product with different test machines.
Method at present is that full wafer wafer is carried out to a DC test from the beginning to the end, compares the good of two wafers after the completion
Rate and DC parameter, to determine whether relevance verification is qualified.Specifically, including two ways:
One, full wafer wafer is tested
Current relevance verification is all that full wafer wafer all needs to test, and the time of cost is longer, and wafer size is increasing,
Tube core number is more and more, and later relevance verification can be slower and slower, and efficiency is worse and worse；
Two, full wafer wafer is repeatedly tested
The wafer for doing relevance verification is often specially to do the wafer of relevance verification with a piece of, after multiple full wafer test,
Will cause needle tracking to be difficult to distinguish, in addition will affect relevance verification as a result, the purpose for doing relevance verification is not achieved.
Moreover, the size of wafer is increasing now, tube core number is also more and more, and it is very long to be bound to cause the testing time,
The efficiency of volume production can be largely effected on for test factory.
Summary of the invention
The purpose of the present invention is to provide a kind of methods for improving test wafer service life, are able to solve the testing time
It is long, and needle tracking is not easily controlled, the problem for causing test wafer service life short.
To achieve the goals above, the invention proposes a kind of methods for improving test wafer service life, comprising steps of
Test wafer is subjected to subregion, is divided into several regions；
Part of region is tested, until needle tracking can not distinguish, then replaces domain test.
Further, in the method for the raising test wafer service life, test wafer is subjected to equal part.
Further, in the method for the described raising test wafer service life, by the region be divided into first part,
Second part and Part III.
Further, in the method for the described raising test wafer service life, the first part is first tested, when the
A part of needle tracking can not distinguish, second part described in re-test, when second part needle tracking can not distinguish, third portion described in re-test
Point.
Further, in the method for the raising test wafer service life, include by test wafer progress subregion
Step: using additional probe station setting area, saves setting.
Compared with prior art, the beneficial effects are mainly reflected as follows: test wafer is subjected to region and to part
Domain test, after relevance verification test wafer is tested multiple, partial region needle tracking, which becomes larger, to be deepened, and can not be carried out next time
When relevance verification, region can be replaced and carry out relevance verification, to increase the service life of test wafer, since region is surveyed
Institute's quantity to be tested reduces in examination, can be improved testing efficiency.
Detailed description of the invention
Fig. 1 is the flow chart that the method for test wafer service life is improved in one embodiment of the invention；
Fig. 2 is the schematic diagram in one embodiment of the invention after test wafer subregion；
Fig. 3 to Fig. 5 is the schematic diagram in one embodiment of the invention in test process.
Specific embodiment
It is described in more detail below in conjunction with method of the schematic diagram to raising test wafer service life of the invention,
Which show the preferred embodiment of the present invention, it should be appreciated that and those skilled in the art can modify invention described herein,
And still realize advantageous effects of the invention.Therefore, following description should be understood as the extensive of those skilled in the art
Know, and is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Referring to FIG. 1, in the present embodiment, a kind of method for improving test wafer service life is proposed, comprising steps of
S100: test wafer is subjected to subregion, is divided into several regions；
S200: testing part of region, until needle tracking can not distinguish, then replaces domain test.
Referring to FIG. 2, in the present embodiment, test wafer can be carried out equal part；It is respectively divided into first part 1, second
Part 2 and Part III 3 certainly, can also be without equal parts in the other embodiments except the present embodiment, or are divided into
Multiple portions are not limited only to 3 parts.Specific subregion can be carried out according to actual requirement, such as according to the arrangement feelings of needle card
Condition arbitrarily divides range, and the present embodiment is only a kind of example.
Specifically, each product has a corresponding spy since all wafers are tested on probe station
The setting of needle platform calls corresponding setting to can be carried out volume production when testing every time, wafer subregion is by additionally adding a probe station
It is arranged and predefines equal part or partitioned area, carries out next time calling directly the setting when relevance verification, pass through probe
Platform calls the incorrect, test scope of setting the problems such as there are deviations caused by also can avoid repeatedly test.
After subregion completion, the first part 1 is first tested, as shown in figure 3, when 1 needle tracking of first part can not distinguish,
Second part 2 described in re-test, as shown in figure 4, when 2 needle tracking of second part can not distinguish, Part III 3 described in re-test, such as
Shown in Fig. 5.
Specifically, needle tracking, which becomes larger, to be deepened when being difficult to differentiate after relevance verification wafer is repeatedly tested, it can be deleted
The subregional probe station setting such as used in preceding, does a unduplicated probe station setting again, and such needle tracking becomes again
It is high-visible, that is, it ensure that the requirement of needle tracking, also improve the reliability of relevance verification, more shorten needed for relevance verification
Time.
For DC test, relevance verification is carried out by wafer equisection method, has maintained correlation to greatest extent
Property verifying accuracy, and the least equal part of probe station walking can be manufactured according to the arranged distribution of probe card
Testing time and probe station walking time is greatly saved in space.
This technology invention carries out DC by wafer equisection method and tests relevance verification, shortens the testing time, improves correlation
Verification efficiency, flexible choice region guarantee the needle tracking quality of wafer, verifying reliability are improved, since DC parameter testing mode is simpler
It is single, so the accuracy of relevance verification can't be reduced because of the reduction of sample.
To sum up, in the method provided in an embodiment of the present invention for improving test wafer service life, test wafer is carried out
Partial region is simultaneously tested in region, and after relevance verification test wafer is tested multiple, partial region needle tracking, which becomes larger, to be deepened, nothing
When method carries out relevance verification next time, region can be replaced and carry out relevance verification, to increase the use longevity of test wafer
Life can be improved testing efficiency since institute's quantity to be tested reduces in domain test.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (5)
1. a kind of method for improving test wafer service life, which is characterized in that comprising steps of
Test wafer is subjected to subregion, is divided into several regions；
Part of region is tested, until needle tracking can not distinguish, then replaces domain test；Chip pair on each wafer
A probe station setting is answered, additionally plus a probe station setting determines the region, calls directly described when testing next time
Probe station setting；After relevance verification wafer is repeatedly tested, needle tracking, which becomes larger, to be deepened when being difficult to differentiate, institute before can deleting
The probe station in the region used is arranged, and does a unduplicated probe station setting again；
One probe station is manufactured according to the arranged distribution of probe card by the relevance verification that wafer equisection method carries out DC test
The least equal part space of walking.
2. improving the method for test wafer service life as described in claim 1, which is characterized in that carry out test wafer etc.
Point.
3. improving the method for test wafer service life as described in claim 1, which is characterized in that the region is divided into the
A part, second part and Part III.
4. improving the method for test wafer service life as claimed in claim 3, which is characterized in that first test described first
Point, when first part's needle tracking can not distinguish, second part described in re-test, when second part needle tracking can not distinguish, re-test institute
State Part III.
5. improving the method for test wafer service life as described in claim 1, which is characterized in that divided test wafer
Area saves setting comprising steps of using additional probe station setting area.
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| CN201610056903.0A CN105679690B (en) | 2016-01-27 | 2016-01-27 | The method for improving test wafer service life |
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| CN105679690A CN105679690A (en) | 2016-06-15 |
| CN105679690B true CN105679690B (en) | 2019-04-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108400098A (en) * | 2017-02-08 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | The method for verifying wafer test correlation |
| CN109188331A (en) * | 2018-09-07 | 2019-01-11 | 德淮半导体有限公司 | The method of calibration of test framework calculates equipment and check system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102162831A (en) * | 2011-03-15 | 2011-08-24 | 上海宏力半导体制造有限公司 | Detection method of wafer parameters |
| CN105242192A (en) * | 2015-10-09 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000014209A (en) * | 1998-08-18 | 2000-03-06 | 윤종용 | Wafer probing method using wafer probe station |
| JP4177162B2 (en) * | 2003-05-02 | 2008-11-05 | Ｊｕｋｉ株式会社 | Sewing machine feeder |
| CN101452027B (en) * | 2007-11-30 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer shipment quality guarantee detecting method |
| JP2009222495A (en) * | 2008-03-14 | 2009-10-01 | Jsr Corp | Wafer tester |
| CN104977518B (en) * | 2014-04-09 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer shipment inspection method |
| CN204361056U (en) * | 2015-01-21 | 2015-05-27 | 上海微世半导体有限公司 | Multiprobe timing sequence test point measurement machine |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102162831A (en) * | 2011-03-15 | 2011-08-24 | 上海宏力半导体制造有限公司 | Detection method of wafer parameters |
| CN105242192A (en) * | 2015-10-09 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
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