CN110061620A - A kind of negative pressure charge pump circuit - Google Patents
A kind of negative pressure charge pump circuit Download PDFInfo
- Publication number
- CN110061620A CN110061620A CN201910486642.XA CN201910486642A CN110061620A CN 110061620 A CN110061620 A CN 110061620A CN 201910486642 A CN201910486642 A CN 201910486642A CN 110061620 A CN110061620 A CN 110061620A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- circuit
- transistor
- pmos transistor
- nmos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of negative pressure charge pump circuits, the auxiliary transistor of the circuit substitutes the PMOS transistor in four phase clock charge pump circuit of traditional negative pressure using NMOS transistor, and transmission transistor still uses PMOS transistor, simultaneously using two-way dislocation clock driver circuit, circuit output end then uses double branch negative pressure charge pumps in parallel.Using technical solution of the present invention, the loss of threshold voltage is eliminated by its circuit structure, the delivery efficiency of charge pump circuit is effectively raised, reduces output voltage ripple, shortens the time for reaching identical voltage, is suitable for memory circuit.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly, to a kind of negative pressure charge pump circuit.
Background technique
With the fast development of system on chip, the continuous diminution of technique node, the transistor size in memory circuit
Also smaller and smaller, pressure resistance is also lower and lower.The design of negative pressure charge pump is to execute the programming and wiping of high voltage in memory
When except work, does not change between port under conditions of potential difference, reduce the absolute value of voltage, design extends basic unit of storage
Service life, improve the reliability of memory, therefore the research of negative pressure charge pump is most important.
Traditional four phase clock charge pump of negative pressure uses PMOS technology, when auxiliary transistor and transmission transistor are all made of
When PMOS transistor, 0 potential voltage is slow to the negative voltage raised time, and the output voltage efficiency of circuit is lower.
Summary of the invention
The present invention provides that a kind of loss of threshold voltage is small, voltage falling time is fast, output voltage is lower, is suitable for memory
The negative pressure charge pump circuit of circuit.
In order to solve the above technical problems, technical scheme is as follows:
A kind of negative pressure charge pump circuit is used in memory, including first voltage transmission circuit and clock driving, in which:
The input terminal of first voltage transmission circuit is electrically connected with 0 current potential, the output voltage after output end output buck, described
First voltage transmission circuit includes several grades of decompression sub-circuits and the first output sub-circuit, is gone here and there between every level-one decompression sub-circuit
The input terminal of connection, first order decompression sub-circuit is electrically connected with 0 current potential, and afterbody is depressured output end and the first output of sub-circuit
The input terminal of sub-circuit is electrically connected, the output voltage after the output end output buck of the first output sub-circuit, every level-one decompression
It include the NMOS transistor as auxiliary transistor and the PMOS transistor as transmission transistor in circuit；
The clock driving includes several clock signals with out of phase, each with first voltage transmission circuit respectively
Grade decompression sub-circuit and output sub-circuit electrical connection, for the clock signal state of conversion circuit, change simultaneously circuit voltage.
It preferably, further include second voltage transmission circuit, the second voltage transmission circuit and first voltage transmission circuit
Parallel connection, the second voltage transmission circuit include several grades of decompression sub-circuits and the second output sub-circuit, every level-one decompression son electricity
Connect between road, the first order decompression sub-circuit input terminal be electrically connected with 0 current potential, afterbody decompression sub-circuit output end and
The input terminal electrical connection of second output sub-circuit, second exports the output voltage after the output end output buck of sub-circuit, decompression
It include the NMOS transistor as auxiliary transistor and the PMOS transistor as transmission transistor, the clock in sub-circuit
Driving is also electrically connected with the decompression sub-circuits at different levels of second voltage transmission circuit and the second output sub-circuit respectively, using double branches
Negative pressure charge pump circuit parallel connection is exported, and can reduce the voltage output period, to reduce output voltage ripple.
Preferably, first voltage transmission circuit includes level Four decompression sub-circuit, and second voltage transmission circuit includes level Four drop
Sub-circuit is pressed, the clock driving includes four clock signals clkA, clkB, clkC and the clkD with out of phase, is used
The sequential relationship of dislocation, can be preferably by voltage output to more negative value, and then improves the delivery efficiency of circuit.
Preferably, the first voltage transmission circuit include as auxiliary transistor the first NMOS transistor, second
NMOS transistor, third NMOS transistor and the 4th NMOS transistor, as transmission transistor the first PMOS transistor, second
PMOS transistor, third PMOS transistor and the 4th PMOS transistor, as the 5th PMOS transistor of output stage, the 5th NMOS
Transistor, as the first capacitor of auxiliary capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, as pumping electricity
The 6th capacitor, the 7th capacitor, the 8th capacitor, the 9th capacitor held, in which:
The drain electrode of first PMOS transistor and the source electrode of the first NMOS transistor are electrically connected with 0 current potential；2nd PMOS crystal
The drain electrode of pipe, the source electrode of the second NMOS transistor, the grid of the first NMOS transistor, the source electrode of the first PMOS transistor and the 6th
Capacitor one end interconnects and forms node N1 in junction；The drain electrode of third PMOS transistor, third NMOS transistor source
The source electrode of pole, the grid of the second NMOS transistor and the second PMOS transistor is electrically connected and with one end of the 7th capacitor in junction
Form node N2；The drain electrode of 4th PMOS transistor, the source electrode of the 4th NMOS transistor, the grid of third NMOS transistor and
The source electrode of three PMOS transistors is electrically connected with one end of the 8th capacitor and forms node N3 in junction；5th PMOS transistor
It drains, the source electrode and the 9th capacitor of the grid of the 4th NMOS transistor of source electrode of the 5th NMOS transistor and the 4th PMOS transistor
One end electrical connection simultaneously forms node N4 in junction；The source electrode of 5th PMOS transistor is electrically connected with circuit output end；
The drain electrode of first NMOS transistor and the grid of the first PMOS transistor and one end of first capacitor be electrically connected and
Junction forms node N5；One end electricity of the drain electrode of second NMOS transistor and the grid of the second PMOS transistor and the second capacitor
It connects and forms node N6 in junction；The drain electrode of third NMOS transistor and the grid of third PMOS transistor and third capacitor
One end electrical connection and junction formed node N7；4th NMOS transistor drain electrode and the 4th PMOS transistor grid and
One end of 4th capacitor is electrically connected and forms node N8 in junction；The drain electrode and the 5th PMOS transistor of 5th NMOS transistor
Grid be electrically connected with one end of the 5th capacitor and junction formed node N9；
First PMOS transistor, the first NMOS transistor, first capacitor, the 6th capacitor form first voltage transmission circuit
The first order is depressured sub-circuit, and the second PMOS transistor, the second NMOS transistor, the second capacitor, the 7th capacitor form first voltage
The second level of transmission circuit is depressured sub-circuit, third PMOS transistor, third NMOS transistor, third capacitor, the 8th capacitance group
At first voltage transmission circuit the third level be depressured sub-circuit, the 4th PMOS transistor, the 4th NMOS transistor, the 4th capacitor,
9th capacitor form first voltage transmission circuit the fourth stage be depressured sub-circuit, the 5th PMOS transistor, the 5th NMOS transistor,
5th capacitor forms the first output sub-circuit of first voltage transmission circuit.
Preferably, the second voltage transmission circuit include as auxiliary transistor the 6th NMOS transistor, the 7th
NMOS transistor, the 8th NMOS transistor and the 9th NMOS transistor, as transmission transistor the 6th PMOS transistor, the 7th
PMOS transistor, the 8th PMOS transistor and the 9th PMOS transistor, as the tenth PMOS transistor of output stage and the tenth
NMOS transistor, the 11st capacitor, the 12nd capacitor, the 13rd capacitor, the 14th capacitor and the 15th as auxiliary capacitor
Capacitor, the 16th capacitor, the 17th capacitor, the 18th capacitor and the 19th capacitor as pumping capacitor, in which:
The drain electrode of 6th PMOS transistor, the source electrode of the 6th NMOS transistor are connected with 0 current potential of input terminal；7th NMOS
The source electrode of transistor, the drain electrode of the 7th PMOS transistor, the grid of the 6th NMOS transistor and the source electrode of the 6th PMOS transistor
It is electrically connected with one end of the 16th capacitor and forms node M 1 in junction；Source electrode, the 8th PMOS of 8th NMOS transistor are brilliant
The source electrode of the drain electrode of body pipe, the grid of the 7th NMOS transistor and the 7th PMOS transistor is electrically connected with one end of the 17th capacitor
And node M 2 is formed in junction；The source electrode of 9th NMOS transistor, the drain electrode of the 9th PMOS transistor, the 8th NMOS transistor
Grid and the 8th PMOS transistor source electrode be electrically connected with one end of the 18th capacitor and junction formed node M 3；Tenth
The source electrode of NMOS transistor, the drain electrode of the tenth PMOS transistor, the grid of the 9th NMOS transistor, the 9th PMOS transistor source
The grid of pole and the 5th NMOS transistor is electrically connected with one end of the 19th capacitor and forms node M 4 in junction；
The drain electrode of 6th NMOS transistor and the grid of the 6th PMOS transistor are electrically connected simultaneously with one end of the 11st capacitor
Node M 5 is formed in junction；7th NMOS transistor drain electrode and the 7th PMOS transistor grid and the 12nd capacitor one
End electrical connection simultaneously forms node M 6 in junction；The drain electrode of 8th NMOS transistor and the grid and the tenth of the 8th PMOS transistor
One end of three capacitors is electrically connected and forms node M 7 in junction；The drain electrode of 9th NMOS transistor and the 9th PMOS transistor
Grid is electrically connected with one end of the 14th capacitor and forms node M 8 in junction；The drain electrode and the tenth of tenth NMOS transistor
The grid of PMOS transistor is electrically connected with one end of the 15th capacitor and forms node M 9 in junction；
6th PMOS transistor, the 6th NMOS transistor, the 11st capacitor, the 16th capacitor composition second voltage transmission electricity
The first order on road is depressured sub-circuit, the 7th PMOS transistor, the 7th NMOS transistor, the 12nd capacitor, the 17th capacitor composition
The second level of second voltage transmission circuit is depressured sub-circuit, the 8th PMOS transistor, the 8th NMOS transistor, the 13rd capacitor,
The third level that 18th capacitor forms second voltage transmission circuit is depressured sub-circuit, the 9th PMOS transistor, the 9th NMOS crystal
The fourth stage decompression sub-circuit of pipe, the 14th capacitor, the 19th capacitor composition second voltage transmission circuit, the tenth PMOS crystal
Second output sub-circuit of pipe, the tenth NMOS transistor, the 15th capacitor composition second voltage transmission circuit.
Preferably, the clock signal clkA respectively with the other end of the second capacitor, the other end of the 4th capacitor, the 11st
The other end of the other end of capacitor, the other end of the 13rd capacitor and the 15th capacitor is electrically connected；Clock signal clkB respectively with
The other end of 7th capacitor, the other end, the other end of the 16th capacitor and the other end of the 18th capacitor of the 9th capacitor are electrically connected
It connects；Clock signal clkC respectively with the other end of first capacitor, the other end of third capacitor, the other end of the 5th capacitor, the tenth
The electrical connection of the other end of the other end of two capacitors and the 14th capacitor；Clock signal clkD respectively with the other end of the 6th capacitor,
The other end, the other end of the 17th capacitor and the other end of the 19th capacitor of 8th capacitor are connected.
Preferably, the voltage magnitude of described four clock signals clkA, clkB, clkC and clkD are equal to memory power electricity
Pressure has different time delays.
Compared with prior art, the beneficial effect of technical solution of the present invention is:
The auxiliary transistor of charge pump circuit substitutes traditional four phase clock charge pumps using NMOS transistor in the present invention
In PMOS transistor, and transmission transistor use PMOS transistor.The loss that threshold voltage is eliminated by circuit structure, has
Charge pump circuit is reduced to more negative voltage from 0 potential voltage by effect step by step, improves circuit output efficiency.The present invention simultaneously
Under the conditions of identical with traditional four phase clock charge pump of negative pressure, the time for reaching identical voltage is shorter.
Detailed description of the invention
Fig. 1 is negative pressure charge pump circuit schematic diagram of the present invention；
Fig. 2 is traditional four phase clock charge pump circuit schematic diagram of negative pressure；
Fig. 3 is the clock signal time diagram of negative pressure charge pump circuit of the present invention；
Fig. 4 is of the invention and the emulation comparison result figure of tradition four phase clock charge pump circuit of negative pressure, in figure, con table
Show traditional four phase clock charge pump simulation result of negative pressure, new negative pressure charge pump simulation result of the present invention.
Specific embodiment
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent；
In order to better illustrate this embodiment, the certain components of attached drawing have omission, zoom in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be understood that certain known features and its explanation, which may be omitted, in attached drawing
's.
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
Embodiment 1
A kind of negative pressure charge pump circuit is used in memory, including first voltage transmission circuit and clock driving, in which:
The input terminal of first voltage transmission circuit is electrically connected with 0 current potential, the output voltage after output end output buck, described
First voltage transmission circuit includes several grades of decompression sub-circuits and the first output sub-circuit, is gone here and there between every level-one decompression sub-circuit
The input terminal of connection, first order decompression sub-circuit is electrically connected with 0 current potential, and afterbody is depressured output end and the first output of sub-circuit
The input terminal of sub-circuit is electrically connected, the output voltage after the output end output buck of the first output sub-circuit, every level-one decompression
It include the NMOS transistor as auxiliary transistor and the PMOS transistor as transmission transistor in circuit；
The clock driving includes several clock signals with out of phase, each with first voltage transmission circuit respectively
Grade decompression sub-circuit and output sub-circuit electrical connection, for the clock signal state of conversion circuit, change simultaneously circuit voltage.
It further include second voltage transmission circuit, the second voltage transmission circuit is in parallel with first voltage transmission circuit, institute
Stating second voltage transmission circuit includes several grades of decompression sub-circuits and the second output sub-circuit, is gone here and there between every level-one decompression sub-circuit
The input terminal of connection, first order decompression sub-circuit is electrically connected with 0 current potential, and afterbody is depressured output end and the second output of sub-circuit
The input terminal of sub-circuit is electrically connected, and the output voltage after the output end output buck of the second output sub-circuit is depressured in sub-circuit
Including the NMOS transistor as auxiliary transistor and as the PMOS transistor of transmission transistor, the clock driving also divides
It is not electrically connected with the decompression sub-circuits at different levels of second voltage transmission circuit and the second output sub-circuit, using double branch negative pressure charges
Pump circuit parallel connection is exported, and can reduce the voltage output period, to reduce output voltage ripple.
First voltage transmission circuit includes level Four decompression sub-circuit, and second voltage transmission circuit includes level Four decompression son electricity
Road, the clock driving includes four clock signals clkA, clkB, clkC and the clkD with out of phase, using dislocation
Sequential relationship, can be preferably by voltage output to more negative value, and then improves the delivery efficiency of circuit.
The first voltage transmission circuit includes the first NMOS transistor, the 2nd NMOS crystal as auxiliary transistor
Pipe, third NMOS transistor and the 4th NMOS transistor, the first PMOS transistor, the 2nd PMOS crystal as transmission transistor
Pipe, third PMOS transistor and the 4th PMOS transistor, as the 5th PMOS transistor of output stage, the 5th NMOS transistor,
As the first capacitor of auxiliary capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, as pumping capacitor the 6th
Capacitor, the 7th capacitor, the 8th capacitor, the 9th capacitor, in which:
The drain electrode of first PMOS transistor and the source electrode of the first NMOS transistor are electrically connected with 0 current potential；2nd PMOS crystal
The drain electrode of pipe, the source electrode of the second NMOS transistor, the grid of the first NMOS transistor, the source electrode of the first PMOS transistor and the 6th
Capacitor one end interconnects and forms node N1 in junction；The drain electrode of third PMOS transistor, third NMOS transistor source
The source electrode of pole, the grid of the second NMOS transistor and the second PMOS transistor is electrically connected and with one end of the 7th capacitor in junction
Form node N2；The drain electrode of 4th PMOS transistor, the source electrode of the 4th NMOS transistor, the grid of third NMOS transistor and
The source electrode of three PMOS transistors is electrically connected with one end of the 8th capacitor and forms node N3 in junction；5th PMOS transistor
It drains, the source electrode and the 9th capacitor of the grid of the 4th NMOS transistor of source electrode of the 5th NMOS transistor and the 4th PMOS transistor
One end electrical connection simultaneously forms node N4 in junction；The source electrode of 5th PMOS transistor is electrically connected with circuit output end；
The drain electrode of first NMOS transistor and the grid of the first PMOS transistor and one end of first capacitor be electrically connected and
Junction forms node N5；One end electricity of the drain electrode of second NMOS transistor and the grid of the second PMOS transistor and the second capacitor
It connects and forms node N6 in junction；The drain electrode of third NMOS transistor and the grid of third PMOS transistor and third capacitor
One end electrical connection and junction formed node N7；4th NMOS transistor drain electrode and the 4th PMOS transistor grid and
One end of 4th capacitor is electrically connected and forms node N8 in junction；The drain electrode and the 5th PMOS transistor of 5th NMOS transistor
Grid be electrically connected with one end of the 5th capacitor and junction formed node N9；
First PMOS transistor, the first NMOS transistor, first capacitor, the 6th capacitor form first voltage transmission circuit
The first order is depressured sub-circuit, and the second PMOS transistor, the second NMOS transistor, the second capacitor, the 7th capacitor form first voltage
The second level of transmission circuit is depressured sub-circuit, third PMOS transistor, third NMOS transistor, third capacitor, the 8th capacitance group
At first voltage transmission circuit the third level be depressured sub-circuit, the 4th PMOS transistor, the 4th NMOS transistor, the 4th capacitor,
9th capacitor form first voltage transmission circuit the fourth stage be depressured sub-circuit, the 5th PMOS transistor, the 5th NMOS transistor,
5th capacitor forms the first output sub-circuit of first voltage transmission circuit.
The second voltage transmission circuit includes the 6th NMOS transistor, the 7th NMOS crystal as auxiliary transistor
Pipe, the 8th NMOS transistor and the 9th NMOS transistor, as the 6th PMOS transistor of transmission transistor, the 7th PMOS crystal
Pipe, the 8th PMOS transistor and the 9th PMOS transistor, as the tenth PMOS transistor of output stage and the tenth NMOS transistor,
As the 11st capacitor, the 12nd capacitor, the 13rd capacitor, the 14th capacitor and the 15th capacitor of auxiliary capacitor, as pump
The 16th capacitor, the 17th capacitor, the 18th capacitor and the 19th capacitor of Pu capacitor, in which:
The drain electrode of 6th PMOS transistor, the source electrode of the 6th NMOS transistor are connected with 0 current potential of input terminal；7th NMOS
The source electrode of transistor, the drain electrode of the 7th PMOS transistor, the grid of the 6th NMOS transistor and the source electrode of the 6th PMOS transistor
It is electrically connected with one end of the 16th capacitor and forms node M 1 in junction；Source electrode, the 8th PMOS of 8th NMOS transistor are brilliant
The source electrode of the drain electrode of body pipe, the grid of the 7th NMOS transistor and the 7th PMOS transistor is electrically connected with one end of the 17th capacitor
And node M 2 is formed in junction；The source electrode of 9th NMOS transistor, the drain electrode of the 9th PMOS transistor, the 8th NMOS transistor
Grid and the 8th PMOS transistor source electrode be electrically connected with one end of the 18th capacitor and junction formed node M 3；Tenth
The source electrode of NMOS transistor, the drain electrode of the tenth PMOS transistor, the grid of the 9th NMOS transistor, the 9th PMOS transistor source
The grid of pole and the 5th NMOS transistor is electrically connected with one end of the 19th capacitor and forms node M 4 in junction；
The drain electrode of 6th NMOS transistor and the grid of the 6th PMOS transistor are electrically connected simultaneously with one end of the 11st capacitor
Node M 5 is formed in junction；7th NMOS transistor drain electrode and the 7th PMOS transistor grid and the 12nd capacitor one
End electrical connection simultaneously forms node M 6 in junction；The drain electrode of 8th NMOS transistor and the grid and the tenth of the 8th PMOS transistor
One end of three capacitors is electrically connected and forms node M 7 in junction；The drain electrode of 9th NMOS transistor and the 9th PMOS transistor
Grid is electrically connected with one end of the 14th capacitor and forms node M 8 in junction；The drain electrode and the tenth of tenth NMOS transistor
The grid of PMOS transistor is electrically connected with one end of the 15th capacitor and forms node M 9 in junction；
6th PMOS transistor, the 6th NMOS transistor, the 11st capacitor, the 16th capacitor composition second voltage transmission electricity
The first order on road is depressured sub-circuit, the 7th PMOS transistor, the 7th NMOS transistor, the 12nd capacitor, the 17th capacitor composition
The second level of second voltage transmission circuit is depressured sub-circuit, the 8th PMOS transistor, the 8th NMOS transistor, the 13rd capacitor,
The third level that 18th capacitor forms second voltage transmission circuit is depressured sub-circuit, the 9th PMOS transistor, the 9th NMOS crystal
The fourth stage decompression sub-circuit of pipe, the 14th capacitor, the 19th capacitor composition second voltage transmission circuit, the tenth PMOS crystal
Second output sub-circuit of pipe, the tenth NMOS transistor, the 15th capacitor composition second voltage transmission circuit.
The clock signal clkA respectively with the other end of the second capacitor, the other end of the 4th capacitor, the 11st capacitor
The other end of the other end, the other end of the 13rd capacitor and the 15th capacitor is electrically connected；Clock signal clkB is electric with the 7th respectively
The other end electrical connection of the other end of appearance, the other end of the 9th capacitor, the other end of the 16th capacitor and the 18th capacitor；Clock
Signal clkC respectively with the other end of first capacitor, the other end of third capacitor, the other end of the 5th capacitor, the 12nd capacitor
The electrical connection of the other end of the other end and the 14th capacitor；Clock signal clkD respectively with the other end of the 6th capacitor, the 8th capacitor
The other end, the other end of the 17th capacitor and the other end of the 19th capacitor be connected.
The voltage magnitude of described four clock signals clkA, clkB, clkC and clkD are equal to memory power voltage, have
Different time delays.
In the specific implementation process, as shown in Figure 1, for the above branch, the drain electrode of the first PMOS transistor NP1, first
The source electrode of NMOS transistor NN1 is connected with 0 current potential of input terminal；The drain electrode of second PMOS transistor NP2, the second NMOS transistor
The source electrode of NN2, the grid of NN1, the source electrode of NP1 and the 6th one end capacitor C6 interconnect and form node N1 in junction；The
The drain electrode of three PMOS transistor NP3, the source electrode of third NMOS transistor NN3, the grid of NN2, the source electrode of NP2 and the 7th capacitor C7
One end interconnects and forms node N2 in junction；The drain electrode of 4th PMOS transistor NP4, the 4th NMOS transistor NN4
Source electrode, the grid of NN3, the source electrode of NP3 and the 8th one end capacitor C8 interconnect and form node N3 in junction；5th PMOS
The drain electrode of transistor NP5, the source electrode of the 5th NMOS transistor NN5, the grid of NN4, the source electrode of NP4 and the 9th one end capacitor C9 are mutual
It is connected and forms node N4 in junction；The source electrode of NP5, the tenth load capacitance one end and circuit output end are connected with each other.NN1
Drain electrode, NP1 grid and the one end first capacitor C1 be connected with each other and junction formed node N5；The drain electrode of NN2, NP2
Grid and second one end capacitor C2 are connected with each other and form node N6 in junction；The drain electrode of NN3, the grid of NP3 and third electricity
Hold one end to be connected with each other and form node N7 in junction；The drain electrode of NN4, the grid of NP4 and the 4th one end capacitor C4 mutually interconnect
It connects and forms node N8 in junction；The drain electrode of NN5, the grid of NP5 and the 5th one end capacitor C5 are connected with each other and in junctions
Form node N9.The voltage clock signal conversion circuit is by four kinds of clock signals clkA, clkB, clkC with out of phase
And clkD, the clock signal clkA are connected with the one end capacitor C2, the one end capacitor C4；Clock signal clkB and capacitor C7 mono-
End, the one end capacitor C9 are connected；Clock signal clkC is connected with the one end capacitor C1, the one end capacitor C3, the one end capacitor C5；Clock
Signal clkD is connected with the one end capacitor C6, the one end capacitor C8.
The structures of traditional four phase clock charge pump circuits is as shown in Fig. 2, difference with traditional four phase clock charge pumps
It is, in the present embodiment, the auxiliary transistor of charge pump circuit substitutes traditional four phase clock charges using NMOS transistor
PMOS transistor in pump, and transmission transistor uses PMOS transistor.The present embodiment is effectively by the voltage of charge pump circuit
It is output to more negative value, shortens the time for reaching identical voltage, is suitable for memory circuit.
The timing diagram of the four kinds of clock signals used in the present embodiment is as shown in figure 3, the timing to be misplaced using such two-way
Relationship, can be preferably by voltage output to more negative value, and then improves the delivery efficiency of circuit.
A kind of working principle for negative pressure charge pump circuit that the present embodiment is proposed specifically:
By taking the 2nd grade of the upper branch of charge pump circuit and 3rd level as an example, clock signal is divided into 8 moment.In T1
It carving, clkA becomes low potential from high potential, and the voltage of node N6 reduces, and the voltage of thus pulling down node N1 is understood in the conducting of NN2 pipe,
NP2 pipe is in the conductive state simultaneously, and the charge of node N2 is transmitted to node N1, and the voltage of node N2 reduces.At the T2 moment,
ClkA becomes high potential from low potential, and the voltage of node N6 increases, and NP2 pipe ends at this time, and the voltage of node N2 is no longer to node
N1 transmission.At the T3 moment, clkB becomes low potential from high potential, the voltage of node N2 after the decline of previous process again into
Row reduces.At the T4 moment, clkD becomes high potential, the voltage raising of node N1 and node N3, node N1 and node from low potential
N3 prepares to carry out charge transmission reduction voltage to previous stage.At the T5 moment, clkC becomes low potential from high potential, with T1 moment class
Seemingly, the voltage of node N7 reduces, the conducting of NN3 pipe, can thus pulling down node N2 voltage, while NP3 pipe is in the conductive state, section
The charge of point N3 is transmitted to node N2, and the voltage of node N3 reduces.At the T6 moment, clkC becomes high potential from low potential,
The voltage of node N7 increases, and NP3 pipe is in off state at this time, and the charge of node N3 is no longer transmitted to node N2.At the T7 moment,
ClkD becomes low potential from high potential, and the voltage of node N3 is reduced again after the decline of previous process, while node
The voltage of N1 also reduces.At the T8 moment, clkB becomes high potential from low potential, and the voltage of node N2 increases, prepares to previous stage
Carrying out charge transmission reduces voltage.
It is exported using double branch negative pressure charge pump circuit parallel connections, can reduce the voltage output period, to reduce defeated
Voltage ripple out.
The emulation comparison result of four phase clock charge pump circuit of the present embodiment and traditional negative pressure is as shown in figure 4, this implementation
When example is identical with the simulated conditions of four phase clock charge pump circuit of traditional negative pressure, the output voltage of the present embodiment is more negative,
The time for reaching identical voltage is shorter.
The same or similar label correspond to the same or similar components；
The terms describing the positional relationship in the drawings are only for illustration, should not be understood as the limitation to this patent；
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention
Protection scope within.
Claims (7)
1. a kind of negative pressure charge pump circuit, in memory, which is characterized in that driven including first voltage transmission circuit and clock
It is dynamic, in which:
The input terminal of first voltage transmission circuit is electrically connected with 0 current potential, the output voltage after output end output buck, and described first
Voltage transmission circuit includes several grades of decompression sub-circuits and the first output sub-circuit, is connected between every level-one decompression sub-circuit, the
The input terminal of level-one decompression sub-circuit is electrically connected with 0 current potential, and afterbody is depressured the output end and the first output son electricity of sub-circuit
The input terminal on road is electrically connected, and the output voltage after the output end output buck of the first output sub-circuit, every level-one is depressured sub-circuit
In include the NMOS transistor as auxiliary transistor and the PMOS transistor as transmission transistor；
Clock driving includes several clock signals with out of phase, respectively with the drops at different levels of first voltage transmission circuit
Sub-circuit and output sub-circuit electrical connection are pressed, for the clock signal state of conversion circuit, changes simultaneously circuit voltage.
2. negative pressure charge pump circuit according to claim 1, which is characterized in that further include second voltage transmission circuit, institute
It is in parallel with first voltage transmission circuit to state second voltage transmission circuit, the second voltage transmission circuit includes several grades of decompression
Circuit and the second output sub-circuit, every level-one are depressured between sub-circuit and connect, and the first order is depressured the input terminal and 0 current potential of sub-circuit
Electrical connection, the output end of afterbody decompression sub-circuit are electrically connected with the input terminal of the second output sub-circuit, the second output son electricity
Output voltage after the output end output buck on road, be depressured sub-circuit in include as auxiliary transistor NMOS transistor and
As the PMOS transistor of transmission transistor, the clock driving is also electric with the decompressions at different levels of second voltage transmission circuit respectively
Road and the second output sub-circuit electrical connection.
3. negative pressure charge pump circuit according to claim 2, which is characterized in that first voltage transmission circuit includes level Four drop
Sub-circuit is pressed, second voltage transmission circuit includes level Four decompression sub-circuit, and the clock driving includes four with out of phase
A clock signal clkA, clkB, clkC and clkD.
4. negative pressure charge pump circuit according to claim 3, which is characterized in that the first voltage transmission circuit includes making
For the first NMOS transistor of auxiliary transistor, the second NMOS transistor, third NMOS transistor and the 4th NMOS transistor, make
For the first PMOS transistor of transmission transistor, the second PMOS transistor, third PMOS transistor and the 4th PMOS transistor, make
For the 5th PMOS transistor of output stage, the 5th NMOS transistor, first capacitor, the second capacitor, third as auxiliary capacitor
Capacitor, the 4th capacitor, the 5th capacitor, as pumping capacitor the 6th capacitor, the 7th capacitor, the 8th capacitor, the 9th capacitor,
In:
The drain electrode of first PMOS transistor and the source electrode of the first NMOS transistor are electrically connected with 0 current potential；Second PMOS transistor
Drain electrode, the source electrode of the second NMOS transistor, the grid of the first NMOS transistor, the source electrode of the first PMOS transistor and the 6th capacitor
One end interconnects and forms node N1 in junction；The drain electrode of third PMOS transistor, the source electrode of third NMOS transistor,
The grid of bi-NMOS transistor and the source electrode of the second PMOS transistor are electrically connected with one end of the 7th capacitor and are formed in junction
Node N2；The drain electrode of 4th PMOS transistor, the source electrode of the 4th NMOS transistor, third NMOS transistor grid and third
The source electrode of PMOS transistor is electrically connected with one end of the 8th capacitor and forms node N3 in junction；The leakage of 5th PMOS transistor
Pole, the 5th NMOS transistor the 4th NMOS transistor of source electrode grid and the 4th PMOS transistor source electrode and the 9th capacitor one
End electrical connection simultaneously forms node N4 in junction；The source electrode of 5th PMOS transistor is electrically connected with circuit output end；
The drain electrode of first NMOS transistor and the grid of the first PMOS transistor and one end of first capacitor are electrically connected and are connecting
Place forms node N5；The drain electrode of second NMOS transistor and the grid of the second PMOS transistor are electrically connected with one end of the second capacitor
And node N6 is formed in junction；The drain electrode of third NMOS transistor and the grid and the one of third capacitor of third PMOS transistor
End electrical connection simultaneously forms node N7 in junction；The drain electrode of 4th NMOS transistor and the grid and the 4th of the 4th PMOS transistor
One end of capacitor is electrically connected and forms node N8 in junction；The drain electrode of 5th NMOS transistor and the grid of the 5th PMOS transistor
Pole is electrically connected with one end of the 5th capacitor and forms node N9 in junction；
First PMOS transistor, the first NMOS transistor, first capacitor, the 6th capacitor form the first of first voltage transmission circuit
Grade decompression sub-circuit, the second PMOS transistor, the second NMOS transistor, the second capacitor, the composition first voltage transmission of the 7th capacitor
The second level of circuit is depressured sub-circuit, third PMOS transistor, third NMOS transistor, third capacitor, the 8th capacitor composition the
The third level of one voltage transmission circuit is depressured sub-circuit, the 4th PMOS transistor, the 4th NMOS transistor, the 4th capacitor, the 9th
The fourth stage that capacitor forms first voltage transmission circuit is depressured sub-circuit, the 5th PMOS transistor, the 5th NMOS transistor, the 5th
Capacitor forms the first output sub-circuit of first voltage transmission circuit.
5. negative pressure charge pump circuit according to claim 4, which is characterized in that the second voltage transmission circuit includes making
For the 6th NMOS transistor, the 7th NMOS transistor, the 8th NMOS transistor and the 9th NMOS transistor of auxiliary transistor, make
For the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor and the 9th PMOS transistor of transmission transistor, make
For the tenth PMOS transistor of output stage and the tenth NMOS transistor, as the 11st capacitor of auxiliary capacitor, the 12nd capacitor,
13rd capacitor, the 14th capacitor and the 15th capacitor, the 16th capacitor, the 17th capacitor, the 18th as pumping capacitor
Capacitor and the 19th capacitor, in which:
The drain electrode of 6th PMOS transistor, the source electrode of the 6th NMOS transistor are connected with 0 current potential of input terminal；7th NMOS crystal
The source electrode of pipe, the drain electrode of the 7th PMOS transistor, the grid of the 6th NMOS transistor and the 6th PMOS transistor source electrode and
One end of 16 capacitors is electrically connected and forms node M 1 in junction；The source electrode of 8th NMOS transistor, the 8th PMOS transistor
Drain electrode, the grid of the 7th NMOS transistor and the source electrode of the 7th PMOS transistor be electrically connected with one end of the 17th capacitor and
Junction forms node M 2；The source electrode of 9th NMOS transistor, the drain electrode of the 9th PMOS transistor, the 8th NMOS transistor grid
The source electrode of pole and the 8th PMOS transistor is electrically connected with one end of the 18th capacitor and forms node M 3 in junction；Tenth NMOS
The source electrode of transistor, the drain electrode of the tenth PMOS transistor, the grid of the 9th NMOS transistor, the source electrode of the 9th PMOS transistor and
The grid of 5th NMOS transistor is electrically connected with one end of the 19th capacitor and forms node M 4 in junction；
The drain electrode of 6th NMOS transistor and the grid of the 6th PMOS transistor are electrically connected and even with one end of the 11st capacitor
The place of connecing forms node M 5；One end electricity of the drain electrode of 7th NMOS transistor and the grid of the 7th PMOS transistor and the 12nd capacitor
It connects and forms node M 6 in junction；The drain electrode of 8th NMOS transistor and the grid of the 8th PMOS transistor and the 13rd electricity
One end of appearance is electrically connected and forms node M 7 in junction；The drain electrode of 9th NMOS transistor and the grid of the 9th PMOS transistor
It is electrically connected with one end of the 14th capacitor and forms node M 8 in junction；The drain electrode of tenth NMOS transistor and the tenth PMOS are brilliant
The grid of body pipe is electrically connected with one end of the 15th capacitor and forms node M 9 in junction；
6th PMOS transistor, the 6th NMOS transistor, the 11st capacitor, the 16th capacitor form second voltage transmission circuit
The first order is depressured sub-circuit, the 7th PMOS transistor, the 7th NMOS transistor, the 12nd capacitor, the 17th capacitor composition second
The second level of voltage transmission circuit is depressured sub-circuit, the 8th PMOS transistor, the 8th NMOS transistor, the 13rd capacitor, the tenth
The third level that eight capacitors form second voltage transmission circuit is depressured sub-circuit, the 9th PMOS transistor, the 9th NMOS transistor, the
The fourth stage decompression sub-circuit of 14 capacitors, the 19th capacitor composition second voltage transmission circuit, the tenth PMOS transistor, the tenth
Second output sub-circuit of NMOS transistor, the 15th capacitor composition second voltage transmission circuit.
6. negative pressure charge pump circuit according to claim 5, which is characterized in that the clock signal clkA is respectively with second
The other end of capacitor, the other end of the 4th capacitor, the other end of the 11st capacitor, the other end of the 13rd capacitor and the 15th electricity
The other end of appearance is electrically connected；Clock signal clkB respectively with the other end of the 7th capacitor, the other end of the 9th capacitor, the 16th electricity
The electrical connection of the other end of the other end of appearance and the 18th capacitor；Clock signal clkC respectively with the other end of first capacitor, third
The other end electrical connection of the other end of capacitor, the other end of the 5th capacitor, the other end of the 12nd capacitor and the 14th capacitor；When
Clock signal clkD respectively with the other end of the 6th capacitor, the other end of the 8th capacitor, the 17th capacitor the other end and the 19th
The other end of capacitor is connected.
7. according to the described in any item negative pressure charge pump circuits of claim 3 to 6, which is characterized in that four clock signals
The voltage magnitude of clkA, clkB, clkC and clkD are equal to memory power voltage, have different time delays.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910486642.XA CN110061620A (en) | 2019-06-05 | 2019-06-05 | A kind of negative pressure charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910486642.XA CN110061620A (en) | 2019-06-05 | 2019-06-05 | A kind of negative pressure charge pump circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110061620A true CN110061620A (en) | 2019-07-26 |
Family
ID=67325684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910486642.XA Pending CN110061620A (en) | 2019-06-05 | 2019-06-05 | A kind of negative pressure charge pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110061620A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773822A (en) * | 2005-09-22 | 2006-05-17 | 复旦大学 | Efficient Low-power dissipation whole PMOS charge pump circuit adapted to low-source voltage |
| CN104300781A (en) * | 2013-07-18 | 2015-01-21 | 力旺电子股份有限公司 | Charge pump system |
| CN108282083A (en) * | 2017-12-15 | 2018-07-13 | 普冉半导体（上海）有限公司 | A kind of mixing structure charge pump circuit |
| CN109286314A (en) * | 2018-10-24 | 2019-01-29 | 华南理工大学 | A kind of four phase clock charge pump of full N-type |
-
2019
- 2019-06-05 CN CN201910486642.XA patent/CN110061620A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1773822A (en) * | 2005-09-22 | 2006-05-17 | 复旦大学 | Efficient Low-power dissipation whole PMOS charge pump circuit adapted to low-source voltage |
| CN104300781A (en) * | 2013-07-18 | 2015-01-21 | 力旺电子股份有限公司 | Charge pump system |
| CN108282083A (en) * | 2017-12-15 | 2018-07-13 | 普冉半导体（上海）有限公司 | A kind of mixing structure charge pump circuit |
| CN109286314A (en) * | 2018-10-24 | 2019-01-29 | 华南理工大学 | A kind of four phase clock charge pump of full N-type |
Non-Patent Citations (1)
| Title |
|---|
| 姜凯: ""PFM调制开关电容稳压电荷泵电路设计", 《中国优秀硕士学位论文数据库 工程科技Ⅱ辑》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104796171B (en) | A kind of control circuit applied to SOI CMOS RF switches | |
| CN102208909B (en) | Level shifting circuit | |
| CN103091526B (en) | Voltage detection circuit | |
| CN109039059A (en) | A kind of efficient multi-mode charge pump | |
| CN101304251B (en) | Difference interface circuit for on-chip long lines interlinkage | |
| CN100574068C (en) | Charge pump | |
| CN105099173A (en) | Charge pump | |
| CN1477773B (en) | Electric charge pump circuit based on coupling capacitance share | |
| CN103248218B (en) | Charge pump single-stage circuit and charge pump circuit | |
| CN103117740B (en) | Low-power-consumptiolevel level shift circuit | |
| CN102446480A (en) | Voltage conversion circuit | |
| CN110061620A (en) | A kind of negative pressure charge pump circuit | |
| CN208623548U (en) | A kind of charge pump circuit | |
| CN202513820U (en) | Charge pump single-stage circuit and charge pump circuit | |
| CN102280127B (en) | Clock generation circuit and charge pump system | |
| CN103208988A (en) | Level shifting circuit and method for conducting positive voltage level shifting and negative voltage level shifting | |
| CN207200573U (en) | A kind of charge pump circuit | |
| CN105656294A (en) | Step-down circuit in medium voltage and high voltage integrated circuit | |
| CN106602866B (en) | Charge pump | |
| CN102437841A (en) | Analog switch circuit | |
| CN110112910A (en) | A kind of positive pressure charge pump circuit | |
| CN206878701U (en) | Differential charge pump circuit | |
| CN103684380B (en) | Switched capacitor circuit | |
| CN207706052U (en) | Booster circuit | |
| CN206878700U (en) | Differential charge pump element circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190726 |
|
| RJ01 | Rejection of invention patent application after publication |