CN110061107B - Micron-sized light emitting diode chip and preparation method thereof - Google Patents
Micron-sized light emitting diode chip and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title description 10
- 238000004891 communication Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 21
- 229910052594 sapphire Inorganic materials 0.000 claims description 12
- 239000010980 sapphire Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000003892 spreading Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 5
- 239000007789 gas Substances 0.000 claims 3
- 238000002156 mixing Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000005286 illumination Methods 0.000 abstract description 9
- 238000001514 detection method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 238000000605 extraction Methods 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 abstract 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 13
- 238000009616 inductively coupled plasma Methods 0.000 description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000004020 luminiscence type Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 229910015844 BCl3 Inorganic materials 0.000 description 4
- 238000000344 low-energy electron-beam lithography Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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Abstract
The invention provides a micron-sized diode chip, comprising: the LED structure comprises a first table top, a second table top, a gallium nitride layer, an n-GaN layer, a stress release layer, a multi-quantum well light emitting layer, a p-GaN layer, a first electrode, a second electrode and an insulating layer, wherein the sizes of the first table top and the second table top are different. The invention avoids the technical problems of small output light power of the original LED and large mismatch between the thermal expansion rate and the lattice constant and the GaN, realizes the technical effect of high light extraction efficiency while integrating various functions of communication, illumination, detection and the like on the same chip.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a multifunctional chip and a preparation method thereof.
Background
The modern lighting field is changed for four generations, and the LED gradually gets on the stage. Since the LED has been invented, the LED has been used in many fields such as illumination, display, optical communication, etc. because of its advantages of energy saving, long life, environmental protection, strong robustness, controllability and durability. Among them, the application to the field of illumination requires the characteristic of high power of the device, and a large-area LED is often used; the GaN-based LED can emit blue light and green light by changing the components of the quantum well, the GaAs-based LED can emit red light, full-color display can be realized by integrating three-color LEDs, and red, green and blue light can be mixed by covering light conversion materials such as fluorescent powder or quantum dots on the LED surface; in the field of visible light communication, micro-LEDs are gaining attention due to their excellent bandwidth performance. The invention provides a design method, which can improve the functionality of an LED on the same LED device, so that the LED device has multiple functions of illumination, display, visible light communication and the like.
One prior art is chinese patent application with patent publication No. 107482031a, and its technical solution is shown in fig. 1. The utility model discloses a preparation method of GaN-based micron-scale LED array. The large-area evaporation metal electrode can inhibit light from emitting from the front side, the mutually independent array units can be used as a transmitting and receiving end, and the external circuit design is matched to collect external vibration and energy of a light source, so that back light of the device is realized respectively, and the ultrahigh-speed MIMO system and the energy acquisition function are realized. The first prior art has the disadvantages that the band gap of Si is small, the quantum well luminescence is easily absorbed, the light extraction efficiency is reduced, and in addition, the response current and the detection sensitivity are low.
The second prior art is a chinese patent application with patent publication No. 105897337a, and a technical scheme thereof is shown in fig. 2, which discloses a visible light communication system based on a micron LED array and an establishment method thereof. By combining LED preparation and a visible light communication system, the prepared micron LED array has high photoelectric modulation bandwidth, can realize parallel communication, has high communication speed and simultaneously has the functions of micro-display and illumination. The second prior art has the defects that the output light power of the micron LED is relatively small, so that the communication distance and the practicability of the micron LED are limited; the epitaxial wafer is etched from the p-type layer to the n-type layer through dry etching, the area of a side wall is increased due to the etching, the defects of the side wall are increased, and the defects capture carriers in transportation, so that the internal quantum efficiency of the device is reduced.
Disclosure of Invention
In order to overcome the defects of the prior art and avoid the technical problems of lower response current and detection sensitivity and closer communication distance of the original LED, the multifunctional microchip with large response current and high detection sensitivity is provided.
A micron-scale light emitting diode chip comprising:
the system comprises a first table top, a second table top and a communication system receiving end;
the first table top is a lighting source, the second table top is a communication system transmitting end, and the back of the micron-sized light emitting diode chip is the communication system receiving end;
the first table top comprises a first stress release layer, a first multi-quantum well light-emitting layer, a first p-GaN layer and a first current expansion layer ITO which are arranged from bottom to top; the second table top comprises a second stress release layer, a second multi-quantum well light-emitting layer, a second p-GaN layer and a second current expansion layer ITO which are arranged from bottom to top;
the first insulating layer coats the first table top, and the second insulating layer coats the second table top; an unintentional gallium nitride-doped layer and an n-GaN layer are arranged below the first table top and the second table top from bottom to top;
in the first mesa and the second mesa, the first mesa is larger in size, and the mesa size of the first mesa is 100 micrometers by 100 micrometers to 1 millimeter by 1 millimeter; the second mesa is smaller in size, the second mesa being 3 microns by 3 microns to 250 microns by 250 microns.
Preferably, the second table-board is prepared by a method of limiting the light-emitting area of the micron-sized light-emitting diode chip by depositing a micron-sized current expansion layer ITO.
A preparation method of a micron-sized light emitting diode chip comprises the following steps: step 1: obtaining a mesa area through exposure and etching, wherein the mesa area comprises a first mesa; step 2: a second table top is obtained in the table top area by adopting a method of depositing a micron-sized current expansion layer ITO to limit the light emitting area of the light emitting diode; and step 3: the exposure defines the isolation region and the electrode region.
Preferably, the step 1 comprises: uniformly and rotationally coating photoresist on the sapphire substrate GaN-based epitaxial wafer, defining a mesa region through exposure and etching, and grinding and polishing the sapphire substrate.
Preferably, the step 1 comprises: step 1.1: exposing a region to be etched; step 1.2: corroding the current expansion layer ITO in the photoresist-free area to the surface of the p-GaN by adopting a wet corrosion method; step 1.3: dry etching and removing the photoresist to obtain the mesa region, wherein the mesa region comprises a first mesa; step 1.4: and grinding and polishing the sapphire substrate.
Preferably, the step 3 comprises: step 3.1: growing a SiO2 insulating layer by adopting a chemical vapor deposition method; step 3.2, exposing and defining the corrosion area of the insulating layer; step 3.3: etching the isolated area in the etching area by adopting dry etching or wet etching; step 3.4: removing the residual photoresist, uniformly spin-coating the photoresist again, and exposing to define an electrode area; step 3.5: and evaporating a Ni/Au metal layer to remove the residual photoresist.
Preferably, the dry etching uses a mixed gas of BCl3 and Ar.
Preferably, the chemical vapor deposition adopts mixed gas of N2O, N2 and SiH 4.
Preferably, the dry etching uses CHF3 gas, and the wet etching uses a BOE solution.
When a small-size table surface is defined, the method for preparing the Micro-LED is characterized in that the micron-level LED table surface is not required to be etched, the luminous area of the LED is limited by limiting the size of the ITO of the current expansion layer to be the micron level, the area of the ITO of the current expansion layer is reduced, and the effect of limiting a carrier transport path is achieved, so that the Micro-LED is used as an emitting end of a communication system, and meanwhile, the receiving area of a receiving end is not influenced. The chip is used as a receiving end in a visible light communication system. By selective CHF at p-GaN surface3Plasma treatment can achieve the effect of limiting carrier transport. The invention realizes higher output light power through the LED with higher power and is used for illumination; micro-LED luminescence of a local area is realized by limiting the current expansion layer area, and the micro-LED luminous device is used for micro-LED display and high-speed visible light communication; meanwhile, the current spreading layer ITO only covers part of p-GaN, and the quantum well region of the mesa part which is not covered with the current spreading layer ITO can also detect external luminescence, so that the current spreading layer ITO has high response current and detection sensitivity.
Drawings
FIG. 1 is a flow chart of a first prior art solution;
FIG. 2 is a flow chart of a second prior art solution;
FIG. 3 is a flow chart of an embodiment of the present invention;
FIG. 4 is a schematic view of a GaN-based epitaxial wafer structure;
fig. 5 is a schematic cross-sectional view of a GaN-based multifunctional chip unit array.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, the following examples of which are intended to be illustrative only and are not to be construed as limiting the scope of the invention.
Example one
The embodiment provides a multifunctional micro-LED chip with a carrier transport region limited by a small-sized current spreading layer ITO and a preparation method thereof, as shown in FIGS. 3 to 5.
Taking a green light epitaxial wafer as an example, the method specifically comprises the following steps:
step 1: the sapphire substrate comprises an unintentional doped GaN layer of 3 micrometers, an n-GaN layer of 2 micrometers, a stress release layer of 0.3 micrometer, a multiple quantum well light-emitting layer of 0.17 micrometer, a p-GaN layer of 0.5 micrometer and a current expansion layer ITO from bottom to top; 4000 rev/min of resist using S1818, 1.8 to 2.2 microns thick, exposure for 10 seconds using uv photo-lithography machine (MA6), development for 50 seconds using 0.5% NaOH solution;
step 2: etching with a mixed solution of concentrated hydrochloric acid/concentrated nitric acid (4: 1) for 1 minute and 30 seconds;
and step 3: using an inductively coupled plasma etcher (Oxford), BCl330sccm, 15sccm of Ar, 150W of radio frequency power, 1000W of ICP power, 10 mTorr of gas pressure, 20 ℃ of temperature and 6 minutes and 43 seconds of etching time;
and 4, step 4: removing the residual photoresist by using an acetone solution;
and 5: photoetching and defining a small mesa area, and corroding for 1 minute and 30 seconds by using a concentrated hydrochloric acid/concentrated nitric acid (4: 1) mixed solution;
step 6: the thermal annealing conditions were 0.6 liter/min N using a rapid thermal annealer (RTP-300)2At the temperature of 300 ℃ for 10 seconds and at the temperature of 550 ℃ for 15 minutes under the atmosphere;
and 7: using plasma enhanced chemical vapor deposition (Oxford), N2O 710sccm，N2161.5sccm，SiH48.5sccm, a gas pressure of 1000 mTorr, a temperature of 300 ℃, an inclination angle of 20.9 ℃, and a deposition time of 244 seconds;
and 8: uniformly spin-coating photoresist, and defining an insulating layer etching area through exposure;
and step 9: using an inductively coupled plasma etcher (Oxford), CHF35sccm, 30W of RF power, 600W of ICP power, 10.2 mTorr of gas pressure,the temperature is 20 ℃, and the etching time is 164 seconds; carrying out wet etching by using a BOE solution for 20 seconds;
step 10: removing the residual photoresist, uniformly spin-coating the photoresist again, and exposing to define an electrode area;
step 11: magnetron sputtering is used, under Ar atmosphere, the direct current power is 100 watts, the air pressure is 2 mTorr, and Ni is sputtered for 200 seconds; the DC power is 135W, and the gas pressure is 2 mTorr to sputter Au for 200 seconds.
The present embodiment also provides a method of passing CHF3A multifunctional micro-LED chip for limiting a carrier transport region through plasma treatment and a preparation method thereof take a green light epitaxial wafer as an example and specifically comprise the following steps:
step 1: the sapphire substrate comprises an unintentional doped GaN layer of 3 micrometers, an n-GaN layer of 2 micrometers, a stress release layer of 0.3 micrometer, a multiple quantum well light-emitting layer of 0.17 micrometer, a p-GaN layer of 0.5 micrometer and a current expansion layer ITO from bottom to top; 4000 rev/min of resist using S1818, 1.8 to 2.2 microns thick, exposure for 10 seconds using uv photo-lithography machine (MA6), development for 50 seconds using 0.5% NaOH solution;
step 2: etching with a mixed solution of concentrated hydrochloric acid/concentrated nitric acid (4: 1) for 1 minute and 30 seconds;
and step 3: using an inductively coupled plasma etcher (Oxford), BCl330sccm, 15sccm of Ar, 150W of radio frequency power, 1000W of ICP power, 10 mTorr of gas pressure, 20 ℃ of temperature and 6 minutes and 43 seconds of etching time;
and 4, step 4: removing residual photoresist by using an acetone solution, and defining and corroding the small-size current expansion layer ITO by photoetching;
and 5: lithographically defining RIE region and using CHF3The plasma passivates the surface of the p-GaN to achieve the purpose of limiting a carrier transport region;
step 6: the thermal annealing conditions were 0.6 liter/min N using a rapid thermal annealer (RTP-300)2At the temperature of 300 ℃ for 10 seconds and at the temperature of 550 ℃ for 15 minutes under the atmosphere;
and 7: using plasma enhanced chemical vapor deposition (Oxford), N2O 710sccm，N2161.5sccm，SiH48.5sccm, a gas pressure of 1000 mTorr,the temperature is 300 ℃, the inclination angle is 20.9 ℃, and the deposition time is 244 seconds;
and 8: uniformly spin-coating photoresist, and defining an insulating layer etching area through exposure;
and step 9: using a reactive coupled plasma etcher (Oxford), CHF35sccm, 30W of radio frequency power, 600W of ICP power, 10.2 mTorr of air pressure, 20 ℃ of temperature and 164 seconds of etching time; carrying out wet etching by using a BOE solution for 20 seconds;
step 10: removing the residual photoresist, uniformly spin-coating the photoresist again, and exposing to define an electrode area;
step 11: magnetron sputtering is used, under Ar atmosphere, the direct current power is 100 watts, the air pressure is 2 mTorr, and Ni is sputtered for 200 seconds; the DC power is 135W, and the gas pressure is 2 mTorr to sputter Au for 200 seconds. The present embodiment provides a GaN epitaxial wafer, as shown in fig. 4 and 5, including a sapphire substrate 100, which is unintentionally doped with GaN 110; n-GaN 120; a stress release layer 130; a multiple quantum well light-emitting layer 140; p-GaN 150; a current spreading layer ITO 160; an n-type electrode 210; SiO22 An insulating layer 220; large-sized mesas 230; a small size mesa 240.
The large-size mesa has a size of 100 micrometers by 100 micrometers to 1 millimeter by 1 millimeter; the small-sized mesa has a size of 3 microns by 3 microns to 250 microns by 250 microns.
The method for limiting the light emitting area of the diode by depositing the micron-sized current expansion layer ITO is adopted to prepare the small-sized table top, namely the small-sized current expansion layer ITO limits the carrier transport channel, or CHF is adopted3Plasma treating the p-GaN layer.
The first table top is a lighting source, the second table top is a communication system transmitting end, and the sapphire substrate on the back of the chip is polished and then is a communication system receiving end.
The area of the second table top is determined according to the area of the micro-LED to be prepared.
In some embodiments, the preparation of the small-sized mesa limits the transport channel of the carriers by reducing the size of the current spreading layer ITO; or is CHF3Ion-passivating p-GaN so as not to be substituted by CHF3Ion modifiedCan transport carriers; or activating Mg doping of p-GaN by low-energy electron beam irradiation (LEEBI) to improve the conductivity.
Example two
The present embodiment provides a multifunctional micro-LED chip and a method for fabricating the same, which increases the carrier concentration in a confined region by activating the magnesium doping of p-GaN through LEEBI (low energy electron beam irradiation) to confine the carrier transport region, as shown in fig. 3 to 5.
Step 1: the sapphire substrate comprises an unintentional doped GaN layer of 3 micrometers, an n-GaN layer of 2 micrometers, a stress release layer of 0.3 micrometer, a multiple quantum well light-emitting layer of 0.17 micrometer and a p-GaN layer of 0.5 micrometer from bottom to top; 4000 rev/min of resist using S1818, 1.8 to 2.2 microns thick, exposure for 10 seconds using uv photo-lithography machine (MA6), development for 50 seconds using 0.5% NaOH solution;
step 2: using an inductively coupled plasma etcher (Oxford), BCl330sccm, 15sccm of Ar, 150W of radio frequency power, 1000W of ICP power, 10 mTorr of gas pressure, 20 ℃ of temperature and 6 minutes and 43 seconds of etching time;
and step 3: removing residual photoresist by using an acetone solution, and defining and corroding the small-size table top by photoetching;
and 4, step 4: treating small-sized regions with a 10keV electron beam of a Cameca SX100 electron probe microanalyzer;
and 5: defining and depositing a current expansion layer ITO as a current expansion layer by photoetching;
step 6: the thermal annealing conditions were 0.6 liter/min N using a rapid thermal annealer (RTP-300)2At the temperature of 300 ℃ for 10 seconds and at the temperature of 550 ℃ for 15 minutes under the atmosphere;
and 7: using plasma enhanced chemical vapor deposition (Oxford), N2O 710sccm，N2161.5sccm，SiH48.5sccm, a gas pressure of 1000 mTorr, a temperature of 300 ℃, an inclination angle of 20.9 ℃, and a deposition time of 244 seconds;
and 8: uniformly spin-coating photoresist, and defining an insulating layer etching area through exposure;
and step 9: using a reactive coupled plasma etcher (Oxford), CHF35sccm, a radio frequency power of 30 watts,ICP power is 600W, air pressure is 10.2 mTorr, temperature is 20 ℃, and etching time is 164 seconds; carrying out wet etching by using a BOE solution for 20 seconds;
step 10: removing the residual photoresist, uniformly spin-coating the photoresist again, and exposing to define an electrode area;
step 11: magnetron sputtering is used, under Ar atmosphere, the direct current power is 100 watts, the air pressure is 2 mTorr, and Ni is sputtered for 200 seconds; the DC power is 135W, and the gas pressure is 2 mTorr to sputter Au for 200 seconds.
The design of the invention defines a large square table and a small square table on the same array of the chip, wherein the large size is 100 micrometers by 100 micrometers to 1 millimeter by 1 millimeter, and the small size is 3 micrometers by 3 micrometers to 250 micrometers by 250 micrometers. The large size has higher optical power and thus can be used as an illumination source; the small size has fast response time and high response frequency, and can be used as a light emitting end in a visible light communication system; meanwhile, the back sapphire substrate is ground and polished, and when light with signals is incident from the back of the chip, photogenerated carriers are generated due to the photoelectric effect of the GaN semiconductor chip, so that the chip can also be used as a receiving end in a visible light communication system. The invention realizes higher output light power through the LED with higher power and is used for illumination; micro-LED luminescence of a local area is realized by limiting the current expansion layer area, and the micro-LED luminous device is used for micro-LED display and high-speed visible light communication; meanwhile, although the current expansion layer ITO only covers part of p-GaN and limits a light emitting region, the quantum well region of the mesa part which is not covered with the current expansion layer ITO can also detect external light emission, and has high response current and detection sensitivity.
Particularly, compared with the preparation method for realizing the small-size table structure by etching disclosed by the second prior art, the invention has the advantages that the defects of the side wall are increased, the current carriers in the transportation are captured, and the internal quantum efficiency of the device is reducedMeanwhile, the receiving area of the receiving end is not influenced, and the ratio of the side wall area to the pixel area is reduced, so that the defects are reduced, and the efficiency of the device is improved. By selective CHF at p-GaN surface3Plasma treatment can also achieve the effect of limiting carrier transport.
The invention realizes higher output light power through the LED with higher power and is used for illumination; the micro-LED luminescence of the local area is realized by limiting the current expansion layer area, and the micro-LED luminous display device is used for micro-LED display and high-speed visible light communication. Meanwhile, the current spreading layer ITO only covers part of p-GaN, and the quantum well region of the mesa part which is not covered with the current spreading layer ITO can also detect external luminescence, so that the current spreading layer ITO has high response current and detection sensitivity.
The foregoing is merely a description of embodiments of the present invention, and specific embodiments of the present invention are not limited in this respect. All simple substitutions made by the conception of the present invention including direct or indirect use of the related art shall fall within the protection scope of the present invention.
Claims (9)
1. A micron-sized light emitting diode chip, comprising:
the system comprises a first table top, a second table top and a communication system receiving end;
the first table top is a lighting source, the second table top is a communication system transmitting end, and the back of the micron-sized light emitting diode chip is the communication system receiving end;
the first table top comprises a first stress release layer, a first multi-quantum well light-emitting layer, a first p-GaN layer and a first current expansion layer ITO which are arranged from bottom to top; the second table top comprises a second stress release layer, a second multi-quantum well light-emitting layer, a second p-GaN layer and a second current expansion layer ITO which are arranged from bottom to top;
the first insulating layer coats the first table top, and the second insulating layer coats the second table top; an unintentional gallium nitride-doped layer and an n-GaN layer are arranged below the first table top and the second table top from bottom to top;
in the first mesa and the second mesa, the first mesa is larger in size, and the size of the first mesa is 100 micrometers by 100 micrometers to 1 millimeter by 1 millimeter; the second mesa is smaller in size, the second mesa being 3 microns by 3 microns to 250 microns by 250 microns.
2. The micron-sized light emitting diode chip of claim 1, wherein the second mesa is fabricated by depositing a micron-sized current spreading layer of ITO to limit the light emitting area of the micron-sized light emitting diode chip.
3. A method for manufacturing a micron-sized light emitting diode chip as claimed in any one of claims 1 to 2, comprising: step 1: obtaining a mesa area through exposure and etching, wherein the mesa area comprises a first mesa; step 2: a second table top is obtained in the table top area by adopting a method of depositing a micron-sized current expansion layer ITO to limit the light emitting area of the light emitting diode; and step 3: the exposure defines the isolation region and the electrode region.
4. A method for preparing micron-sized light emitting diode chip as claimed in claim 3, wherein the step 1 comprises: uniformly and rotationally coating photoresist on the sapphire substrate GaN-based epitaxial wafer, defining a mesa region through exposure and etching, and grinding and polishing the sapphire substrate.
5. A method for preparing micron-sized light emitting diode chip as claimed in claim 3, wherein the step 1 comprises: step 1.1: exposing a region to be etched; step 1.2: corroding the current expansion layer ITO in the photoresist-free area to the surface of the p-GaN by adopting a wet corrosion method; step 1.3: dry etching and removing the photoresist to obtain the mesa region, wherein the mesa region comprises a first mesa; step 1.4: and grinding and polishing the sapphire substrate.
6. A method for manufacturing a micron-sized light emitting diode chip as claimed in claim 3, wherein the step 3 comprises: step 3.1: method for chemical vapor depositionGrowing SiO2An insulating layer; step 3.2, exposing and defining the corrosion area of the insulating layer; step 3.3: etching the isolated area in the etching area by adopting dry etching or wet etching; step 3.4: removing the residual photoresist, uniformly spin-coating the photoresist again, and exposing to define an electrode area; step 3.5: and evaporating a Ni/Au metal layer to remove the residual photoresist.
7. The method for manufacturing micron-sized light emitting diode chip as claimed in claim 5, wherein BCl is adopted for dry etching3Mixed with Ar gas.
8. The method for manufacturing a micro-scale light emitting diode chip as claimed in claim 6, wherein the chemical vapor deposition employs N2O，N2，SiH4And (4) mixing the gases.
9. The method for manufacturing a micron-sized light emitting diode chip as claimed in claim 6, wherein the dry etching employs CHF3And gas, wherein the wet etching adopts BOE solution.
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