CN110058974A - A kind of USB PD fast charge protocol chip checking method based on RISC_V processor - Google Patents
A kind of USB PD fast charge protocol chip checking method based on RISC_V processor Download PDFInfo
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- CN110058974A CN110058974A CN201910223768.8A CN201910223768A CN110058974A CN 110058974 A CN110058974 A CN 110058974A CN 201910223768 A CN201910223768 A CN 201910223768A CN 110058974 A CN110058974 A CN 110058974A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses cpu instructions to read technology, more particularly, to a kind of USB PD fast charge protocol chip checking method based on RISC_V processor.A kind of USB PD fast charge protocol chip checking method based on RISC_V processor, language is verified using UVM verification methodology and systemverilog, verification platform is constructed using expansible chip interface behavior model driver, moniter, functional verification is implemented to USB_PD chip.The beneficial effect is that: provide a kind of verification platform of USBPD protocol chip based on RISV_V, the verification platform can be with lower time and human cost, the work problem of higher verification efficiency processing chip checking, the characteristic and performance of reliable verifying USBPD protocol chip comprehensively, reduce enterprise's production and operation cost, the economic loss for reducing enterprise brings great convenience to enterprise's normal operation.
Description
Technical field
The invention discloses a kind of verification methods of processor, more particularly, to a kind of USB based on RISC_V processor
PD fast charge protocol chip checking method.
Background technique
In the prior art, since fast charge chip belongs to consumer electronics product, the market demand is changed quickly, so right
There is higher requirement in the development cycle of USBPD protocol chip.The workload of chip checking is occupied in a chip design more than 50%
Time and efforts higher want is proposed to the efficiency of chip checking work with the continuous growth of chip design complexity
It asks.Improving chip checking efficiency can be completed by following three kinds of methods:
1. improving the reusability (reuse between disparity items and reuse between same project disparate modules) of verification environment；
2. improving the scalability of verification environment (verification environment can be relatively easy to modification when design specification is modified)；
3. providing the convenience and flexibility of verification environment building test case；
4. automatic comparison simulation result and collection coverage rate (including code coverage and function coverage)；
Above four kinds of method validation efficiency is more low, greatly wastes the production cost of chip production enterprise, consumes big
The manpower of amount and time cause huge economic loss to enterprise.
Summary of the invention
The purpose of the present invention is to provide a kind of USB PD fast charge protocol chip checking based on RISC_V processor
Method, the technical solution adopted by the present invention is that: language is verified using UVM verification methodology and systemverilog, utilization is expansible
Chip interface behavior model driver, moniter constructs verification platform, implements functional verification to USB_PD chip.
Further, verification platform is by following module composition:
The top layer TOP_env of the entire verification environment of module 1--；
Module 2-- design USB_PD_DUT to be measured；
The various verification environment interface interface for needing to be connected with DUT of module 3--；
Register model REG_MOD of the module 4-- based on UVM_REG；
Module 5--REG2AHB_Adapter, the translation type for being responsible for register model REG_MOD and AHB_ENV turn
Change function；
Module 6--AHB bus access verification environment AHB_ENV；
The sequencer of sequence is received in module 7--AHB_ENV；
The excitation sending module driver of module 8--AHB bus；
Module 9--CPU_ENV allows DUT to send USB_PD protocol package by configuration register and DMEM, and processing is interrupted, and core is handled
The USB_PD protocol package that piece receives；
The transmission agent of module 10--CPU_ENV is responsible for allowing DUT to send USB_PD protocol package by configuration register and DMEM；
Module 11--CPU_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected CPU_driver；
Module 12--CPU_ENV sends the driver of agent, is responsible for sending the excitation of read-write register and DMEM；
The reception agent of module 13--CPU_ENV is responsible for processing interrupt signal and handles the USB_PD protocol package that chip receives；
The monitoring module MONITOR of the reception agent of module 14--CPU_ENV, is responsible for monitoring interrupt signal and executes phase
Answer interrupt processing；
The reference model RM of module 15--CPU_ENV, it is responsible according to the desired protocol package of USB_PD protocol requirement generation and corresponding
Behavior (such as packet loss, time-out)；
The scoreboard SCOREBOARD of module 16--CPU_ENV, to the data received from DUT, and the data received from RM carry out
It compares；
Module 17--PD_ENV sends USB_PD protocol package to chip by CC interface, is connect by CC interface
Receive the USB_PD protocol package that chip is sent；
The transmission agent of module 18--PD_ENV is responsible for sending USB_PD protocol package to chip by CC interface；
Module 19--PD_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected PD_driver；
Module 20--PD_ENV sends the driver of agent, responsible to generate the excitation for meeting USB_PD phy layer protocol data
It is sent to the CC pin of DUT；
The reception agent of module 21--PD_ENV is responsible for receiving the USB_PD protocol package that chip is sent by CC interface；
The monitoring module MONITOR of the reception agent of module 22--PD_ENV, is responsible for monitoring CC signal and is properly received correctly
PD protocol package, and identify wrong data packet；
The reference model RM of module 23--PD_ENV.It is responsible for generating corresponding expecting contract packet and behavior according to USB_PD protocol requirement
(such as packet loss, time-out retransmit, counter)；
The scoreboard SCOREBOARD of module 24--PD_ENV.To the data received from DUT, and the data received from RM are compared
It is right；
The library module 25--Sequence, for generating the testcase of various complexity；
Module 26--Virtual_sequencer, virtual sequencer are used to the various sequence of complicated testcase to distribute
To corresponding sequencer；
Module 27--config configuration file configures DUT and verification environment according to different testcase demands；
Module 28--Functional Coverage module. function coverage module.For the complete of statistical testing of business cycles work
Property；
29-Test_case of module, test case layer；
Further, the functional verification energy of USB_PD chip is implemented at random using the method and the generation automated meets USB_
The data of PD agreement are simultaneously applied to chip；
Further, correct chip feedback expectation number can be automatically generated using the functional verification that the method implements USB_PD chip
According to；
Further, the various numbers issued using the acquisition chip that the functional verification that the method implements USB_PD chip can automate
According to, and correct expected data automate and that verification environment generates is compared；
Further, various abnormal surveys can be generated by unbound document using the functional verification that the method implements USB_PD chip
Examination excitation, and verification environment can excitation generates correctly expectation extremely to these；
Further, functional coverage defined in coverage rate group can be passed through using the functional verification that the method implements USB_PD chip
Point information, the functional coverage point information analysis according to acquisition obtain the function coverage of entire USB_PD chip, to guarantee
Verification quality.
The invention has the advantages that: a kind of verification platform of USBPD protocol chip based on RISV_V is provided,
The verification platform can be with lower time and human cost, the work problem of higher verification efficiency processing chip checking, comprehensively
The characteristic and performance of reliable verifying USBPD protocol chip, reduce enterprise's production and operation cost, reduce the economic damage of enterprise
It loses, brings great convenience to enterprise's normal operation.
Detailed description of the invention
Fig. 1 is USB PD verification platform schematic diagram of the invention；
In figure, 1. top layer TOP_env；2. design USB_PD_DUT to be measured；3. the various verification environments for needing to be connected with DUT
Interface interface；4. the register model REG_MOD based on UVM_REG； 5.Adapter；6. ahb bus access is tested
Demonstrate,prove environment AHB_ENV；The sequencer of sequence is received in 7.AHB_ENV；The excitation sending module of 8.AHB bus
driver； 9.CPU_ENV；The transmission agent of 10.CPU_ENV；The sequencer of 11.CPU_ENV transmission agent；
The driver of 12.CPU_ENV transmission agent；The reception agent of 13.CPU_ENV；The prison of the reception agent of 14.CPU_ENV
Control module MONITOR；The reference model RM of 15.CPU_ENV； 16. SCOREBOARD； 17. PD_ENV； 18.PD_ENV
Transmission agent；The sequencer of 19.PD_ENV transmission agent； 20. driver；The reception agent of 21.PD_ENV；
22. monitoring module MONITOR；The reference model RM of 23.PD_ENV；The scoreboard SCOREBOARD of 24.PD_ENV；
The library 25.Sequence；26.Virtual_sequencer, virtual sequencer；27.config configuration file, according to difference
Testcase demand；28.Functional Coverage module. function coverage module；29.Test_case, test
Use-case layer.Specific embodiment
Below in conjunction with drawings and examples, the present invention is further illustrated.
A kind of USB PD fast charge protocol chip checking method based on RISC_V processor of the invention, is tested using UVM
It demonstrate,proves methodology and systemverilog verifies language, utilize expansible chip interface behavior model driver, moniter structure
Verification platform is built, functional verification is implemented to USB_PD chip.
Further, verification platform is by following module composition:
The top layer TOP_env of the entire verification environment of module 1--；
Module 2-- design USB_PD_DUT to be measured；
The various verification environment interface interface for needing to be connected with DUT of module 3--；
Register model REG_MOD of the module 4-- based on UVM_REG；
Module 5--REG2AHB_Adapter, the translation type for being responsible for register model REG_MOD and AHB_ENV turn
Change function；
Module 6--AHB bus access verification environment AHB_ENV；
The sequencer of sequence is received in module 7--AHB_ENV；
The excitation sending module driver of module 8--AHB bus；
Module 9--CPU_ENV allows DUT to send USB_PD protocol package by configuration register and DMEM, and processing is interrupted, and core is handled
The USB_PD protocol package that piece receives；
The transmission agent of module 10--CPU_ENV is responsible for allowing DUT to send USB_PD protocol package by configuration register and DMEM；
Module 11--CPU_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected CPU_driver；
Module 12--CPU_ENV sends the driver of agent, is responsible for sending the excitation of read-write register and DMEM；
The reception agent of module 13--CPU_ENV is responsible for processing interrupt signal and handles the USB_PD protocol package that chip receives；
The monitoring module MONITOR of the reception agent of module 14--CPU_ENV, is responsible for monitoring interrupt signal and executes phase
Answer interrupt processing；
The reference model RM of module 15--CPU_ENV, it is responsible according to the desired protocol package of USB_PD protocol requirement generation and corresponding
Behavior (such as packet loss, time-out)；
The scoreboard SCOREBOARD of module 16--CPU_ENV, to the data received from DUT, and the data received from RM carry out
It compares；
Module 17--PD_ENV sends USB_PD protocol package to chip by CC interface, is connect by CC interface
Receive the USB_PD protocol package that chip is sent；
The transmission agent of module 18--PD_ENV is responsible for sending USB_PD protocol package to chip by CC interface；
Module 19--PD_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected PD_driver；
Module 20--PD_ENV sends the driver of agent, responsible to generate the excitation for meeting USB_PD phy layer protocol data
It is sent to the CC pin of DUT；
The reception agent of module 21--PD_ENV is responsible for receiving the USB_PD protocol package that chip is sent by CC interface；
The monitoring module MONITOR of the reception agent of module 22--PD_ENV, is responsible for monitoring CC signal and is properly received correctly
PD protocol package, and identify wrong data packet；
The reference model RM of module 23--PD_ENV.It is responsible for generating corresponding expecting contract packet and behavior according to USB_PD protocol requirement
(such as packet loss, time-out retransmit, counter)；
The scoreboard SCOREBOARD of module 24--PD_ENV.To the data received from DUT, and the data received from RM are compared
It is right；
The library module 25--Sequence, for generating the testcase of various complexity；
Module 26--Virtual_sequencer, virtual sequencer are used to the various sequence of complicated testcase to distribute
To corresponding sequencer；
Module 27--config configuration file configures DUT and verification environment according to different testcase demands；
Module 28--Functional Coverage module. function coverage module.For the complete of statistical testing of business cycles work
Property；
29-Test_case of module, test case layer；
Further, the functional verification energy of USB_PD chip is implemented at random using the method and the generation automated meets USB_
The data of PD agreement are simultaneously applied to chip；
Further, correct chip feedback expectation number can be automatically generated using the functional verification that the method implements USB_PD chip
According to；
Further, the various numbers issued using the acquisition chip that the functional verification that the method implements USB_PD chip can automate
According to, and correct expected data automate and that verification environment generates is compared；
Further, various abnormal surveys can be generated by unbound document using the functional verification that the method implements USB_PD chip
Examination excitation, and verification environment can excitation generates correctly expectation extremely to these；
Further, functional coverage defined in coverage rate group can be passed through using the functional verification that the method implements USB_PD chip
Point information, the functional coverage point information analysis according to acquisition obtain the function coverage of entire USB_PD chip, to guarantee
Verification quality.
Brief description is made to a specific embodiment of the invention with reference to the accompanying drawing.
The verifying system of the present invention provides a kind of USB_PD fast charge protocol chip based on RISC_V processor, makes
USB_PD chip can carry out efficiently comprehensive verifying using UVM verification platform.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
The framework of verification platform of the present invention is as shown in Figure 1, verification platform mainly includes module 1- top layer TOP_ENV, module
2- design DUT to be measured, module 3-DUT interface module interface, module 29- test case layer test_case, module 9-CPU
Verification environment CPU_ENV, module 17-PD verification environment PD_ENV, module 4- register model register model, module
26- dummy excitation generator virtual seqencer, module 6-AHB bus access act on behalf of AHB_ENV, and module 25- motivates library
File sequence lib, module 27- chip and verification environment configuration file config, module 28- function coverage module；
Module 1-TOP_ENV is the top of verification platform, to other checking assemblies in addition to module 25-sequence_lib into
Row example, and example is carried out to the interface module 3-interface for link block 2-DUT and testbench.
In interface comprising the DUT interface signal in need used definition, the data communication for verification platform and DUT；
29-Test_case layers of module are test case layers, each test_case different verifying ring of exampleization according to actual needs
Border env and virtual sequence, different test can be by the different parameters of modification config file configuration to DUT
And verification environment, the sequence for the suitable current use-case that different test can choose from sequence lib, group
At virtual sequence, very simple and flexible different test cases can be constructed using this verification platform；
Module 4-register model is register model, and the module 8-driver in module 6-AHB_ENV is responsible for DUT's
AHB signal interaction, module 5-REG2AHB_adapter be a conversion module, is responsible for generating register model
Transaction is converted into the transaction that AHB_driver can be identified.The other assemblies of verification platform, such as module
12-CPU_driver can be accessed directly inside DUT by the interface of module 4- register model when wanting access to register
Register, verification platform backstage can be automatically performed remaining thing, greatly facilitate the construction of test case；
Module 9-CPU_ENV includes module 10-CPU_tx_agent, module 13-CPU_rx_agent, module 15-CPU_
4 big modules of Reference_module, module 16-CPU_scoreboard etc., CPU_ENV are responsible for passing through configuration register
DUT is allowed to send USB_PD protocol package with DMEM, processing is interrupted, the USB_PD protocol package that processing chip receives.
Module 10-CPU_tx_agent includes module 11-CPU_tx_sequencer and module 12-CPU_tx_driver
Two modules, CPU_tx_agent are responsible for receiving the sequence from virtual_sequencer and then passing through configuring deposit
Device and DMEM allow DUT to send USB_PD protocol package.Module 11-CPU_tx_sequencer is responsible for receiving from virtual_
The sequence of sequencer simultaneously gives sequence connected CPU_driver.Module 12-CPU_tx_driver is responsible for
Send the excitation of read-write register and DMEM；
Module 13-CPU_rx_agent includes module 14-CPU_rx_monitor, is responsible for the interrupt signal of reception DUT sending simultaneously
It carries out corresponding interrupt processing and handles the USB_PD protocol package that chip receives, module 14-CPU_rx_monitor monitoring module,
It is responsible for the interrupt signal that monitoring DUT is issued and executes respective interrupt processing and handle the USB_PD protocol package that chip receives；
Module 15-CPU_RM verification environment reference model is responsible for generating desired protocol package and phase according to USB_PD protocol requirement
The behavior (such as packet loss, time-out) answered, module 16-CPU_SCOREBOARD, to the data received from DUT, and the number received from RM
According to being compared；
Module 17-PD_ENV includes module 18-PD_tx_agent, module 21-PD_rx_agent, module 23-PD_
4 big modules of Reference_module, module 24-PD_scoreboard etc., PD_ENV pass through CC interface to core
Piece sends USB_PD protocol package, receives the USB_PD protocol package that chip is sent by CC interface；
Module 18-CPU_tx_agent includes two moulds of module 19-PD_tx_sequencer and module 20-PD_tx_driver
Block, PD_tx_agent are responsible for receiving the sequence from virtual_sequencer and then pass through driving CC interface
USB_PD protocol package is sent to chip, module 19-PD_tx_sequencer is responsible for receiving from virtual_sequencer
Sequence and sequence is given connected PD_driver, module 20-PD_tx_driver, responsible generation meets
The excitation of USB_PD phy layer protocol sends data to the CC pin of DUT；
Module 21-PD_rx_agent includes module 22-PD_rx_monitor, is responsible for receiving by monitoring CC interface
The USB_PD protocol package that chip is sent, module 22-PD_rx_monitor monitoring module are responsible for monitoring CC signal and are properly received
Correct PD protocol package, and identify wrong data packet；
Module 23-PD_RM verification environment reference model.It is responsible for generating corresponding expecting contract packet and row according to USB_PD protocol requirement
For (such as packet loss, time-out, re-transmission, counter), module 24-CPU_SCOREBOARD is received to the data received from DUT, and from RM
To data be compared；
Module 26-virtual sequencer is for managing all sequencer and virtual in platform concentratedly
The module of sequence.The benefit of centralized management is that different virtual can be successively executed in the same function body
Sequence facilitates verifying so as to avoid the confusion of the multiple virtual sequence execution sequences of complicated use-case bring
Sequencing between personal management difference virtual sequence.
Module 27-config configuration file configures DUT and verification environment, can make according to different testcase demands
The realization of test_case is more flexible and convenient；
Module 28-Functional Coverage module. function coverage module, being capable of all authentication functions of programming count
The coverage rate of group verifies the completeness of work.
The present invention is not limited to the above-described embodiments, anyone should learn make under the inspiration of the present invention with the present invention
With same or similar technical solution, fall within the scope of protection of the present invention.
Technology not described in detail in the present invention, shape, construction portion are well-known technique.
Claims (7)
1. a kind of USB PD fast charge protocol chip checking method based on RISC_V processor, it is characterized in that: being verified using UVM
Methodology and systemverilog verify language, utilize expansible chip interface behavior model driver, moniter building
Verification platform implements functional verification to USB_PD chip.
2. a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor according to right 1,
Be characterized in that: verification platform is by following module composition:
The top layer TOP_env of the entire verification environment of module 1--；
Module 2-- design USB_PD_DUT to be measured；
The various verification environment interface interface for needing to be connected with DUT of module 3--；
Register model REG_MOD of the module 4-- based on UVM_REG；
Module 5--REG2AHB_Adapter, the translation type for being responsible for register model REG_MOD and AHB_ENV turn
Change function；
Module 6--AHB bus access verification environment AHB_ENV；
The sequencer of sequence is received in module 7--AHB_ENV；
The excitation sending module driver of module 8--AHB bus；
Module 9--CPU_ENV allows DUT to send USB_PD protocol package by configuration register and DMEM, and processing is interrupted, and core is handled
The USB_PD protocol package that piece receives；
The transmission agent of module 10--CPU_ENV is responsible for allowing DUT to send USB_PD protocol package by configuration register and DMEM；
Module 11--CPU_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected CPU_driver；
Module 12--CPU_ENV sends the driver of agent, is responsible for sending the excitation of read-write register and DMEM；
The reception agent of module 13--CPU_ENV is responsible for processing interrupt signal and handles the USB_PD protocol package that chip receives；
The monitoring module MONITOR of the reception agent of module 14--CPU_ENV, is responsible for monitoring interrupt signal and executes phase
Answer interrupt processing；
The reference model RM of module 15--CPU_ENV, it is responsible according to the desired protocol package of USB_PD protocol requirement generation and corresponding
Behavior (such as packet loss, time-out)；
The scoreboard SCOREBOARD of module 16--CPU_ENV, to the data received from DUT, and the data received from RM carry out
It compares；
Module 17--PD_ENV sends USB_PD protocol package to chip by CC interface, is connect by CC interface
Receive the USB_PD protocol package that chip is sent；
The transmission agent of module 18--PD_ENV is responsible for sending USB_PD protocol package to chip by CC interface；
Module 19--PD_ENV sends the sequencer of agent, is responsible for receiving from virtual_sequencer's
Sequence simultaneously gives sequence connected PD_driver；
Module 20--PD_ENV sends the driver of agent, responsible to generate the excitation for meeting USB_PD phy layer protocol data
It is sent to the CC pin of DUT；
The reception agent of module 21--PD_ENV is responsible for receiving the USB_PD protocol package that chip is sent by CC interface；
The monitoring module MONITOR of the reception agent of module 22--PD_ENV, is responsible for monitoring CC signal and is properly received correctly
PD protocol package, and identify wrong data packet；
The reference model RM of module 23--PD_ENV is responsible for generating corresponding expecting contract packet and behavior according to USB_PD protocol requirement
(such as packet loss, time-out retransmit, counter)；
The scoreboard SCOREBOARD of module 24--PD_ENV, to the data received from DUT, and the data received from RM are compared
It is right；
The library module 25--Sequence, for generating the testcase of various complexity；
Module 26--Virtual_sequencer, virtual sequencer are used to the various sequence of complicated testcase to distribute
To corresponding sequencer；
Module 27--config configuration file configures DUT and verification environment according to different testcase demands；
Module 28--Functional Coverage module. function coverage module, for the complete of statistical testing of business cycles work
Property；
29-Test_case of module, test case layer.
3. according to a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor of right 1 and 2
And verification platform, it is characterised in that: can be random and automation using the functional verification that the method implements USB_PD chip
It generates the data for meeting USB_PD agreement and is applied to chip.
4. according to a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor of right 1 and 2
And verification platform, it is characterised in that: correct core can be automatically generated using the functional verification that the method implements USB_PD chip
Piece feeds back expected data.
5. according to a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor of right 1 and 2
And verification platform, it is characterised in that: the acquisition chip that can be automated using the functional verification that the method implements USB_PD chip
The various data issued, and correct expected data automate and that verification environment generates is compared.
6. according to a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor of right 1 and 2
And verification platform, it is characterised in that: can be generated by unbound document using the functional verification that the method implements USB_PD chip
Various abnormal test and excitations, and verification environment can excitation generates correctly expectation extremely to these.
7. according to a kind of verification method of the USB_PD fast charge protocol chip based on RISC_V processor of right 1 and 2
And verification platform, it is characterised in that: can be by fixed in coverage rate group using the functional verification that the method implements USB_PD chip
The functional coverage point information of justice, the function that the functional coverage point information analysis according to acquisition obtains entire USB_PD chip are covered
Lid rate, to guarantee verification quality.
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| CN110602503A (en) * | 2019-08-01 | 2019-12-20 | 福州瑞芯微电子股份有限公司 | SOP packet decoding method, storage device and decoder suitable for USB-PD protocol |
| CN111859845A (en) * | 2020-06-16 | 2020-10-30 | 眸芯科技（上海）有限公司 | Detection system for connecting line from top layer inside chip to top layer outside chip and application |
| CN112231164A (en) * | 2020-12-11 | 2021-01-15 | 鹏城实验室 | Processor verification method, device and readable storage medium |
| CN114265766A (en) * | 2021-12-03 | 2022-04-01 | 湖南炬神电子有限公司 | Programmable multifunctional test system and method integrating PD rapid charging protocol |
| CN115037474A (en) * | 2022-04-14 | 2022-09-09 | 深圳曼巴微电子有限公司 | USB PD protocol chip and identity authentication method |
| CN117422025A (en) * | 2023-12-18 | 2024-01-19 | 青岛本原微电子有限公司 | RISC-V architecture-based random interrupt debugging verification system |
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| CN110602503A (en) * | 2019-08-01 | 2019-12-20 | 福州瑞芯微电子股份有限公司 | SOP packet decoding method, storage device and decoder suitable for USB-PD protocol |
| CN111859845A (en) * | 2020-06-16 | 2020-10-30 | 眸芯科技（上海）有限公司 | Detection system for connecting line from top layer inside chip to top layer outside chip and application |
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| CN112231164B (en) * | 2020-12-11 | 2021-08-27 | 鹏城实验室 | Processor verification method, device and readable storage medium |
| CN114265766A (en) * | 2021-12-03 | 2022-04-01 | 湖南炬神电子有限公司 | Programmable multifunctional test system and method integrating PD rapid charging protocol |
| CN115037474A (en) * | 2022-04-14 | 2022-09-09 | 深圳曼巴微电子有限公司 | USB PD protocol chip and identity authentication method |
| CN117422025A (en) * | 2023-12-18 | 2024-01-19 | 青岛本原微电子有限公司 | RISC-V architecture-based random interrupt debugging verification system |
| CN117422025B (en) * | 2023-12-18 | 2024-03-29 | 青岛本原微电子有限公司 | Random interrupt debugging verification system based on RISC-V architecture |
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Application publication date: 20190726 |