CN110047931B - 碳化硅平面垂直型场效应晶体管及其制作方法 - Google Patents

碳化硅平面垂直型场效应晶体管及其制作方法 Download PDF

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CN110047931B
CN110047931B CN201910304405.7A CN201910304405A CN110047931B CN 110047931 B CN110047931 B CN 110047931B CN 201910304405 A CN201910304405 A CN 201910304405A CN 110047931 B CN110047931 B CN 110047931B
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段宝兴
王彦东
黄芸佳
杨银堂
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Abstract

本发明提出了一种碳化硅平面垂直型场效应晶体管及其制作方法，该器件在N型漂移区的中间区域通过离子注入形成N+电流通道，P型基区以及相应的N+型源区和P+沟道衬底接触的下方通过离子注入还形成有P型屏蔽层。本发明有效地解决了源漏穿通问题，并降低了栅介质层中的峰值电场，改善了器件的击穿电压与导通损耗。

Description

碳化硅平面垂直型场效应晶体管及其制作方法
技术领域
本发明涉及功率半导体器件领域，尤其涉及一种碳化硅垂直型场效应晶体管。
背景技术
随着半导体技术的发展，传统的Si和GaAs半导体由于材料特性限制，在高温、高频、大功率以及抗辐射等方面越来越显出其不足和局限性，越来越多的领域如航天、航空、军事、通讯等迫切地需要能够承受高温又在高频大功率、抗辐照等方面有良好性能的半导体器件。碳化硅材料由于具有禁带宽度大，电子漂移饱和速度高、介电常数小、导电性能好的特点，其本身具有的优越性质及其在功率器件领域应用中潜在的巨大前景，宽带隙半导体材料得到了飞速的发展。
然而在宽带隙半导体中杂质一般采用离子注入工艺，注入结较浅，很容易出现源漏穿通现象，无法充分发挥宽禁带材料的优势。为了避免基区穿通效应，需要高掺杂浓度的P型基区，宽带隙材料特性会导致极高的阈值电压，此外在器件关断时，由于较高的电压，栅介质层中内会产生高电场，器件的寿命和可靠性也会大大降低。
发明内容
本发明提出一种碳化硅平面垂直型场效应晶体管，旨在进一步提高垂直型场效应晶体管的击穿电压，同时降低其导通电阻，改善器件性能。
本发明的技术方案如下：
该碳化硅平面垂直场效应晶体管，包括：
碳化硅材料的衬底，兼作漏区；
在衬底上表面形成碳化硅外延层，作为N型漂移区；
分别在碳化硅外延层上部的左、右两端区域形成的两处P型基区以及相应的N+型源区和P+沟道衬底接触；每一处P型基区中形成沟道，其中N+型源区与沟道邻接，P+沟道衬底接触相对于N+型源区位于沟道远端；
源极，覆盖P+沟道衬底接触与相应N+型源区相接区域的上表面；两处源极共接；
漏极，位于衬底下表面；
有别于现有技术的是：
N型漂移区的中间区域通过离子注入形成N+电流通道，该N+电流通道纵向贯通N型漂移区；N型漂移区的掺杂浓度由器件的耐压要求决定，N+电流通道的掺杂浓度远高于N型漂移区的掺杂浓度；
两处P型基区以及相应的N+型源区和P+沟道衬底接触的下方通过离子注入还形成有P型屏蔽层；
栅介质层覆盖所述碳化硅外延层上部的两侧沟道及其之间区域的表面；
栅极位于栅介质层上表面；
源极覆盖P+沟道衬底接触与N+型源区相接区域的上表面，两处源极共接。
基于以上方案，本发明还进一步作了如下优化：
所述N型漂移区的掺杂浓度比N+电流通道的掺杂浓度小1-3个数量级。
所述P型屏蔽层的长度大于或等于P型基区、N+型源区和P+沟道衬底接触的整体长度。
所述N+电流通道的掺杂浓度典型值为1×1016cm-3～1×1018cm-3，N型漂移区的掺杂浓度典型值为1×1015cm-3～1×1016cm-3。
所述P型屏蔽层的掺杂浓度典型值为1×1017cm-3～1×1019cm-3。
所述P型基区的掺杂浓度典型值为1×1016cm-3～1×1017cm-3。
所述栅介质层的厚度为0.02～0.1μm。
所述P型屏蔽层与N+电流通道相接或保持间距。
所述源极、栅极、漏极均通过欧姆接触相连。
一种制作上述碳化硅平面垂直型场效应晶体管的方法，包括以下步骤：
(1)取碳化硅材料作为衬底同时作为漏区；
(2)在衬底上形成外延层作为轻掺杂漂移区；
(3)在外延层中间通过离子注入形成N+电流通道；
(4)根据所设计击穿电压的要求重复步骤(2)和(3)达到所要求的漂移区厚度；
(5)在碳化硅外延层上部的左、右两端区域采用离子注入形成P型屏蔽层、P型基区及其N+型源区和P+沟道衬底接触，形成相应的沟道；
(6)在两侧沟道及中间表面形成栅介质层，并淀积金属形成栅极；
(8)在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
(9)在接触孔内淀积金属并刻蚀(去除周边其余的钝化层)形成源极，并将两处源极共接。
本发明技术方案的有益效果如下：
本发明利用N+重掺杂构造新的电流通道，改变了传统器件中电流分布；同时采用P型屏蔽层解决了宽带隙半导体材料在高电压下容易发生源漏穿通的问题。器件关断时，P型屏蔽层有效的降低了栅介质层中的峰值电场，提高了器件的可靠性，在正向导通时，由于新的电流通道，可以获得较低的导通电阻，在器件关断时，N+电流通道被夹断，整个漂移区承担反向偏压，可以获得较高的击穿电压，弱化了击穿电压与漂移区浓度之间的矛盾关系。
本发明的碳化硅平面垂直型场效应晶体管，在相同漂移区长度的情况下，具有更高的耐压和更低的导通损耗。
附图说明
图1是本发明的结构示意图。
其中，1-源极；2-栅介质层；3-栅极；4-P型基区；5-N+型源区；6-P+沟道衬底接触(P+型体区)；7-P型屏蔽层；8-N型漂移区；9-漏区；10-漏极；11-N+电流通道。
具体实施方式
下面结合附图以N沟道碳化硅平面垂直型场效应晶体管为例介绍本发明。
如图1所示，本实施例的结构包括：
碳化硅材料的衬底，兼作漏区9；
衬底上的N型碳化硅外延层，作为N型漂移区8；N型漂移区8的中间区域通过离子注入形成N+电流通道11，该N+电流通道11纵向贯通N型漂移区8；
分别在碳化硅外延层上部的左、右两端区域形成的两处P型基区4以及相应的N+型源区5和P+沟道衬底接触6；每一处P型基区4中形成沟道，其中N+型源区5与沟道邻接，P+沟道衬底接触6相对于N+型源区5位于沟道远端；
在N+型源区5和P+沟道衬底接触6整体的上表面形成的源极1；
栅介质层2覆盖碳化硅外延层上部的两侧沟道及其之间区域的表面；栅极3为平面结构，位于栅介质层上表面；
在漏区9下表面形成的漏极10。
N型漂移区的厚度和由器件的耐压要求决定，N+电流通道的掺杂浓度以及深度由器件的导通损耗决定。
P型屏蔽层的浓度、厚度、长度由器件的耐压要求决定，P型基区的浓度由器件的阈值电压决定。
N型漂移区的掺杂浓度根据设计的击穿电压确定，典型掺杂浓度范围为1×1015cm-3～1×1016cm-3。
N+电流通道的掺杂浓度根据设计的击穿电压确定，典型掺杂浓度范围为1×1016cm-3～1×1018cm-3。
P型基区的掺杂浓度根据设计的阈值电压确定，典型掺杂浓度范围为1×1016cm-3～1×1017cm-3。
P型屏蔽层的掺杂浓度根据设计的击穿电压确定，典型掺杂浓度范围为1×1017cm-3～1×1019cm-3。
N型碳化硅外延层的厚度根据设计的击穿电压确定，例如：耐压为800V时，N型宽带隙外延层的厚度大约为5μm。
栅介质层的厚度根据阈值电压确定，典型值为0.02～0.1μm。
该器件可按照以下步骤制备：
(1)取碳化硅材料制作N+型衬底，同时作为漏区；
(2)在N+型衬底上表面形成碳化硅材料的N型外延层，并在中间区域通过离子注入形成N+电流通道；外延注入的次数由所设计的击穿电压确定，例如耐压800V时，漂移区的长度典型值为5μm，需要2～3次外延注入；
(3)在N+型衬底下表面形成金属化漏极；
(4)在掩膜的保护下，在碳化硅外延层上部的左、右两端区域采用离子注入形成P型屏蔽层、P型基区及其N+型源区和P+沟道衬底接触，形成相应的沟道；
(5)在两侧沟道及中间表面形成栅介质层，并淀积金属形成栅极；
(7)在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
(8)在接触孔内淀积金属并刻蚀(去除周边其余的钝化层)形成源极，并将两处源极共接。
本发明采用轻掺杂的N型漂移区和重掺杂的N+电流通道组成特殊的漂移区，同时结合P型屏蔽层。当器件正向导通时，由于重掺杂形成的N+导电通道，可以获得较低的导通电阻，在器件关断时，随着漏极电压的升高，P型屏蔽层附近的耗尽区扩展，N+电流通路被夹断后，漂移区承担反向偏压，可以获得较高的击穿电压，因此弱化了击穿电压与漂移区浓度之间的矛盾关系。而且，由于P型屏蔽层的作用，解决了碳化硅半导体材料在高电压下容易发生源漏穿通的问题，降低了栅介质层中的峰值电场，提高了器件的可靠性，同时碳化硅材料的高热导率特性有利于器件的散热，器件性能有效改善。结合以上优势，与传统碳化硅垂直型场效应晶体管相比，本发明提出的结构具有更高的耐压和更低的导通损耗。
经ISE TCAD仿真表明，本发明提出的新型器件的性能较之于传统宽禁带垂直型场效应晶体管明显提升，当两种器件具有相等的击穿电压时，新型器件的导通电阻下降了30％以上。
本发明中的垂直型场效应晶体管当然也可以为P型沟道，其结构与N沟道垂直型场效应晶体管等同，也应当视为属于本申请权利要求的保护范围，在此不再赘述。
另外，虽然本发明主要是基于宽带隙半导体材料(碳化硅)的器件进行的改进，但其原理同样适用于其他半导体材料，如硅、金刚石等。因此，基于本发明的器件结构仅作材料替换，也应视为属于本申请权利要求的保护范围。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换的方案也落入本发明的保护范围。

Claims (7)

1.碳化硅平面垂直型场效应晶体管，其特征在于，包括：
碳化硅材料的衬底，兼作漏区(9)；
在衬底上表面形成碳化硅外延层，作为N型漂移区(8)；
分别在碳化硅外延层上部的左、右两端区域形成的两处P型基区(4)以及相应的N+型源区(5)和P+沟道衬底接触(6)；每一处P型基区(4)中形成沟道，其中N+型源区(5)与沟道邻接，P+沟道衬底接触(6)相对于N+型源区(5)位于沟道远端；
源极(1)，覆盖P+沟道衬底接触(6)与相应N+型源区(5)相接区域的上表面；两处源极共接；
漏极(10)，位于衬底下表面；
所述N型漂移区(8)的中间区域通过离子注入形成N+电流通道(11)，该N+电流通道(11)纵向贯通N型漂移区(8)；N型漂移区(8)的掺杂浓度由器件的耐压要求决定，N+电流通道(11)的掺杂浓度为1×1016cm-3～1×1018cm-3，N型漂移区(8)的掺杂浓度为1×1015cm-3～1×1016cm-3；
两处P型基区(4)以及相应的N+型源区(5)和P+沟道衬底接触(6)的下方通过离子注入还形成有P型屏蔽层(7)；P型基区的掺杂浓度为1×1016cm-3～1×1017cm-3；P型屏蔽层(7)的掺杂浓度为1×1017cm-3～1×1019cm-3；
栅介质层(2)覆盖所述碳化硅外延层上部的两侧沟道及其之间区域的表面；
栅极(3)位于栅介质层上表面；
源极(1)覆盖P+沟道衬底接触(6)与N+型源区(5)相接区域的上表面，两处源极共接。
2.根据权利要求1所述的碳化硅平面垂直型场效应晶体管，其特征在于：所述N型漂移区(8)的掺杂浓度比N+电流通道(11)的掺杂浓度小1-3个数量级。
3.根据权利要求1所述的碳化硅平面垂直型场效应晶体管，其特征在于：所述P型屏蔽层(7)的长度大于或等于P型基区(4)、N+型源区(5)和P+沟道衬底接触(6)的整体长度。
4.根据权利要求1所述的碳化硅平面垂直型场效应晶体管，其特征在于：所述栅介质层的厚度为0.02～0.1μm。
5.根据权利要求1所述的碳化硅平面垂直型场效应晶体管，其特征在于：所述P型屏蔽层(7)与N+电流通道(11)相接或保持间距。
6.根据权利要求1所述的碳化硅平面垂直型场效应晶体管，其特征在于：所述源极、栅极、漏极均通过欧姆接触相连。
7.一种制作权利要求1所述碳化硅平面垂直型场效应晶体管的方法，包括以下步骤：
(1)取碳化硅材料为衬底，同时作为漏区；
(2)在衬底上形成碳化硅外延层作为N型漂移区；
(3)在碳化硅外延层中间区域上通过离子注入形成N+电流通道；
(4)根据耐压要求重复步骤(2)和(3)达到所需的N型漂移区厚度；
(5)在碳化硅外延层上部的左、右两端区域采用离子注入形成P型屏蔽层、P型基区及其N+型源区和P+沟道衬底接触，形成相应的沟道；
(6)在两侧沟道及中间表面形成栅介质层，并淀积金属形成栅极；
(8)在器件表面淀积钝化层，并在对应于源极的位置刻蚀接触孔；
(9)在接触孔内淀积金属并刻蚀，形成源极，并将两处源极共接。
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