CN110047826A - Semiconductor packages and its manufacturing method - Google Patents
Semiconductor packages and its manufacturing method Download PDFInfo
- Publication number
- CN110047826A CN110047826A CN201910037043.XA CN201910037043A CN110047826A CN 110047826 A CN110047826 A CN 110047826A CN 201910037043 A CN201910037043 A CN 201910037043A CN 110047826 A CN110047826 A CN 110047826A
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- China
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- encapsulant
- substrate
- interconnection
- semiconductor packages
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- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of semiconductor packages and its manufacturing methods.As non-limiting embodiment, various aspects of the invention provide semiconductor packages and its manufacturing method comprising the shielding on its multiple side.
Description
Technical field
The invention relates to semiconductor packages and its manufacturing methods.
The cross reference of related application/be incorporated by reference into:
The present invention is to submit entitled " SEMICONDUCTOR PACKAGE AND on January 15th, 2018
U.S. Patent Application No. 15/871, the 617 part connecting cases of MANUFACTURING METHOD THEREOF ", the U.S. are special
Benefit application the 15/871,617th is to submit entitled " SEMICONDUCTOR PACKAGE AND on May 8th, 2016
U.S. Patent Application No. 15/149, the 144 part connecting cases of MANUFACTURING METHOD THEREOF ", the U.S. are special
Benefit application the 15/149th, 144 is U.S. Patent No. 9 now, 935, No. 083, refers to and advocates to mention on November 12nd, 2015
The South Korea of entitled " the SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME " that hands over
The priority that patent application the 10-2015-0159058th, and advocate the equity of the South Korea patent application case, entire contents are logical
It crosses and is incorporated herein by reference.
Background technique
Current semiconductor packages and the method for forming semiconductor packages are insufficient, for example, cause cost it is excessively high, can
By property reduction, unsuitable shielding, too big package dimension etc..By by existing and conventional method and such as remaining of present application
The present invention illustrated in part referring to attached drawing is compared, other existing and conventional method limitations and disadvantage are for this field
It will become obvious for skilled worker.
Summary of the invention
The method that various aspects of the invention provide semiconductor packages and manufacture semiconductor packages.As non-limiting reality
Example is applied, various aspects of the invention provide semiconductor packages and its manufacturing method comprising the shielding on its multiple side.
Aspect according to the present invention, a kind of semiconductor packages comprising: substrate comprising: substrate top side comprising base
The first liner and substrate top second pad at the top of plate；Substrate bottom side comprising the liner of base plate bottom first and base plate bottom the
Two liners；Substrate cross side；First electronic device on the substrate top side and is coupled to the lining of substrate top first
Pad faces the substrate top side wherein first electronic device includes: first device bottom side；First device top side；And
First device cross side；Driven member on the substrate top side and is coupled to the liner of substrate top second；First
Encapsulant is at least encapsulated the substrate top side, the driven member and first electronic device, wherein first capsule
Sealing object includes: the first encapsulant bottom side, faces the substrate top side；First encapsulant top side；And first encapsulant it is lateral
Side；Second electronic device on the substrate bottom side and is coupled to the liner of base plate bottom first, wherein described second
Electronic device includes: second device top side, faces the substrate bottom side；Second device bottom side；And second device cross side；
Outside interconnection on the substrate bottom side and includes: that top interconnects end, is coupled to the base plate bottom second and pads；
And lower section interconnects end；Second encapsulant is at least encapsulated the substrate bottom side and the second electronic device, wherein described
Second encapsulant includes: the second encapsulant top side, faces the substrate bottom side；Second encapsulant bottom side；And second be encapsulated
Object cross side, wherein lower section interconnection end is also lower than second encapsulant bottom side；And electromagnetic interference (Electro
Magnetic Interference, abbreviation EMI) shielding, it at least surrounds: first encapsulant top side；Described first is encapsulated
Object cross side；And the substrate cross side, wherein the electromagnetic interference shield is opened with the external interconnection barriers.In some realities
It applies in example, at least part of the second device bottom side is exposed from second encapsulant.In some embodiments, described
One device lateral side is also longer than the second device cross side in vertical direction.In some embodiments, it described first is encapsulated
Object includes the first layer with molding material；And second encapsulant includes the second layer with the molding material.?
In some embodiments, the external interconnection includes: to be encapsulated section, by the first part of second encapsulant surround and with
First part's contact；Exposure section, by the second part of second encapsulant surround and with the second part
It separates；And prominent section, it is also lower than second encapsulant bottom side.In some embodiments, the second encapsulant packet
Platform portion (ledge) is included, the external interconnection is laterally surrounded and is located at the first part of second encapsulant and described
Between second part.In some embodiments, the electromagnetic interference shield includes continuous shape-preserving coating, conforms to described
One encapsulant top side, the first encapsulant cross side, the substrate transverse side and the second encapsulant cross side
Respective profile.In some embodiments, the electromagnetic interference shield covers the second encapsulant cross side, so as to derive from described
Second encapsulant bottom side and the exposure height being measured in vertical direction along the second encapsulant cross side are from described
Electromagnetic interference shield is exposed no more than 0 to 50 μm.In some embodiments, the second device bottom side and described second is encapsulated
Object bottom side is coplanar.
Aspect according to the present invention, a kind of semiconductor packages comprising: substrate comprising: substrate top side comprising base
The first liner and substrate top second pad at the top of plate；Substrate bottom side comprising substrate third liner and substrate interconnection liner；With
And substrate cross side；First device on the substrate top side and is coupled to the liner of substrate top first, wherein institute
Stating first device includes: first device bottom side, faces the substrate top side；First device top side；And first device is lateral
Side；Second device on the substrate top side and is coupled to the liner of substrate top second；First encapsulant, until
It is encapsulated the substrate top side, the first device and the second device less, wherein first encapsulant includes: the first capsule
Object bottom side is sealed, the substrate top side is faced；First encapsulant top side；And the first encapsulant cross side；3rd device,
On the substrate bottom side and it is coupled to the substrate third liner, wherein the 3rd device includes: 3rd device top side,
In face of the substrate bottom side；3rd device bottom side；And 3rd device cross side；Interconnection, the substrate bottom side and by
It is coupled to the substrate interconnection liner, wherein described interconnect provides external interface to the semiconductor packages and include: top
End is interconnected, the substrate interconnection liner is coupled to；And lower section interconnects end；Second encapsulant is encapsulated the substrate base
At least part in side and the 3rd device each, wherein second encapsulant includes: the second encapsulant top side,
It faces the substrate bottom side；Second encapsulant bottom side；And the second encapsulant cross side；And electromagnetic interference (EMI) shielding,
It is at least surrounded: first encapsulant top side；The first encapsulant cross side；And the substrate cross side, in which: institute
It is also lower than second encapsulant bottom side to state lower section interconnection end；And the first device, the second device or the third
At least one of device is electronic device；And in the first device, the second device or the 3rd device extremely
Few one is driven member.It in some embodiments, further comprise bottom electromagnetic interference (EMI) shielding, at least: surrounding institute
State 3rd device cross side；Second encapsulant is extended through from the substrate bottom side and towards second encapsulant bottom
Side；It and does not include thin-sheet metal.In some embodiments, at least part of the 3rd device bottom side is from second capsule
Seal object exposure.In some embodiments, first encapsulant includes the first layer with molding material；And second capsule
Sealing object includes the second layer with the molding material.In some embodiments, the external interconnection includes: to be encapsulated section,
It is surrounded and contacted with the first part by the first part of second encapsulant；Exposure section, by second capsule
The second part of envelope object is surrounded and is separated with the second part；And prominent section, than second encapsulant bottom side
It is also low.In some embodiments, second encapsulant includes platform portion, laterally surrounds the interconnection and is located at second capsule
It seals between the first part and the second part of object.In some embodiments, the electromagnetic interference shield includes continuous
Shape-preserving coating, conform to first encapsulant top side, the first encapsulant cross side, the substrate transverse side with
And the respective profile of the second encapsulant cross side.
Aspect according to the present invention, a kind of manufacturing method comprising: substrate is provided comprising: substrate top side comprising
The liner of substrate top first and substrate top second pad；Substrate bottom side comprising substrate third liner and substrate interconnection liner；
And substrate cross side；First device is provided, on the substrate top side and the substrate top first is coupled to and pads,
Wherein the first device includes: first device bottom side, faces the substrate top side；First device top side；An and device
Cross side；Second device is provided, on the substrate top side and is coupled to the liner of substrate top second；First is encapsulated
Object is encapsulated the substrate top side, the first device and the second device, wherein first encapsulant includes:
One encapsulant bottom side faces the substrate top side；First encapsulant top side；And the first encapsulant cross side；Third is provided
Device on the substrate bottom side and is coupled to the substrate third liner, wherein the 3rd device includes: third dress
Top set side faces the substrate bottom side；3rd device bottom side；And 3rd device cross side；And interconnection is provided, in institute
The substrate interconnection liner is stated on substrate bottom side and be coupled to, wherein the interconnection includes: that top interconnects end, is coupled to
The substrate interconnection liner；And lower section interconnects end；And the second encapsulant is provided, it is encapsulated the substrate bottom side, described the
At least part in three devices and the interconnection each, wherein second encapsulant includes: the second encapsulant top side,
It faces the substrate bottom side；Second encapsulant bottom side；And the second encapsulant cross side, in which: the lower section interconnects end ratio
Second encapsulant bottom side is also low；And at least one in the first device, the second device or the 3rd device
Person is electronic device；And at least one of the first device, the second device or described 3rd device are passive structures
Part.In some embodiments, second encapsulant is encapsulated at least part of the interconnection.In some embodiments, into one
Step includes forming the first electromagnetic interference (EMI) shielding comprising at least: first encapsulant top side；First encapsulant
Cross side and the substrate cross side.In some embodiments, the interconnection includes: to be encapsulated section, by second capsule
The first part of envelope object surrounds and contacts with the first part；Exposure section, by second of second encapsulant
Divide and surrounds and separated with the second part；And prominent section, it is also lower than second encapsulant bottom side.
Detailed description of the invention
Fig. 1 shows the sectional views of the semiconductor packages of the embodiment of the present invention；
Fig. 2 indicates the flow chart that the method for semiconductor packages is manufactured shown in Fig. 1；
Fig. 3 A to 3E indicates the sectional view of each step of the method for manufacturing manufacture semiconductor packages shown in Fig. 2；
Fig. 4 indicates the sectional view of the semiconductor packages of another embodiment of the present invention；
Fig. 5 A and 5B expression manufacture semiconductor shown in Fig. 4 by semiconductor package fabrication method shown in Fig. 2
The sectional view of each step of encapsulation；
Fig. 6 indicates the plan view and sectional view of the structure of fixture shown in Fig. 5 A；
Fig. 7 indicates another embodiment of the present invention to manufacture the flow chart of the method for semiconductor packages shown in Fig. 4；
Fig. 8 A to 8C indicates the sectional view of each step of the method for manufacture semiconductor packages shown in Fig. 7；
Fig. 9 A indicates the sectional view of the semiconductor packages according to an embodiment；
Fig. 9 B indicates the amplifier section of the semiconductor packages of Fig. 9 A；
Figure 10 A to 10C indicates each initial semiconductor packages assembly stage；
Figure 11 A to 11E indicates each subsequent semiconductor packages assembly for leading to the semiconductor packages of Fig. 9；
Figure 12 A indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 12 B indicates the amplifier section of the semiconductor packages of Figure 12 A；
Figure 13 A to 13E indicates each subsequent semiconductor packages assembly for leading to the semiconductor packages of Figure 12；
Figure 14 A indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 14 B indicates the amplifier section of the semiconductor packages of Figure 14 A；
Figure 15 A to 15D indicates each subsequent semiconductor packages assembly for leading to the semiconductor packages of Figure 14；
Figure 16 indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 17 A to 17C indicates each subsequent semiconductor packages assembly for leading to the semiconductor packages of Figure 16；
Figure 18 indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 19 indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 20 indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 21 indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 22 A indicates the sectional view of the semiconductor packages according to an embodiment；
Figure 22 B indicates the amplifier section of the semiconductor packages of Figure 22 A；
Figure 23 A to 23E indicates each subsequent semiconductor packages assembly for leading to the semiconductor packages of Figure 22.
Specific embodiment
Various aspects of the invention are presented by providing example in following discussion.Such example is non-limiting, and
Therefore the range of various aspects of the invention should not be limited by any specific feature of provided embodiment.In following discussion
In, term " for example ", " such as " and " demonstration " be non-limiting and usually with " by embodiment rather than limitation ",
" such as and without restriction " and fellow are synonymous.
As used herein, " and/or " refer to " and/or " connection list in one or more any projects.As
Embodiment, " x and/or y " mean any element in three element sets { (x), (y), (x, y) }.In other words, " x and/or
Y " indicates " in x and y one or two ".As another embodiment, " x, y and/or z " refer to seven element sets (x), (y),
(z), (x, y), (x, z), (y, z), (x, y, z) } in any element.In other words, " x, y and/or z " mean " x, y and
One or more in z ".
Term used in the present invention is merely for for the purpose of describing particular embodiments, it is undesirable that the limitation present invention.Such as this
As used herein, unless the context clearly dictates otherwise, otherwise singular is also intended to encompass plural form.It will further manage
Solution, the terms "include", "comprise", " having " and/or " having " when used in this manual, specify institute's features set forth,
Entirety, step, operation, the presence of component and/or component, but be not excluded for one or more other features, entirety, step, operation,
Component, component and/or the presence of its group or addition.
Although it will be appreciated that term first, second etc. can be used to describe various assemblies herein, these components
It should not be limited by these terms.These terms are only used to separate a component with another component.Therefore, for example, exist
Without departing from the teachings of the present invention, first assembly discussed below, first component or the first section are referred to alternatively as second
Component, second component or the second section.Similarly, the kind spatial terminology of such as " top ", " lower section ", " side " and fellow can quilts
Using to distinguish a component and another component with opposite method.It should be understood, however, that component can differently be determined
To, for example, semiconductor packages can lateral rotation so that its " top " surface level ground to and its " side " surface perpendicular to the ground
To without departing from the teachings of the present invention.
In the accompanying drawings, for the sake of clarity, the thickness of laminated, region and/or component can be amplified.Therefore, this hair
Bright scope should not be limited by this thickness or size.In addition, in the accompanying drawings, identical appended drawing reference refers herein to identical
Component.Have apostrophe (') component of component symbol can be similar to the component of the not corresponding assembly symbol of apostrophe.
It will also be understood that when component A referred to as " is connected to " or when " being coupled to " component B, component A can be directly connected to
To component B or be connected indirectly to component B (for example, intermediate module C (and/or other assemblies) can component A and component B it
Between).
Certain embodiments of the present invention relates to semiconductor packages and its manufacturing method.
For exchanging the various electronic devices of signal and being incorporated into respectively with multiple semiconductor packages that various structures manufacture
In kind electronic system, therefore electromagnetic interference may be inevitably generated in electrically operated semiconductor packages and electronic device
(EMI)。
EMI can be generally defined as the synthesis radiation of electric and magnetic fields.EMI can be by flowing in conductive material and magnetic field
Electric current formed electric field generate.
If EMI is that the electronic device from semiconductor packages and dense pack on mainboard generates, other are adjacent
Semiconductor packages directly or indirectly may be influenced and be likely to be broken by EMI.
Semiconductor packages and its manufacturing method are provided in terms of various aspects of the invention, it can be by the two of substrate
Mouldings are formed on a surface to prevent warpage and can shield by being formed as the EMI shielded layer of Overmolded object and substrate
Cover electromagnetic interference (EMI).
Aspect according to the present invention provides a kind of semiconductor packages comprising: substrate has first surface and with the
The opposite second surface in one surface；At least one first electronic device forms on the first surface and is electrically connected to substrate；First
Mouldings are formed on the first surface to cover the first electronic device；Second mouldings are formed as covering second surface；
Multiple first conductive bumps form on a second surface and are electrically connected to substrate and pass through the second mouldings；Electromagnetic interference
(EMI) shielded layer, be formed about surface, the first mouldings and the second mouldings of substrate with the first conductive bumps interval
It opens；Multiple second conduct electricity convex block be formed on a surface of the second mouldings be electrically connected respectively to it is multiple first conduction it is convex
Block.
Another aspect according to the present invention provides a kind of method for manufacturing semiconductor packages, and semiconductor packages includes: base
Plate has first surface and the second surface opposite with first surface；At least one first electronic device, is formed in first surface
It goes up and is electrically connected to substrate；And multiple second conductive bumps, it is formed on a second surface and is electrically connected to substrate, this method
It include: to form the first mouldings on the first surface to cover the first electronic device and form the second mouldings on a second surface
To cover the first conductive bumps, the second mouldings are ground so that multiple first conductive bumps are exposed to outside, form multiple second
Conductive bumps are electrically connected respectively to multiple first conductive bumps of exposure, and placing clamp is below the second mouldings to surround
Multiple second conductive bumps, and EMI shielded layer is formed to cover the surface of substrate, the first mouldings and the second mouldings, it passes through
Outside is exposed to by fixture.
Another aspect according to the present invention provides a kind of method for manufacturing semiconductor packages, and semiconductor packages includes: base
Plate has first surface and the second surface opposite with first surface；At least one first electronic device, is formed in first surface
It goes up and is electrically connected to substrate；And multiple second conductive bumps, it is formed on a second surface and is electrically connected to substrate, this method
It include: to form the first mouldings on the first surface to cover the first electronic device and form the second mouldings on a second surface
To cover the first conductive bumps, the second mouldings are ground so that multiple first conductive bumps are exposed to outside, form EMI shielded layer
Surface, the first mouldings and the second mouldings of substrate are completely covered, multiple exposed holes are formed in EMI shielded layer with will be more
A first conductive bumps are exposed to outside, and form multiple second conductive bumps, pass through multiple exposed holes respectively and are electrically connected to
Exposed multiple first conductive bumps.
In one embodiment, a kind of manufacturing method may include providing substrate comprising: substrate top surface, with base
The first liner and substrate top second pad at the top of plate；Substrate surface, with the liner of base plate bottom first and substrate base
Portion second pads；And substrate lateral surfaces.This method also may include that the first electronic device is attached to substrate top surface, the
One electronic device is coupled to the liner of substrate top first and includes: first device first surface, faces substrate top surface；
First device lateral surfaces；And first device second surface, back to substrate top surface.This method also may include by first
Driven member is coupled to the liner of substrate top second, and applies the first encapsulant to be encapsulated substrate top surface, first passively
Component and the first electronic device, wherein the first encapsulant has the first encapsulant top surface and the first encapsulant lateral
Surface.This method also may include that second electronic device is attached to substrate surface, and second electronic device is coupled to substrate
Bottom first pads and includes: second device first surface, faces substrate surface；Second device lateral surfaces；And
Second device second surface, back to substrate surface.This method also may include providing the first outside interconnection, be coupled to
Base plate bottom second pads, and applies the second encapsulant to be encapsulated substrate surface and second electronic device, and second
Encapsulant includes the second encapsulant lateral surfaces.In one embodiment, this method may also include the first electromagnetic interference (EMI) shielding
Using laminated as one, at least surround: the first encapsulant top surface, the first encapsulant lateral surfaces and substrate transverse direction table
Face, wherein the first EMI shielding is opened in identical or another embodiment with external interconnection barriers, method also may include applying electromagnetism to do
Disturb (EMI) shielding, around second device periphery, contacted with the second encapsulant and do not include thin-sheet metal.
In one embodiment, semiconductor packages may include substrate, substrate top surface be included, with substrate top
First liner and substrate top second pad；Substrate surface, with the liner of base plate bottom first and base plate bottom second
Liner；And substrate lateral surfaces.Encapsulation also may include the first electronic device, on substrate top surface and be coupled to base
First pads at the top of plate, and the first electronic device includes: first device first surface, faces substrate top surface；First device
Lateral surfaces；With first device second surface again, back to substrate top surface.Encapsulation also may include being coupled to substrate top
It first driven member of the second liner and is encapsulated the first of substrate top surface, driven member and the first electronic device and is encapsulated
Object, the first encapsulant have the first encapsulant top surface and the first encapsulant lateral surfaces.Encapsulation also may include the second electricity
Sub-device on substrate surface and is coupled to the liner of base plate bottom first, and second electronic device includes: second device
First surface faces substrate surface；Second device lateral surfaces；And second device second surface, back to substrate
Bottom surface.Encapsulation also may include being coupled to outside the liner of base plate bottom second and first including the first outside interconnection height
Interconnect and be encapsulated the second encapsulant of substrate surface and second electronic device, the second encapsulant includes: second to be encapsulated
Object lateral surfaces and the second encapsulant height, wherein the first outside interconnection height is outstanding more farther than the second encapsulant height.
Encapsulation may also include the first electromagnetic interference (EMI) shielding, at least surround: the first encapsulant top surface, the first encapsulant are horizontal
To surface and substrate lateral surfaces, wherein the first EMI shielding is opened with external interconnection barriers.
In one embodiment, a kind of manufacturing method can include: substrate is provided, includes substrate top surface comprising base
The first liner and substrate top second pad at the top of plate；Substrate surface comprising substrate third liner and substrate interconnection lining
Pad；And substrate cross side；First device is provided, on substrate top surface and is coupled to the lining of substrate top first
Pad, first device includes: first device bottom surface, faces substrate top surface；First device lateral surfaces；And back to
The first device top surface on substrate top surface；Second device component is provided, the liner of substrate top second is coupled to；It mentions
For the first encapsulant, it is encapsulated substrate top surface, first device and second device, the first encapsulant has the first encapsulant
Top surface and the first encapsulant lateral surfaces；3rd device is attached to the liner of the substrate third on substrate surface,
3rd device includes: 3rd device top surface, faces substrate surface；3rd device lateral surfaces；And back to base
The 3rd device bottom surface of plate bottom surface；First interconnection is provided, on the substrate surface and is coupled to
Substrate interconnection liner, the first interconnection include interconnecting prominent section and providing external interface to semiconductor packages；Apply the second capsule
Object is sealed, substrate surface, at least partly 3rd device and the first interconnection are encapsulated, the second encapsulant includes the second encapsulant
Bottom surface and the second encapsulant lateral surfaces；It interconnects prominent section and projects through the second encapsulant bottom surface；First dress
It sets, at least one of second device or 3rd device are electronic devices；And in first device, second device or 3rd device
At least one be driven member.
In one embodiment, a kind of semiconductor packages can include: substrate comprising: substrate top surface comprising substrate
The liner of top first and substrate top second pad；Substrate bottom side comprising substrate third liner and substrate interconnection liner；And
Substrate cross side；First device on substrate top side and is coupled to the liner of substrate top first, first device packet
Include: first device bottom surface faces the substrate top surface；First device cross side；And back to substrate top table
The first device top surface in face；Second device component is coupled to the substrate top second and pads；First encapsulant,
It is encapsulated substrate top surface, first device and second device, the first encapsulant have the first encapsulant top surface and
First encapsulant lateral surfaces；3rd device on substrate surface and is coupled to substrate third liner, 3rd device
Include: 3rd device top surface, faces substrate surface；3rd device lateral surfaces；And back to base plate bottom table
The 3rd device bottom surface in face；First interconnection, on the substrate surface and is coupled to substrate interconnection liner,
First interconnection includes interconnecting prominent section and providing external interface to semiconductor packages；Second encapsulant, is encapsulated substrate base
Portion surface, at least partly 3rd device and the first interconnection, the second encapsulant include the second encapsulant bottom surface and second
Encapsulant lateral surfaces；First electromagnetic interference (EMI) shielding, at least surrounds the first encapsulant top surface, the first encapsulant
Lateral surfaces and substrate lateral surfaces；Wherein 3rd device bottom surface is exposed from the second encapsulant；It is prominent to interconnect prominent section
Pass through the second encapsulant bottom surface out；At least one of first device, second device or 3rd device are electronic devices；With
And at least one of first device, second device or 3rd device are driven members.
In one embodiment, a kind of manufacture may include include providing to be attached to the top device of substrate, substrate, which has, to be attached
There are substrate top side, substrate lateral surfaces and the substrate bottom side opposite with substrate top side of top device；Top device has attached
It is connected to the top device bottom side, top device lateral surface and the top device top opposite with top device bottom side of substrate top side
Side；First encapsulant is provided, substrate top side and top device top side are encapsulated；The lower section dress for being attached to the bottom side of substrate is provided
Set, lower section device include with the lower section device top side of convex block, the lower section device lateral surface for being coupled to substrate surface with
And the lower section device bottom side opposite with substrate bottom side；First interconnection is provided, substrate bottom side and from below device lateral are attached to
Displacement；Second encapsulant is provided, substrate bottom side, lower section device and the first interconnection are encapsulated；And provide the first electromagnetic interference
(EMI) it shields, surrounds at least part of the first encapsulant top surface and a part of the first encapsulant lateral surfaces,
Wherein lower section bottom of device surface is exposed from the second encapsulant；Top device lateral surface is greater than lower section device in vertical direction
Lateral surfaces；At least one of top device or lower section device are electronic devices；And top device or lower section device are at least
One is driven member.
It, can be by two of substrate as described above, in semiconductor packages according to the present invention and its manufacturing method
Mouldings are formed on surface to prevent warpage, and can be by forming shielded layer with the EMI of Overmolded object and substrate shielding
Layer shields electromagnetic interference (EMI).
Below with reference to the accompanying drawings detailed description of the present invention other embodiments, feature and advantage and various realities of the invention
Apply example structurally and operationally.
Referring to Fig. 1, the sectional view of the semiconductor packages of the embodiment of the present invention is shown.
As shown in fig. 1, semiconductor packages 100 include substrate 110, the first electronic device 120, second electronic device 130,
First mouldings 140, the second mouldings 150, the first conductive bumps 160, the second conductive bumps 170 and electromagnetic interference (EMI) screen
Cover layer 180.
Substrate 110 is by panel forming, with first surface 110a and the second surface opposite with first surface 110a
110b.Herein, the first surface 110a of substrate 110 can be top surface, and second surface 110b can be bottom surface, on the contrary
?.Substrate 110 includes multiple first line patterns 111 being formed on first surface 110a and is formed on second surface 110b
Multiple second line patterns 112.In addition, substrate 110 may also include multiple conductive patterns 113, it is electrically connected to form in substrate 110
First surface 110a on first line pattern 111 and the second line pattern 112 for being formed on second surface 110b.Conductive pattern
113 can be configured as and penetrate between the first surface 110a of substrate 110 and second surface 110b or partly penetrate to connect
Connect the multiple line patterns formed by multiple layers.That is, conductive pattern 113 can be straight in the case where substrate 110 is single layer
The first line pattern 111 and the second line pattern 112 are connect in succession, or additional line pattern can be used by the first line pattern 111
It is connected with the second line pattern 112.That is, the first line pattern 111 of substrate 110, the second line pattern 112 and conductive pattern
113 can be realized with various structures and type, but aspect of the invention is without being limited thereto.
First electronic device 120 is mounted on the First Line that substrate 110 is electrically connected on the first surface 110a of substrate 110
Pattern 111.First electronic device 120 may include semiconductor grain 121 and driven member 122, can be according to semiconductor packages 100
Type modify in various ways, but aspect of the invention is without being limited thereto.In the following description, will describe by way of example include
First electronic device 120 of two semiconductor grains 121 and two driven members 122.In addition, semiconductor grain 121 is with flip
Pattern is formed, and may be mounted so that the conductive bumps of semiconductor grain 121 are welded to the first line pattern of substrate 110
111.Semiconductor grain 121 may include joint liner and can be connected to the first line pattern 111 by wire bonding.However,
Connection relationship between semiconductor grain 121 and the first line pattern 111 is not limited to the connection relationship in the invention by the present invention.
Second electronic device 130 is mounted on the second surface 110b of substrate 110, is formed in substrate 110 to be electrically connected to
On the second line pattern 112.Illustrate the second electronic device 130 being made of single semiconductor grain.However, the second electronics fills
Setting 130 can be made of multiple semiconductor grains, or may further include driven member, but aspect of the invention is unlimited
In this.
First mouldings 140 can be formed on the first surface 110a of substrate 110, be mounted on substrate 110 with covering
The first electronic device 120 on first surface 110a.First mouldings 140 can be made of general molding compound resin,
Such as epoxy, but the scope of the present invention is not limited thereto.First mouldings 140 can protect the first electronic device 120
Exempt to be affected by.
Second mouldings 150 can be formed on the second surface 110b of substrate 110, be mounted on substrate 110 with covering
Second electronic device 130 on second surface 110b.Second mouldings 150 will be formed on the second surface 110b of substrate 110
The first conductive bumps 160 be externally exposed, while second electronic device 130 is completely covered.Second mouldings 150 and first pass
Pilot block 160 can have identical height.Second mouldings 150 and the first mouldings 140 can be made of identical material.
Second mouldings 150 can protect second electronic device 130 and exempt to be affected by.
First conductive bumps 160 may include be formed on the second surface 110b of substrate 110 it is multiple first conduction it is convex
Block, to be electrically connected to the second line pattern 112 being formed on substrate 110.First conductive bumps 160 are configured as its lateral parts
It is surrounded by the second mouldings 150, and a part of its bottom surface is externally exposed through the second mouldings 150.Exposed
One conductive bumps 160 are electrically connected to the second conductive bumps 170.That is, the first conductive bumps 160 are electrically connected to form in substrate
The second conductive bumps 170 and the second line pattern 112 on 110.First conductive bumps 160 may include conductive post, copper post, conduction
Ball or copper ball, but aspect of the invention is not limited to this.
Second conductive bumps 170 can be formed on the bottom surface of the second mouldings 150, penetrate the second mould to be electrically connected to
Object 150 processed is exposed to the first external conductive bumps 160.In the external device (ED) that semiconductor packages 100 is mounted on to such as mainboard
In the case where upper, the second conductive bumps 170 can be used for semiconductor packages 100 being electrically connected to external device (ED).
Other than the bottom surface of the second mouldings 150, EMI shielded layer 180 can be formed as being enough to be completely covered partly leading
The predetermined thickness of body encapsulation 100.That is, EMI shielded layer 180 is formed as covering the top surface of all semiconductor packages 100
With four side surfaces.In addition, EMI shielded layer 180 can be made of conductive material, and it may be electrically connected to semiconductor packages
100 ground wire or external ground connection.EMI shielded layer 180 can be shielded and be caused by semiconductor packages 100 (or by semiconductor packages 100
Generate) EMI.In addition, semiconductor packages 100 may include the first and second mouldings 140 and 150, to cover substrate 110
Both first and second surface 110a and 110b, to prevent the warpage of semiconductor packages 100, this may be only in substrate 110
A surface on formed mouldings when occur.
Referring to fig. 2, the flow chart of the method for illustrating to manufacture semiconductor packages shown in Fig. 1 is shown.Such as institute in Fig. 2
Show, the method (S10) of manufacture semiconductor packages 100 includes forming mouldings (S11), grinding the second mouldings (S12), forming the
Two conductive bumps (S13), placing clamp (S14) and formation EMI shielded layer (S15).
Referring to Fig. 3 A to Fig. 3 E, cutting for each step of the method for manufacturing semiconductor packages shown in Fig. 2 is shown
Face figure.
Firstly, the first electronic device 120 to be mounted on to the first surface of substrate 110 before forming mouldings (S11)
110a is upper to be electrically connected to the first line pattern 111, and second electronic device 130 is mounted on the second surface 110b of substrate 110
To be electrically connected to the second line pattern 112, and multiple first conductive bumps 160 are then formed on to the second surface of substrate 110
110b is upper to be electrically connected to the second line pattern 112.
As shown in Figure 3A, in the formation of mouldings (S11), the first mouldings 140 are formed as covering the first of substrate 110
Surface 110a and the first electronic device 120, and the second mouldings 150 are formed as covering the second surface 110b of substrate 110, the
Two electronic devices 130 and multiple first conductive bumps 160.First mouldings 140 and the second mouldings 150 can be formed simultaneously.
For example, placing mold around the substrate including the first electronic device 120, second electronic device 130 and the first conductive bumps 160
110, and moulded resin is injected into the space in mold, to be formed simultaneously the first mouldings 140 and the second mouldings 150.
Herein, the first electronic device 120, second electronic device 130, the first conductive bumps 160 and substrate 110 and mold inner surface
It is spaced apart in the state of the inner surface for not contacting mold, moulded resin is injected in mold, to form the first molded item
140 and second molded item 150.That is, the first mouldings 140 are formed as the first surface 110a that substrate 110 is completely covered
With the first electronic device 120, and the second mouldings 150 are formed as being completely covered the second surface 110b of substrate 110, the second electricity
Sub-device 130 and the first conductive bumps 160.
As shown in Figure 3B, in the grinding of the second mouldings (S12), the bottom surface of the second mouldings 150 is ground with by the
One conductive bumps 160 are exposed to the outside of the second mouldings 150.That is, in the grinding of the second mouldings 150 (S12),
The second mouldings 150 are ground so that the first conductive bumps 160 are exposed to outside.At this point, the bottom of the first conductive bumps 160 can also
By partial mill.The bottom surface of first conductive bumps 160 and the bottom surface of the second mouldings 150 can be coplanar.Separately
Outside, second electronic device 130 can be located in the second mouldings 150, and second electronic device 130 can be for example not exposed to
It is external.Such as diamond abrasive machine and its equivalent can be used to be ground, but aspect of the invention is without being limited thereto.
As shown in Figure 3 C, when forming the second conductive bumps (S13), multiple second conductive bumps 170 are formed as being electrically connected
Into the grinding in the second mouldings, (S12) is respectively exposed to external multiple first conductive bumps 160.Can be used falling sphere,
One of silk-screen printing, plating, vacuum evaporation, plating and its equivalent person forms the second conductive bumps 170, but of the invention
Aspect it is without being limited thereto.In addition, the second conductive bumps 170 can be made of metal material, such as lead/tin (Pb/Sn) or unleaded
Sn and their equivalent, but aspect of the invention is without being limited thereto.
As shown in Figure 3D, it at placing clamp (S14), loads and placing clamp 10 is with the bottom of the second mouldings 150 of covering
Surface 150b.Fixture 10 is shaped with substantially a rectangular frame and can have inner space 11, which arrives with top
Predetermined depth in bottom direction and extend outwardly the planar section 12 of predetermined length along excircle.Planar section 12 can be with
The excircle of the bottom surface 150b of two mouldings 150 is contacted and then is fixed, and is formed in the bottom surface 150b of the second mouldings 150
On the second conductive bumps 170 be inserted into inner space 11.That is, fixture 10 is put at placing clamp (S14)
It sets to cover the bottom surface 150b of the second mouldings 150, and the first mouldings 140, the side surface of substrate 110 and the second mould
The side surface of object 150 processed is externally exposed.
As shown in FIGURE 3 E, when forming EMI shielded layer (S15), the first mould exposed to the outside at placing clamp (S14)
EMI shielded layer 180 is formed in object 140 processed, the side surface of substrate 110 and the side surface of the second mouldings 150.In addition to by pressing from both sides
Except the bottom surface 150b of second mouldings 150 of 10 covering of tool, EMI shielded layer 180 is formed as that all first moulds are completely covered
Object 140, the side surface of substrate 110 and the side surface of the second mouldings 150 processed.That is, in addition to semiconductor packages 100
Bottom surface except, EMI shielded layer 180 is formed as four side surfaces that semiconductor packages 100 is completely covered and top surface.
EMI shielded layer 180 can be deposited or be sprayed through plasma-based and form predetermined thickness, but aspect of the invention is without being limited thereto.Separately
Outside, it after forming EMI shielded layer (S15), is produced in the formation of EMI shielded layer 180 made of conductive material to remove
Raw metal residue can be cleaned with further progress.In addition, after forming EMI shielded layer 180 and executing cleaning, separation
Fixture 10 positioned at 150 lower section of the second mouldings is to complete the semiconductor packages 100 with EMI shielded layer 180.Extremely referring to Fig. 3 A
Fig. 3 E manufactures single semiconductor packages 100, but can form multiple semiconductor packages on substrate 110, then by single
Change processing procedure and is divided into discrete semiconductor encapsulation 100.
Referring to fig. 4, the sectional view of semiconductor packages according to another embodiment of the present invention is shown.
As shown in figure 4, semiconductor packages 200 includes substrate 110, the first electronic device 120, second electronic device 130, the
One mouldings 140, the second mouldings 150, the first conductive bumps 160, the second conductive bumps 170 and EMI shielded layer 280.Including
Substrate 110, the first electronic device 120, second electronic device 130, the first mouldings 140, the conduction of the second mouldings 150, first
The semiconductor packages 200 of convex block 160 and the second conductive bumps 170 has structure identical with semiconductor packages 100 shown in Fig. 1
It makes.Therefore, being described below for semiconductor packages 200 will focus on EMI shielded layer 280, be and semiconductor package shown in Fig. 1
Fill 100 different features.
EMI shielded layer 280 is formed as covering top surface, four side surfaces and the bottom surface of semiconductor packages 200 to pre-
Determine thickness, and the second conductive bumps 170 can be exposed to outside.That is, other than the second conductive bumps 170,
EMI shielded layer 280 can be formed as that semiconductor packages 200 is completely covered.In addition, EMI shielded layer 280 can be by conductive material system
At and may be electrically connected to semiconductor packages 200 ground wire or external ground connection.
EMI shielded layer 280 may include multiple exposed hole 280a.Second conductive bumps 170 can be sudden and violent by exposed hole 280a
It is exposed to the outside of EMI shielded layer 280.That is, the exposed hole 280a of EMI shielded layer 280 may be positioned such that corresponding to second
Conductive bumps 170.
In addition, exposed hole 280a can have the width bigger than the diameter of the second conductive bumps 170.That is, EMI
Shielded layer 280 can by exposed hole 280a and with the second conductive bumps 170 (d) spaced a predetermined distance from, and can with by passing
It is electrically disconnected to lead the second conductive bumps 170 made of material.Herein, around the second conductive bumps 170 in the second mouldings 150
Part can be exposed to the outside of the exposed hole 280a of EMI shielded layer 280.
Other than the second conductive bumps 170 as external terminal, EMI shielded layer 280 is formed as covering semiconductor package
200 all surface is filled, thus shielding (or on it incuding) EMI as caused by semiconductor packages 200.
Semiconductor packages 200 shown in Fig. 4 includes by manufactured by semiconductor package fabrication method shown in Fig. 2.Referring to
Fig. 5 A and 5B, show by semiconductor package fabrication method shown in Fig. 2 and manufacture the side of semiconductor packages shown in Fig. 4
The sectional view of each step in method.Hereinafter, manufacture semiconductor packages 200 will be described with reference to Fig. 2, Fig. 5 A and Fig. 5 B
Method.
As shown in Fig. 2, the method (S10) of manufacture semiconductor packages 200 includes forming mouldings (S11), the second mould of grinding
Object (S12), formation the second conductive bumps (S13), placing clamp (S14) and formation EMI shielded layer (S15) processed.Herein, mouldings
Formation (S11), the second mouldings grinding (S12) and the second conductive bumps formation (S13) and Fig. 3 A to 3C shown in
Corresponding steps in the manufacturing method of semiconductor packages 100 are identical.Therefore, below to the manufacturing method of semiconductor packages 200
(S10) description will focus on the placement (S14) of fixture and the formation (S15) of EMI shielded layer, these be referring to Fig. 5 A and 5B and
The feature different from the manufacture method of semiconductor packages shown in Fig. 3 A to 3C.
As shown in Figure 5A, it at placing clamp (S14), loads and placing clamp 20 is with the bottom of the second mouldings 150 of covering
Portion.As shown in fig. 6, fixture 20 shapes with substantially rectangular frame and can have multiple grooves 21, groove 21 has from upper
The depth in the direction under.Fixture 20 may include multiple grooves 21, correspond to the second conductive bumps of semiconductor packages 200
170, and the second conductive bumps 170 can be inserted into respectively in multiple grooves 21.That is, the second conductive bumps 170 can be with
It is surrounded by fixture 20.Herein, in order to allow the second conductive bumps 170 to enter in multiple grooves 21 of fixture 20, multiple grooves 21
Preferably there is the diameter greater than the second conductive bumps 170.
In addition, fixture 20, with rectangle loop forming, the center portion thereof point is open by the hole 22 being centrally formed.That is, not phase
The central part of the bottom surface 150b of second mouldings 150 of adjacent second conductive bumps 170 (or not close to the second conductive bumps 170)
The hole 22 through fixture 20 is divided to be exposed to outside.EMI shielded layer 280 can also be formed in semiconductor package by the hole 22 of fixture 20
It fills on 200 bottom surface.
At placing clamp (S14), fixture 20 is placed on 150 lower section of the second mouldings to cover the second conductive bumps
170, and the first mouldings 140, substrate 110 and the second mouldings 150 are exposed to outside.
As shown in Figure 5 B, when forming EMI shielded layer (S15), when EMI shielded layer 280 is formed in placing clamp (S14)
In first mouldings 140 exposed to the outside, substrate 110 and the second mouldings 150.That is, forming EMI shielded layer
(S15) when, use fixture 20 as shielding, other than the second conductive bumps 170, form EMI shielded layer 280 and partly led with covering
Top surface, four side surfaces and the bottom surface of body encapsulation 200.EMI shielded layer 280 can be deposited or be sprayed through plasma-based and be formed
For predetermined thickness, but aspect of the invention is without being limited thereto.In addition, after forming EMI shielded layer (S15), in order to remove
The metal residue generated in the formation of EMI shielded layer 280 made of conductive material can be cleaned with further progress.In addition,
After forming EMI shielded layer 280 and executing cleaning, separation is located at the fixture 20 of 150 lower section of the second mouldings to complete to have
The semiconductor packages 200 of EMI shielded layer 280.In addition, once fixture 20 is separated, since EMI shielded layer 280 is not formed in
In the second conductive bumps 170 surrounded by fixture 20 and on the part of the second conductive bumps 170, so the second conduction of exposure
The exposed hole 280a of convex block 170 is arranged in EMI shielded layer 280.Then, EMI shielded layer 280 can through exposed hole 280a with
Second conductive bumps 170 are electrically disconnected, and can be with the second conductive bumps 170 (d) spaced a predetermined distance from.
Referring to Fig. 7, the method that another embodiment according to the present invention is used to manufacturing semiconductor packages shown in Fig. 4 is shown
Flow chart.As shown in fig. 7, the method (S20) of manufacture semiconductor packages 200 includes forming mouldings (S11), the second molding of grinding
Object (S12) forms EMI shielded layer (S23), forms exposed hole (S24) and form the second conductive bumps (S25).Herein, Fig. 7 institute
The formation for the mouldings (S11) shown and the grinding of the second mouldings (S12) and semiconductor packages 100 shown in Fig. 2,3A and 3B
Corresponding steps in manufacturing method are identical.
Referring to Fig. 8 A to 8C, formation EMI shielded layer (S23), formation exposed hole (S24) and formation shown in Fig. 7 are shown
The sectional view of the step of second conductive bumps (S25).Therefore, manufacture semiconductor packages will be described with reference to Fig. 7 and Fig. 8 A to 8C
200 method (S20).
As shown in Figure 8 A, when forming EMI shielded layer (S23), formed EMI shielded layer 280 be completely covered substrate 110,
First mouldings 140 and the second mouldings 150.EMI shielded layer 280, which can be deposited or be sprayed by plasma-based, forms predetermined thickness,
But aspect of the invention is without being limited thereto.
As shown in Figure 8 B, when forming exposed hole (S24), EMI shielded layer 280 can be removed partly to conduct first
Convex block 160 is exposed to outside.That is, by forming multiple exposed hole 280a in EMI shielded layer 280, the first conduction is convex
Block 160 is exposed to outside.Multiple exposed hole 280a of EMI shielded layer 280 remove EMI shielded layer 280 by etching or laser
A part and formed.Furthermore it is possible to exposed hole 280a is formed by any processing procedure known in the art to execute, as long as EMI screen
Covering material can be with desired pattern, but is not limited to etching or laser as disclosed in the present invention.As shown in Figure 8 B, often
The width (d1) of a exposed hole 280a is preferably more than the diameter (d2) of each first conductive bumps 160.In order to be described later on
The first conductive bumps 160 and the second conductive bumps 170 are electrically disconnected, exposed hole 280a is preferably formed to have sufficiently large
Width (that is, d1).In addition, can further execute the cleaning for removing metal residue after forming exposed hole 280a
Processing procedure.
As shown in Figure 8 C, when forming the second conductive bumps (S25), the second conductive bumps 170 are formed as through exposed hole
280a is electrically connected to the first conductive bumps 160 exposed to the outside.Second conductive bumps 170 are preferably formed to have than exposure
The bigger diameter (d3) of the width (d1) of hole 280a.That is, the second conductive bumps 170 can be separated with EMI shielded layer 280
Preset distance, with electrically disconnected with EMI shielded layer 280.
Fig. 9 A shows the sectional view of the semiconductor packages 900 according to one embodiment.Fig. 9 B shows partly leading for Fig. 9 A
The amplifier section of body encapsulation 900.Semiconductor packages 900 and its component can be similar to it is of the present invention any one or more
Other semiconductor packages or its correspondence component, and the characteristic of semiconductor packages 900 is described further below.
Semiconductor packages 900 includes substrate 910, and the substrate 910 has substrate top surface 911,912 and of substrate bottom surface
Substrate lateral surfaces 913 between them.Substrate 910 further includes that the substrate top first at substrate top surface 911 pads
9111 and at substrate bottom surface 912 base plate bottom first liner 9121.Substrate 910 can be similar to of the present invention
Any substrate, such as substrate 110.In identical or other embodiments, substrate 910 may include redistribution structure (RDS), tool
There are one or more dielectric layers of dielectric material and one or more conducting shells between dielectric layer and across dielectric layer.
Such conducting shell can define liner, trace and through-hole, electric signal or voltage can through the liner, trace and through-hole and
RDS is passed through to be distributed in the horizontal and vertical directions.
Semiconductor packages 900 further includes being attached to substrate top surface 911 and being coupled to the liner of substrate top first 9111
Electronic device 920.Electronic device 920 may include one or more transistors, and may include microcontroller device, penetrates
Frequently (RF) device, wireless (WiFi, WLAN etc.) switch, power amplifier apparatus, low-noise amplifier (LNA) device etc..May be used also
With the embodiment in the presence of the electronic device 920 that may include MEMS (MEMS) device, wherein MEMS device may include one
A or multiple energy converters.Electronic device 920 includes apparatus surface 921 towards substrate top surface 911, away from substrate top surface
911 apparatus surface 922 and the device lateral surface 923 between them.In the present embodiment, electronic device 920 is included in
With the semiconductor grain of convex block at apparatus surface 921, and flip is installed in substrate top surface 911, so that these convex blocks
In a contact substrate top first liner 9111.Term " convex block " may refer to spherical protrusions (such as solder projection or weldering
Expect the copper core convex block of coating) and/or may refer to metal rod convex block (such as the copper post at or without solder tip).?
In other embodiments, electronic device 920 may include semiconductor grain, non-active surface towards substrate top surface 911 and
The wire bondings padded with one or more from the one or more that its action face extends to from substrate top surface 911.May be used also
With the embodiment in the presence of the electronic device 920 that may include packaging system, wherein there is the packaging system one or more partly to lead
Body crystal grain, and optionally there is another substrate that such a or multiple semiconductor grains are coupled, wherein
Such packaging system may be coupled to one or more liners at substrate top surface 911.
In the present embodiment, semiconductor packages 900 further includes the passive structure of one or more for being coupled to substrate top surface 911
Part, such as it is coupled to the driven member 931 of the liner of substrate top second 9112.In some embodiments, such a or more
A driven member may include capacitor, inductor and/or resistor.Although in the present embodiment, driven member 931 is presented
To be coupled to surface mounting technique (SMT) device of the liner of substrate top second 9112 via SMT connector, but may exist it
His embodiment and so that driven member 931 differently can be encapsulated or is installed, such as pass through line bonding or convex block.
Several configurations of different device and component can be coupled to substrate top surface 911.For example, in addition to 920 He of electronic device
Except driven member 931, Fig. 9 shows the electronic device 9201 for being coupled to substrate 910 at substrate top surface 911, electronics dress
Set 9202 and driven member 932.Electronic device 9201 and/or electronic device 9202, which can be similar to, refers to 920 institute of electronic device
One or more of distinct device option of description.As embodiment, electronic device 920 may include microcontroller device,
And electronic device 9201 may include MEMS device, gyroscope, microphone, pressure sensor or gas sensor etc..To the greatest extent
Pipe shows electronic device 9201 and is joined to substrate top surface 910 by convex block, but can be there may be electronic device 9201
The other embodiments of wire bonding.In addition, alternatively, electronic device 9202 is shown to be coupled to substrate top surface via wire bonding
910, while storehouse is on the top of electronic device 920.Driven member 932 can be similar to driven member 931, and be shown
The substrate top surface 911 being coupled between electronic device 920 and electronic device 9201.
Encapsulant 940 is shown in Fig. 9, is encapsulated substrate top surface 911 and coupled all components, including electronics
Device 920,9201 and 9202 and driven member 931 and 932.Although covering these present embodiment illustrates encapsulant 940
The lateral surfaces and top surface of device and component, can but there may be top surfaces one or more in these devices or component
With the embodiment of exposure through encapsulant 940.
Fig. 9 also shows the electronic device for being attached to substrate bottom surface 912 and being coupled to the first pad of base plate bottom 9121
970.Electronic device 970 can be similar to one or more different device options for describing referring to electronic device 920, and including
Apparatus surface 971 towards substrate bottom surface 912, the apparatus surface 972 away from substrate bottom surface 912 and the dress between them
Set lateral surfaces 973.In the present embodiment, electronic device 970 includes the semiconductor die at apparatus surface 971 with convex block
Grain, and flip is installed on substrate bottom surface 912, so that a contact base plate bottom first in these convex blocks pads
9121.In other embodiments, electronic device 970 may include semiconductor grain, and non-active surface is towards substrate bottom surface
912, and there is the line of one or more one or more liners extended to from substrate bottom surface 912 from its action face to connect
It closes.There may also be the embodiments that electronic device 970 includes packaging system, wherein the packaging system has one inside it
A or multiple semiconductor grains, and it is optionally another with such a or multiple semiconductor grains are coupled
A substrate, wherein this packaging system may be coupled to one or more liners at substrate bottom surface 912.
Semiconductor packages 900 further includes external interconnection (such as external interconnection 980), is configured as semiconductor packages 900
External device (ED) is interfaced with or be attached to, such as is connected to external substrate or the plate part compared with giant electronics.980 coupling of outside interconnection
Base plate bottom second to substrate 910 pads 9122, and than the apparatus surface of electronic device 970 972 from substrate bottom surface 912
Further protrude.Outside interconnection 980 is shown as including the interconnection interior section 981 adjacent with substrate bottom surface 912 and setting
It is set to the interconnection remote portion 982 far from substrate bottom surface 912.Although interconnecting interior section 981 and interconnection in the present embodiment
Remote portion 982 is all rendered as the conductive ball of storehouse, but can be such as solder there may be one or both of which
Copper or metal core ball or conductive bar plating, wire bonding or other realities for being otherwise attach to substrate bottom surface 912 being encapsulated
Apply example.As another option, outside interconnection 980 can be the conducting structure of single conducting structure rather than storehouse, such as singly
A soldered ball, or single conductive bar or column.
Encapsulant 950 is shown in Fig. 9, is encapsulated substrate bottom surface 912 and coupled any component, including electronics
Device 970 and driven member 933.Although present embodiment illustrates the lateral surfaces and bottom surface of this device of covering and component
Encapsulant 950, but there may be the bottom surfaces of device as one or more or component can be protected by encapsulant 950
Hold exposed embodiment.Encapsulant 950 limits external interconnection 980, while exposes the long-range of external interconnection 980 and from encapsulant
Bottom surface 952 is prominent.In some embodiments, the material of encapsulant 950 can be similar to the one kind described for encapsulant 940
Or multiple material.For example, encapsulant 940 may include one layer of moulding material, and encapsulant 940 may include identical mold member
The layer of material, whether either application simultaneously with the layer of encapsulant 940 still with the one application of the layer of encapsulant 940.
Fig. 9 B includes enlarged view, and external 980 details relative to encapsulant 950 that interconnects is presented.In enlarged view
Finding, encapsulant 950 include straight-through perforation 955, disclose the different piece of external interconnection 980.For example, interconnection is encapsulated section
985 are attached to substrate bottom surface 912 and are defined by encapsulant 950 and contacted with encapsulant 950.Exposure section 986 is interconnected to be pressed
Enter to lead directly in perforation 955 and is defined by encapsulant 950 but separated with encapsulant 950.It interconnects prominent section 987 and is not only exposed to capsule
Object 950 is sealed, but also fartherly more prominent than encapsulant bottom surface 952.
Fig. 9 also shows electromagnetic interference (EMI) shielding 960, covers the capsule of encapsulant top surface 942 and encapsulant 940
Seal the substrate lateral surfaces 913 of object lateral surfaces 943 and substrate 910.In the present embodiment, the also covering of EMI shielding 960 is encapsulated
The encapsulant lateral surfaces 953 of object 950.And make the exposure of at least part encapsulant bottom surface 952, so that EMI shielding 960 is protected
It holds and is spaced apart with outside interconnection 980.In the present embodiment, EMI shielding 960 includes one layer of continuous conformal coating, is met respectively
Profile, be included in encapsulant top surface 942, encapsulant lateral surfaces 943, substrate lateral surfaces 913 and encapsulant transverse direction table
Any surface imperfection in face 953 or it is coarse and/or between any surface imperfection or coarse.
Semiconductor packages 900 further includes compartment shielding 990 in the present embodiment, can be EMI shielding, is configured as
EMI protection is provided in the compartment region for surrounding one or more components (such as electronic device 970).Compartment shields 990
It along the compartment transverse direction barrier 991 on the periphery definition device lateral surface 973 of electronic device 970, and further include defining device
The cell bottom barrier 992 on surface 972.
In some embodiments, compartment transverse direction barrier 991 can be multiple conductive bars, such as column or line, either be electroplated
, it is wire bonding, welding still otherwise couple, they are arranged at least one with the periphery of electronic device 970
The adjacent one or more columns per page in part.The region of the lower section of 992 cladding system surface of cell bottom barrier 972 and contact compartment transverse direction
Barrier 991.Cell bottom barrier 992 can be the conformal coating of metal plate or the conformal coating similar to EMI shielding 960.?
In some embodiments, cell bottom barrier 992 can be EMI shielding 960 conformal coating a part, but there may be every
Room bottom barrier 992 can independently of and/or sequentially form EMI shielding 960 other embodiments.Compartment transverse direction barrier 991
Conductive bar exposure at encapsulant bottom surface 952, to allow to contact with cell bottom barrier 992, and such as in the present embodiment
Seen in, it can be and project through encapsulant bottom surface 952, so that this conductive bar lateral part outstanding can be by cell bottom
The material of barrier 992 covers.
There may also be such embodiments, and wherein compartment shields 990 compartment transverse direction barrier 991 and cell bottom partition
992 may include the apparatus surface 972 and device lateral surface 973 for defining electronic device 970 single continuous sheet (such as
Metal cylinder or covering), or such as from the side of electronic device 970 to the other side and wire bonding is to substrate bottom surface 912
One or more line as wire frame.Some embodiments can also include the compartment screen that 990 screening arrangements are shielded similar to compartment
It covers, or removes electronic device 970 or device or component other than electronic device 970.
Figure 10 A to 10C shows the various initial stages of the assembly of semiconductor packages, be similar to it is described herein that
It is one or more of a little, such as semiconductor packages 900 (Fig. 9,11), semiconductor packages 1200 (Figure 12 to 13), semiconductor package
Fill 1400 (Figure 14 to 15), semiconductor packages 1600 (Figure 16 to 17) and/or semiconductor packages 1800 (Figure 18).Figure 10 A is presented
Substrate 910 before unification, the multiple portions including defining adjacent part, these parts then can single chemical conversion singly
Only encapsulation, such as unit part 1011 and unit part 1012.
In some embodiments, substrate 910 can be previously prepared and may include laminated substrate, such as printing electricity
Road plate, and can be band or panel-form.In identical or other embodiments, substrate 910 can be in the dielectric layer of its RDS
Between include sandwich layer, such as glass fibre or other rigid non-conductive materials, to increase the rigidity of structure.However, it is possible to which there are it
His embodiment, wherein substrate 910 can be building (build-up) substrate rather than previously prepared, and/or can be centreless
's.In such embodiments, the different dielectric layer of the RDS of substrate 910 and conducting shell can be by being layered each other and patterning
And it constructs, while the removable carrier supported by being located at 912 lower section of substrate bottom surface.This carrier can be including semiconductor,
The wafer or panel of glass or metal material.
The unit part 1011 of substrate 910 is including electronic device 920,9201,9202 and is coupled to substrate top surface 911
Driven member 931 and 932.Correspondingly, the unit part 1012 of substrate 910 includes electronic device 920', 9201', 9202' and coupling
Close the driven member 931' and 932' of substrate top surface 911.
Figure 10 B presents the follow-up phase of assembly, crosses over unit part 1011 wherein applying encapsulant 940 to be encapsulated in
And unit part 1012 and all devices for being coupled to substrate top surface 911 between unit part 1011 and unit part 1012
And component.Encapsulant 940 include single layer non-conductive materials, such as resin, polymer composites, the polymer with filler,
Epoxy resin, epoxy resin, epoxy acrylate, molding compound with filler (such as silica or other inorganic material)
B-stage preimpregnation film of object, silicone resin and/or resin dipping etc..In the embodiment that encapsulant 940 includes molding compounds, this
Kind material can apply through any one of several ways, such as assist mould by being compression molded, injecting molding or film
Modeling.
Figure 10 C shows the follow-up phase of assembly, and wherein component is added to substrate bottom surface 912.For example, electronics fills
Set 970 and driven member 933 be coupled to substrate bottom surface 912 at the unit part 1011 of substrate 910.Correspondingly, electronics fills
It sets 970' and driven member 933' and is coupled to substrate bottom surface 912 at the unit part 1012 of substrate 910.
Figure 11 A to 11E shows the follow-up phase of the various assemblies after Figure 10 A to 10C, and leads to semiconductor package
Fill 900 (Fig. 9).Figure 11 A shows the interconnection that the external interconnection 980 of substrate bottom surface 912 is attached at unit part 1011
Interior section 981, and be presented in the interconnection for the external interconnection 980' for being attached to substrate bottom surface 912 at unit part 1012
Portion part 981'.In some embodiments, interconnecting interior section 981 and 981' can be used that solder is fallen or ball falls processing procedure, silk
Net printing process or plating processing procedure apply.In identical or other embodiments, interior section 981 and 981' are interconnected once being attached
It can at least partly reflow.
Figure 11 A is also shown across unit part 1011 and unit part 1012 and in unit part 1011 and unit part
Apply encapsulant 950 between 1012, to be encapsulated substrate bottom surface 912 and coupled all components, including electronic device 970
With 970', driven member 933 and 933' and the internal 981 and 981' of interconnection.In the present embodiment, apply encapsulant 950 to make
Encapsulant bottom surface 952 is encapsulated interconnection interior section 981, electronic device 970 and driven member 933 completely, but may exist
Apply encapsulant 950 and the embodiment of the bottom-exposed that one or more of keeps these components.
Figure 11 A further illustrates compartment and shields 990 and 990', they are shielded at unit part 1011 and 1012 respectively
Electronic device 970 and 970'.In some embodiments, compartment transverse direction barrier 991 and 991' can be attached to and corresponding electronics
It the adjacent substrate bottom surface 912 in the periphery of device and is at least partly encapsulated by encapsulant 950.992 He of cell bottom barrier
992' can be applied in encapsulant 950, to be attached respectively to compartment transverse direction barrier 991 and 991'.
The follow-up phase of assembly is presented in Figure 11 B, interconnects inside portion wherein removing the corresponding portion of encapsulant 950 with exposure
Divide 981 and 981'.This removal of encapsulant 950 can correspond to straight-through perforation 955, so that defining interconnection is encapsulated section 985
With the corresponding portion for interconnecting exposure section 986.In some embodiments, can by laser ablation, by mechanical ablation and/or
Straight-through perforation 955 is formed in encapsulant 950 and etching through the material of encapsulant 950.
The follow-up phase of assembly is presented in Figure 11 C, wherein interconnection remote portion 982, which is coupled to, is exposed to straight-through perforation 955
In interconnection interior section 981 so that interconnection remote portion 982 it is fartherly more prominent than encapsulant bottom surface 952.In some implementations
In example, interconnection remote portion 982 can be used that solder is fallen or ball falls processing procedure, silk-screen printing processing procedure or plating processing procedure to apply.
In identical or other embodiments, interconnection remote portion 982 is once attached can at least partly reflow.
The follow-up phase of assembly is presented in Figure 11 D, wherein main band 1190 is attached.Main band 1190 includes across Qi Ding
The main adhesive agent on surface, so that main band part 1191 is attached on 1011 lower section of unit part, and main band part 1192
It is attached on 1012 lower section of unit part.Therefore, main adhesive agent is sealed to encapsulant bottom surface 952 and external interconnection 980,
In in the present embodiment, interconnection remote portion 982 be projected into the thickness of main band 1190 and/or by the thickness of main band 1190
It is encapsulated.Main band 1190 can also include the base for carrying main adhesive agent.
After being attached main band 1190, along dotted line unification shown in Figure 11 D, by encapsulant 940, substrate is passed through
910 and pass through main band 1190, unit part 1011 and 1012 can be separated from each other.Unification is defined in encapsulant bottom table
The encapsulant periphery edge 954 of the unit part 1011 in face 952 and the joint of encapsulant lateral surfaces 953.Main band part
1191 remain attached to unit part 1011 after unification, and main adhesive agent is still hermetically sealed to encapsulant bottom surface
952 bottom and encapsulant periphery edge 954.Similarly, after unification, main band part 1192 remains attached to unit
Part 1012, main adhesive agent are still hermetically sealed to bottom and the encapsulant periphery edge of encapsulant bottom surface 952
954'。
The follow-up phase of assembly is presented in Figure 11 E, and wherein unit part 1011 and 1012 is attached to time of secondary band 1195
Want adhesive agent.Secondary band 1195 can be supported by carrier structure, and unit part 1011 and 1012 is together with corresponding main band
Part 1191 and 1192 can pick up and place adjacent to each other on secondary band 1195, so that each main band part 1191
Bottom with 1192 is sealed relative to the secondary adhesive agent of secondary band 1195.Secondary band 1195 is exposed to the main band part of separation
1191 and 1192 and separative unit part 1011 and 1012 gap location.Secondary band 1195 can also be secondary including carrying thereon
Want the base of adhesive agent.In some embodiments, the base of main band 1190 or secondary band 1195 may include poly terephthalic acid
Glycol ester and/or polyimide material.
In the case where picking up and placement operation is completed, apply EMI shielded layer 1160.In the present embodiment, EMI shielded layer
1160 be applied to it is continuous coated comprising EMI shielding 960, EMI shielding 960' and remaining EMI shielding 1163.EMI shielding 960
Capping unit part 1011, including encapsulant top surface 942, encapsulant lateral surfaces 943, substrate lateral surfaces 913 and be encapsulated
Object lateral surfaces 953.The corresponding assembly of EMI shielding 960' capping unit part 1012.The 1163 main band of covering of remaining EMI shielding
The part of the side wall of part 1191, the side wall of main band part 1192 and secondary band 1195.In the present embodiment, secondary band 1195
By 1163 covering of remaining EMI shielding, no matter secondary band 1195 is exposed in main 1191 or 1192 where of band part comprising is inciting somebody to action
On the gap that main band part 1191 and 1192 point is opened.
Because the side wall and encapsulant lateral surfaces 953 of main band part 1191 are coplanar, EMI shielded layer 1160 is not
It is bent at encapsulant periphery edge 954, but from encapsulant lateral surfaces 953 to the substantially straight of the side wall of main band
Continue in plane.If there is no this interface typically occurred between main band 1190 and encapsulant lateral surfaces 953 to change
Bending when for right angle, so adjacent encapsulant periphery edge 954 will not be accumulated or be protruded to EMI shielded layer 1160.Therefore,
The thickness of EMI shielded layer 1160 is situated between at encapsulant periphery edge 954 and across with the main adhesive agent of main band part 1191
It meets place and keeps substantially constant.
In some embodiments, EMI shielded layer 1160 (including EMI shielding 960, EMI shielding 960' and remaining EMI shielding
1163) may include one or more conductive material layers or alloy, for example, copper (Cu), nickel (Ni), golden (Au), silver-colored (Ag), platinum (Pt),
Cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re) or graphite.In some realities
It applies in example, EMI shielded layer 1160 may include cement to allow internal metallic particles to be bonded to each other and be joined to encapsulant
140, substrate 910 and/or encapsulant 150.In other embodiments, EMI shielded layer 1160 may include doped with metal or gold
Belong to the conducting polymer of oxide, such as polyacetylene, polyaniline, polypyrrole, polythiophene or poly sulfur nitride.In other embodiments
In, EMI shielded layer 1160 may include the conductive ink prepared by mixed conducting material (such as carbon black, graphite or silver).It is formed
The exemplary process of EMI shielded layer 1160 may include using spin coating, spraying, electrolysis plating, electroless-plating or sputtering.EMI shielding
The thickness of layer 1160 can be in about 3 microns (μm) to about 7 microns of range.
Using EMI shielded layer 1160 as depicted in fig. 11E, unit part 1011 can be pulled out from main band part 1191,
Expose encapsulant bottom surface 952 and interconnection remote portion 982, and makes EMI shielding 960 along the generation (figure of semiconductor packages 900
9).During this removal, main band part 1191 remains attached to secondary band 1195, and EMI shielded layer 1160 along its with
The interface of the main adhesive agent of main band part 1191 accurately ruptures, thus by EMI shielding 960 and remaining EMI shielding 1163
It separates.Unit part 1012 can be pulled out similarly from main band part 1192, so that remaining EMI shielding 1163 remains connected to
Main band part 1191 and 1192, and it is connected to secondary band 1195.
The tack strength for being sealed to the secondary adhesive agent of the secondary band 1195 of the base portion of main band part 1191 can be greater than
It is sealed to the bonding strength of the main adhesive agent of the main band part 1191 of unit part 1011.Therefore, secondary adhesive agent can be with
Prevent main band part 1191 from separating with secondary band 1195.This can permit along encapsulant lateral surfaces 953 and main band portion
The EMI screen for dividing the interface between 1191 main adhesive agent to pass through substantially constant thickness on entire encapsulant periphery edge 954
It covers layer 1160 and carries out controlled rupture, to define EMI shielding 960.This constant thickness and the controlled rupture of EMI shielding can permit
Perhaps the increase of encapsulant lateral surfaces 953 and consistent covering, so that vertically being measured from encapsulant bottom surface 952 and along capsule
Exposure height of the envelope object lateral surfaces 953 no more than 0 to 50 μm is from 960 exposure of EMI shielding.This avoids such as EMI screens
The problem of rupture of layer 1160 leaves the overhang of EMI shielding 960 by encapsulant periphery edge 954 is covered, and is also avoided
EMI shielded layer 1160 excessively ruptures above encapsulant periphery edge 954 and leaves from EMI and shield being encapsulated for 960 over-exposures
The problem of object lateral surfaces 953.
Figure 12 A shows the sectional view of the semiconductor packages 1200 according to one embodiment.Figure 12 B shows Figure 12 A's
The amplifier section of semiconductor packages 1200.Semiconductor packages 1200 and its component can be similar to it is as described herein any one or
Other multiple semiconductor packages or its correspondence component, and the characteristic of semiconductor packages 1200 is described further below.For example, half
Conductor encapsulation 1200 can be related to above-mentioned semiconductor packages 900 comprising substrate 910,920,9201,9202 and of electronic device
970, driven member 931,932 and 933 and encapsulant 940 and each corresponding portion and component, and be described above
Other character pairs or component about semiconductor packages 900.It may include these components there may be semiconductor packages 1200
Various combination.
Semiconductor packages 1200 further includes the external interconnection 1280 with interconnection internal 1281 and interconnection remote portion 1282,
It can accordingly be similar to said external interconnection 980, interconnection interior section 981 and interconnection remote portion 982.In addition, partly leading
Body encapsulation 1200 includes encapsulant 1250, wherein the encapsulant 1250 can be similar to encapsulant 950 and its corresponding above-mentioned
Component and part.
Encapsulant 1250 is shown in Figure 12, is encapsulated substrate bottom surface 912 and coupled any component, including electricity
Sub-device 970 and driven member 933.Although present embodiment illustrates the lateral surfaces and bottom surface that cover this device and component
Encapsulant 1250, but there may be one or more bottom surfaces of such device or component can be by encapsulant
1250 keep the embodiment of exposure.In addition, encapsulant 1250 defines external interconnection 1280, while making the long-range of external interconnection 1280
Exposure is simultaneously prominent from encapsulant bottom surface 1252.
Figure 12 B includes enlarged view, and external 1280 details relative to encapsulant 1250 that interconnects is presented.In the present embodiment
In, encapsulant bottom surface 1252 and the bottom of interconnection interior section 1281 are coplanar, and interconnect the top of remote portion 1282
Periphery leans against the part of encapsulant bottom surface 1252, wherein the encapsulant bottom surface 1252 defines interconnection internal 1281
Bottom.
Figure 12 also shows electromagnetic interference (EMI) shielding 1260, is similar to above-mentioned EMI shielding 960.EMI shielding 1260
Cover the encapsulant top surface 942 of encapsulant 940 and the substrate lateral surfaces of encapsulant lateral surfaces 943 and substrate 910
913.In the present embodiment, EMI shielding 1260 also covers the encapsulant lateral surfaces 1253 of encapsulant 1250, and leaves at least
A part of exposure of encapsulant bottom surface 1252, so that EMI shielding 1260 keeps being spaced apart with outside interconnection 1280.
In the present embodiment, semiconductor packages 1200 further includes having compartment transverse direction barrier 991 and compartment as described above
The compartment shielding 990 of bottom barrier 992, can be EMI shielding, be configured to comprising one or more components (such as electronics
Device 970) compartment region in provide EMI protection.
Semiconductor packages 1200 can be assembled by each stage of assembly, including be assembled shown in Figure 10 A to 10C
The initial stage of part.Figure 13 A to 13E shows the stage of the various subsequent assemblies after Figure 10 A to 10C, and leads to half
Conductor encapsulates 1200 (Figure 12).
The stage of the assembly of Figure 13 A description is similar to the stage of the assembly of Figure 11 A, but is for semiconductor packages
1200 (Figure 12).1281 are attached to the substrate bottom surface 912 at unit part 1011 inside the interconnection of outside interconnection 1280,
And interconnect the substrate bottom surface 912 that inside 1281 ' is attached at unit part 1012.Figure 13 A also occurs encapsulant
1250, the encapsulant 1250 is applied across and between unit part 1011 and unit part 1012 to be encapsulated substrate base
Surface 912 and all components for being couple to substrate bottom surface 912 include electronic device 970 and 970 ', 933 and of driven member
933 ' and interconnection internal 1281 and 1281 '.In the present embodiment, encapsulant 1250 is used to be encapsulated interconnection inside completely
1281, electronic device 970 and driven member 933, but it is also possible that other situations, e.g. encapsulant 1250 can be used to
The one or more bottoms for leaving these components are exposed.Figure 13 A is further presented compartment side walls 991 and 991 ', it is described every
Room side wall 991 and 991 ' is attached to adjacent to the substrate bottom surface 912 around respective electronic device 970 and 970 ' and at least
Object 1250 is partly encapsulated to be encapsulated.
The stage of the assembly of Figure 13 B description is similar to the stage of the assembly of Figure 11 B, but is for semiconductor packages
1200 (Figure 12).Encapsulant 1250 is partly removed or thinning is with the bottom of exposure interconnection internal 1281 and 1281 '.Thinning
Or planarization process reduces interconnection exposure section 1286 He of the thickness until interconnection internal 1281 and 1281 ' of encapsulant 1250
1286 ' expose, and in this embodiment, the interconnection exposure section 1286 and 1286 ' exposes simultaneously from encapsulant bottom surface 1252
And it is coplanar with encapsulant bottom surface 1252.In some embodiments, it is described planarization may relate to mechanical polishing process and/or
One or more etch phases.In the present embodiment, the bottom of compartment side walls 991 and 991 ' is also exposed in the planarization.Compartment
Bottom barrier 992 and 992 ' can be applied after this planarization process, and the cell bottom barrier 992 and 992 ' individually covers
The region covered below electronic device 970 and 970 ' and the bottom that individually contact compartment side walls 991 and 991 ' are exposed.
The follow-up phase of assembly is presented in Figure 13 C, is similar to the follow-up phase of the assembly of Figure 11 C, but is to be used for
Semiconductor packages 1200 (Figure 12).Part interconnection remote portion 1282 and 1282 ' is coupled to the planarization process institute by Figure 13 B
1281 and 1281 ' inside exposed interconnection, and it is therefore more prominent compared with encapsulant bottom surface 1252.In certain embodiments,
Part interconnection remote portion 1282 and 1282 ' falls (solder drop) using solder or ball falls (ball drop) system
Journey, screen printing processing or electroplating process and be applied.In identical or other embodiments, part interconnects remote portion
1282 and 1282 ' is once attached, can at least partly reflow.
The follow-up phase of assembly is presented in Figure 13 D, is similar to the follow-up phase of the assembly of Figure 11 D, but it is to use
In semiconductor packages 1200 (Figure 12).Main band 1190 includes the main adhesive agent across its top surface, so that main band part
1191 by gluing to 1011 lower section of unit part and main band part 1192 is by gluing to 1012 lower section of unit part.Therefore,
The main adhesive agent is to be sealed to encapsulant bottom surface 1252 and interconnect 1280 to external, wherein the part of the present embodiment
Interconnection remote portion 1282 is projected into the thickness of main band 1190 and/or is encapsulated by the thickness of main band 1190.
After the attachment of main band 1190, encapsulant 940 is passed through along dotted line unification shown in Figure 13 D, is passed through
Substrate 910 and pass through main band 1190, can be separated from one another by unit part 1011 and unit part 1012.Unification is defined
The encapsulant surrounding edge 1254 of unit part 1011, in connecing for encapsulant bottom surface 1252 and encapsulant lateral surfaces 1253
At conjunction.After unification, unit part 1011, the master of the main band part 1191 is still attached in main band part 1191
It wants adhesive agent to be still hermetically sealed to the bottom of encapsulant bottom surface 1252 and is sealed to encapsulant surrounding edge 1254.
The follow-up phase of assembly is presented in Figure 13 E, is similar to the follow-up phase of the assembly of Figure 11 E, but is to be used for
Semiconductor packages 1200 (Figure 12).Unit part 1011 and unit part 1012 are attached to secondary the secondary of band 1195 and stick together
Agent.Secondary band 1195 can be supported by carrier structure, and unit part 1011 and unit part 1012 are together with corresponding main
Band part 1191 and 1192 can be picked and place adjacent to each other on secondary band 1195, so that each main band part 1191
Bottom with 1192 is sealed to the secondary adhesive agent of secondary band 1195.Secondary band 1195 is exposed to a gap, described
Gap separates main band part 1191 and 1192 and unit part 1011 and unit part 1012 is separated from one another.
When the pickup and placement operation are completed, EMI shielded layer 1160 is applied.In the present embodiment, EMI shielded layer
1160 are applied as continuous coating, and it includes EMI shielding 1260, EMI to shield 1260 ' and remaining EMI shielding 1163.
EMI shields 1260 capping unit parts 1011, includes encapsulant top surface 942, encapsulant lateral surfaces 943, substrate transverse direction table
Face 913 and encapsulant lateral surfaces 1253.EMI shields the correspondence component of 1260 ' capping unit parts 1012.Remaining EMI screen
Cover the side wall of the main band part 1191 of 1163 coverings, the side wall of main band part 1192 and secondary band 1195.In the present embodiment
In, secondary band 1195 is covered by the place that main band part 1191 or 1192 is exposed by remaining EMI shielding 1163, comprising covering
It covers on the gap for separating main band part 1191 with main band part 1192.
The advantages of such configuration provides is similar to the description above in connection with Figure 11 E, so that the thickness of EMI shielded layer 1160
Degree does not swell, but connects described in the main adhesive agent at encapsulant surrounding edge 1254 and across main band part 1191
It is kept at mouthful substantially constant.
EMI shielded layer 1160 is applied with as shown in Figure 13 E, unit part 1011 can be from main 1191 quilt of band part
It pulls out, leaves encapsulant bottom surface 1252 and part interconnection remote portion 1282, and generate half together with EMI shielding 1260
Conductor encapsulates 1200 (Figure 12).During this removal, main band part 1191 remains attached to secondary band 1195, and
EMI shielded layer 1160 is accurately ruptured along the interface of itself and the main adhesive agent of main band part 1191, so that EMI be shielded
1260 separate with remaining EMI shielding 1163.Unit part 1012 can be pulled out similarly from main band part 1192, so that remaining
EMI shielding 1163 remains attached to main band part 1191 and 1192, and is attached to secondary band 1195.
The characteristic of main band 1190 and secondary band 1195 is kept as above for shown in Figure 11 E, to realize EMI shielded layer
1160 constant thickness and controlled rupture, to allow the increase of encapsulant lateral surfaces 1253 and consistent covering.Therefore, from
Encapsulant bottom surface 1252 and along be no more than measured by encapsulant lateral surfaces 1,253 0 to 50 μm of exposure height be from
1260 exposure of EMI shielding.This is avoided the rupture of EMI shielded layer 1160 by encapsulant surrounding edge 1254, leaves EMI shielding 1260
Overhang the problem of, and EMI shielded layer 1160 is also avoided excessively to rupture, leave above encapsulant surrounding edge 1254
The problem of encapsulant lateral surfaces 1253 shield 1260 by over-exposure from EMI.
Figure 14 A shows the sectional view of the semiconductor packages 1400 according to one embodiment.Figure 14 B is illustrated from Figure 14 A's
The amplifier section of semiconductor packages 1400.Semiconductor packages 1400 and its component can be similar to it is described in the present invention other
The corresponding component of any one or more or they of semiconductor packages, and the characteristic of semiconductor packages 1400 will be into one
Step explanation is below.For example, semiconductor packages 1400 can be relevant to semiconductor packages 900 described above,
Comprising substrate 910, electronic device 920,9201,9202 and 970, driven member 931,932 and 933 and encapsulant 940, and it is every
A corresponding portion and component, and other character pairs or component about semiconductor packages 900 are described above.It can be with
There is embodiment, wherein semiconductor packages 1400 may include the various combination of these components.
Semiconductor packages 1400 also may include external interconnection 1480, and the external interconnection 1480 is similar to external interconnection
980 (Fig. 9,11).However, the external interconnection 1480 of the present embodiment is shown as single convex block rather than matching with dual stack convex block
It sets.Or it may include different configurations, such as dual stack convex block that can to have embodiment, which be external interconnection 1480,.
Semiconductor packages 1400 also include encapsulant 1450, the encapsulant 1450 can be similar to encapsulant 950 (Fig. 9,
11) and it is described above in its individual elements and part.The encapsulant 1450 being shown in Figure 14 is encapsulated substrate base table
Face 912 and any component for being couple to the substrate bottom surface 912 include electronic device 970 and driven member 933.Although
The present embodiment shows that encapsulant 1450 covers the lateral surfaces and bottom surface of this device and component simultaneously, can also have embodiment to be
The bottom surface of one or more of this device and component can be left to be exposed by encapsulant 1450.Furthermore encapsulant 1450
It surrounds outside interconnection 1480 while the end for leaving outside interconnection 1480 is exposed and protrudes from encapsulant bottom surface 1452.
Figure 14 includes an enlarged drawing, and the details that external interconnection 1480 is relevant to encapsulant 1450 is presented.In the present embodiment
In, encapsulant 1450 covers the major part of external interconnection 1480, so that encapsulant bottom surface 1452 extends from substrate bottom surface 912
Pass through the maximum width 1489 of external interconnection 1480.In other examples, encapsulant 1450 can cover external interconnection 1480
Small part, begin encapsulant bottom surface extends from substrate bottom surface 912, but the maximum width without reaching external interconnection 1480
Degree 1489.The protrusion that skirt 1459 is encapsulant bottom surface 1452 is also presented in encapsulant 1450, surrounds external interconnection 1480
The exposure end.
Figure 14 further displays electromagnetic interference (EMI) shielding 1460, and the EMI shielding 1460 is similar to as above retouched
The EMI shielding 960 stated.EMI shielding 1460 covering encapsulant 940 encapsulant top surface 942 and encapsulant lateral surfaces 943 with
And the substrate lateral surfaces 913 of substrate 910.In the present embodiment, EMI shielding 1460 also covers the encapsulant cross of encapsulant 1450
To surface 1453, and at least part for leaving encapsulant bottom surface 1452 is exposed so that EMI shielding 1460 keep with it is outer
Portion's interconnection 1480 is spaced apart.
In the present embodiment, semiconductor packages 1400 also comprising with compartment side walls 991 and cell bottom barrier 992 every
Room shielding 990, the EMI shielding that the compartment shielding 990 can be as described above, through construction to surround one or more
EMI protection is provided in the compartment region of a component, one or more of components are, for example, electronic device 970.
Semiconductor packages 1400 can be assembled by the various stages of assembly, comprising as at the beginning of the assembly of Figure 10 A to 10C
Stage beginning.Figure 15 A to 15D diagram is connected in the various back segment stages of the assembly of Figure 10 A to 10C and ultimately forms semiconductor
Encapsulate 1400 (Figure 14).
Back segment stage of Figure 15 A description for the assembly of semiconductor packages 1400 (Figure 14).Compartment side walls 991 and 991 '
Substrate bottom surface 912 is attached to adjacent to respective electronic device 970 and 970 '.Outside interconnection 1480 is also attached, it includes
Remote portion 1482 is interconnected closest to the interconnection inside 1481 of substrate 910 and the part far from substrate 910.Film 1590 is applied
Add or pause at the lower section of substrate bottom surface 912, covering part interconnection remote portion 1482, leave interconnection internal 1481 and be not coated
Lid, and the gap 1550 being defined between film 1590 and substrate bottom surface 912.In certain embodiments, thin when being applied with
When film 1590, film 1590 also contacts the apparatus surface 972 of electronic device 970.In certain embodiments, film 1590 may include
It is constructed into the layer or film for being able to carry out film assisted molding.
Follow-up phase of Figure 15 B description for the assembly of semiconductor packages 1400 (Figure 14).In film assisted molding system
Cheng Zhong, encapsulant 1450 are applied to fill the gap 1550 between film 1590 and substrate bottom surface 912.Encapsulant 1450 is prolonged
Stretch across and between unit part 1011 and unit part 1012 to be encapsulated substrate bottom surface 912 and coupled with it all groups
Part comprising electronic device 970 and 970 ', driven member 933 and 933 ' and interconnection internal 1481 and 1481 ', but leaves prominent
Part out interconnects remote portion 1482 and 1482 '.Therefore, it is measured when from substrate bottom surface 912, the maximum of encapsulant 1450 is thick
Degree is kept to less than the height of interconnection 1480.In the present embodiment, encapsulant 1450 is applied to be fully encapsulated electronics
Device 970 and driven member 933, but can also have embodiment be encapsulant 1450 can be applied and leave it is one or more this
The bottom of component is exposed.For example, film 1590 contact electronic device 970 embodiment in, apparatus surface 972 be left and
From the exposure of encapsulant 1450.Figure 15 B further present compartment side walls 991 and 991 ' be attached to substrate bottom surface 912 and by
Encapsulant 1450 is encapsulated.
Figure 15 C describes the follow-up phase of assembly, is similar to the follow-up phase of Figure 11 D, but is for semiconductor package
Fill 1400 (Figure 14).Film 1590 is removed, and cell bottom barrier 992 and 992 ' can be applied to be individually covered on electricity
Region below sub-device 970 and 970 ' and the end that individually contact compartment side walls 991 and 991 ' are exposed.Main band 1190
Be shown as being attached, answered using the encapsulant bottom surface 1452 that the main adhesive agent of main band 1190 is sealed to encapsulant 1450 and
Sealing to part interconnects remote portion 1482 and 1482 '.Main band 1190 includes main band part 1191, by gluing to unit
The lower section of part 1011, and main band part 1192 is by gluing to the lower section of unit part 1012.Therefore, described mainly to stick together
Agent is sealed to encapsulant bottom surface 1452 and is sealed to external interconnection 1480, in the present embodiment, partially interconnects long-range portion
1482 are divided to be projected into the thickness of main band 1190 and/or be encapsulated by the thickness of main band 1190.
After the attachment of main band 1190, encapsulant 940 is passed through along dotted line unification shown in Figure 15 C, is passed through
Substrate 910 and pass through main band 1190, can be separated from one another by unit part 1011 and unit part 1012.Unification circle
The encapsulant surrounding edge 1454 for determining unit part 1011, in encapsulant bottom surface 1452 and encapsulant lateral surfaces 1453
Joint.After unification, unit part 1011 is still attached in main band part 1191, the main band part 1191
Main adhesive agent is still hermetically sealed to the bottom of encapsulant bottom surface 1452 and is sealed to encapsulant surrounding edge 1454.
Although it is to be different from film 1590 that main band 1190, which is presented, in Figure 15 C, there can also be embodiment to be, film 1590 can wrap
Containing main band 1190 or identical as main band 1190.In such embodiments, film 1590 be not required to it is to be removed and with
Main band 1190 is replaced, because the two is identical.
Figure 15 D describes the follow-up phase of assembly, is similar to the follow-up phase of Figure 11 E, but it is for semiconductor
Encapsulate 1400 (Figure 14).Unit part 1011 and unit part 1012 are attached to the secondary adhesive agent of secondary band 1195.It is secondary
Band 1195 can be supported by carrier structure, and unit part 1011 and unit part 1012 and corresponding main band part
1191 and 1192 can be picked and place adjacent to each other on secondary band 1195, so that each main band part 1191 and 1192
Bottom be sealed to the secondary adhesive agent of secondary band 1195.Secondary band 1195 is exposed to a gap, the gap point
Every main band part 1191 and 1192 and by unit part 1011 and unit part 1012 it is separated from one another.
When the pickup and placement operation are completed, EMI shielded layer 1160 is applied.In the present embodiment, EMI shielded layer
1160 are applied as continuous coating, and it includes EMI shielding 1460, EMI to shield 1460 ' and remaining EMI shielding 1163.
EMI shields 1460 capping unit parts 1011, includes encapsulant top surface 942, encapsulant lateral surfaces 943, substrate transverse direction table
Face 913 and encapsulant lateral surfaces 1453.EMI shields the correspondence component of 1460 ' capping unit parts 1012.Remaining EMI screen
Cover the side wall of the main band part 1191 of 1163 coverings, the side wall of main band part 1192 and secondary band 1195.In the present embodiment
In, secondary band 1195 is covered by the place that main band part 1191 or 1192 is exposed by remaining EMI shielding 1163, comprising covering
It covers on the gap for separating main band part 1191 with main band part 1192.
The advantages of such configuration provides is similar to the description above in connection with Figure 11 E, so that the thickness of EMI shielded layer 1160
Degree does not swell, but connects described in the main adhesive agent at encapsulant surrounding edge 1454 and across main band part 1191
It is kept at mouthful substantially constant.
EMI shielded layer 1160 is applied with as shown in Figure 15 D, unit part 1011 can be from main 1191 quilt of band part
It pulls out, leaves encapsulant bottom surface 1452 and part interconnection remote portion 1482, and generate half together with EMI shielding 1460
Conductor encapsulates 1400 (Figure 14).During this removal, main band part 1191 remains attached to secondary band 1195, and
EMI shielded layer 1160 is accurately ruptured along the interface of itself and the main adhesive agent of main band part 1191, so that EMI be shielded
1460 separate with remaining EMI shielding 1163.Unit part 1012 can be pulled out similarly from main band part 1192, so that remaining
EMI shielding 1163 remains attached to main band part 1191 and 1192, and is attached to secondary band 1195.
The characteristic of main band 1190 and secondary band 1195 is kept as above for shown in Figure 11 E, to realize EMI shielded layer
1160 constant thickness and controlled rupture, to allow the increase of encapsulant lateral surfaces 1453 and consistent covering.Therefore, from
Encapsulant bottom surface 1452 and along be no more than measured by encapsulant lateral surfaces 1,453 0 to 50 μm of exposure height be from
1460 exposure of EMI shielding.This is avoided the rupture of EMI shielded layer 1160 by encapsulant surrounding edge 1454, leaves EMI shielding 1460
Overhang the problem of, and EMI shielded layer 1160 is also avoided excessively to rupture, leave above encapsulant surrounding edge 1454
The problem of encapsulant lateral surfaces 1453 shield 1460 by over-exposure from EMI.
Figure 16 icon is according to the sectional view of the semiconductor packages 1600 of one embodiment.Semiconductor packages 1600 and its group
Part can be similar to the corresponding component of any one or more or they of other semiconductor packages described herein, and
And the characteristic of semiconductor packages 1600 will be further illustrated below.For example, semiconductor packages 1600 can be relevant to
Semiconductor packages 900 described in text, it includes substrates 910, electronic device 920,9201,9202 and 970, driven member
931,932 and 933 and encapsulant 940 and each corresponding portion and component, and be described above about semiconductor package
Fill 900 other character pairs or component.There can be embodiment, wherein semiconductor packages 1600 may include the difference of these components
Combination.
Semiconductor packages 1600 also may include external interconnection 1480, the content as described in above in connection with Figure 14 to 15.Though
So external interconnection 1480 is shown as single convex block, and can also have embodiment is comprising different configurations, such as dual stack convex block.
Semiconductor packages 1600 also may include encapsulant 1650, and in the present embodiment, the encapsulant 1650 is in terms of certain
It is similar to encapsulant 950 described above (Fig. 9,11) and its individual elements and part.However, the present embodiment is encapsulated
Object 1650 the difference is that, the institute being encapsulated between substrate bottom surface 912 and the apparatus surface 971 of electronic device 970
The convex block of gap and electronic device 970 is stated, and is separated with outside interconnection 1480.In the present embodiment, encapsulant
1650 with going back extension along device lateral surface 973, and can have embodiment is that encapsulant 1650 can further completely
The apparatus surface 972 of ground cladding system lateral surfaces 973 and/or electronic device 970.
Encapsulant 1650 may include one or more materials, such as epoxy resin, thermoplastic material, can be thermally cured material, is poly-
Sub- amide (polyimide), polyurethane (polyurethane), polymer material and/or it is relevant to encapsulant 950 above
Described one or more materials.In some embodiments, encapsulant 1650 is referred to alternatively as underfill, such as capillary bottom
(capillary underfill) is filled in portion, and flowing is due to capillary phenomenon；Or molded underfill (molded
It underfill), is to inject in molding process or otherwise apply.There can also be other embodiment, wherein being encapsulated
Object 1650, which can be, to be previously applied underfill (pre-applied underfill), such as non-conductive cream (NCP) or non-conductive
Film (NCF) can be applied (for example, printing, spraying, gluing) before coupling electronic device 970.
Figure 16 further displays electromagnetic interference (EMI) shielding 1660, and the EMI shielding 1660 is similar to as above retouched
The EMI shielding 960 stated.EMI shielding 1660 covering encapsulant 940 encapsulant top surface 942 and encapsulant lateral surfaces 943 with
And the substrate lateral surfaces 913 of substrate 910.
In the present embodiment, semiconductor packages 1600 is similar in described above also comprising compartment shielding 1690
Compartment shielding 990 can be EMI shielding and be protected through construction with providing EMI in the compartment region around one or more components
Shield, one or more of components are, for example, electronic device 970.Compartment shielding 1690 is by compartment side walls 1691 and cell bottom
Barrier 1692 is defined, and in the present embodiment, compartment shielding 1690 includes one block of continuous material, surrounds apparatus surface 972
With 973 the two of apparatus surface of electronic device 970.In certain embodiments, compartment shielding 1690 may include metal can or cover
Lid.In other embodiments, for example, encapsulant 1650 fully the device lateral surface 973 of overlay electronic device 970 and dress
Surface 972 is set, compartment shielding 1690 can be one or more conducting wires, from the side of electronic device 970 to not ipsilateral conduct
Conducting wire cage and be wired conjunction to substrate bottom surface 912.However, it is possible to which wherein compartment shielding 1690 can there are such embodiment
With similar compartment shielding 990, there are different or discontinuous material compartment side walls 991 and cell bottom barrier 992.
Semiconductor packages 1600 can be assembled by the various stages of assembly, comprising as at the beginning of the assembly of Figure 10 A to 10C
Stage beginning.Figure 17 A to 17C diagram is connected in the various back segment stages of the assembly of Figure 10 A to 10C and ultimately forms semiconductor
Encapsulate 1600 (Figure 16).
Back segment stage of Figure 17 A description for the assembly of semiconductor packages 1600 (Figure 16).Outside interconnection 1480 is by coupling
It connects and includes to interconnect remote portion 1482 close to inside the interconnection of substrate 910 1481 and the part far from substrate 910.Compartment
Shielding 1690 is also shown coupled to substrate bottom surface 912 around electronic device 970, but can have embodiment is compartment shielding
1690 can be attached in the stage later, if desired.
Figure 17 B describes the follow-up phase of assembly, is similar to the stage of Figure 11 D, but is for semiconductor packages
1600 (Figure 16).Main band 1190 is shown as being attached, and is sealed to substrate 910 using the main adhesive agent of main band 1190
Substrate bottom surface 912, and it is sealed to external interconnection 1480.Main band 1190 includes to get adhered below unit part 1011
Main band part 1191 and the main band part 1192 to get adhered below unit part 1012.Outside interconnection 1480 and electronics
Device 970 is projected into main band 1190, so that being both fully imbedded among the main adhesive agent of main band 1190.
After the attachment of main band 1190, encapsulant 940 is passed through along dotted line unification shown in Figure 17 B, is passed through
Substrate 910 and pass through main band 1190, can be separated from one another by unit part 1011 and unit part 1012.Unification is defined
The encapsulant surrounding edge 914 of unit part 1011, in the joint of substrate bottom surface 912 and substrate lateral surfaces 913.?
After unification, unit part 1011 is still attached in main band part 1191, and the main band part 1191 is mainly sticked together
Agent is still hermetically sealed to the bottom of encapsulant bottom surface 1452 and is sealed to encapsulant surrounding edge 1454.
The follow-up phase of assembly is presented in Figure 17 C, is similar to the follow-up phase of the assembly of Figure 11 E, but is to be used for
Semiconductor packages 1600 (Figure 16).Unit part 1011 and unit part 1012 are attached to secondary the secondary of band 1195 and stick together
Agent.Secondary band 1195 can be supported by carrier structure, and unit part 1011 and unit part 1012 are together with corresponding main
Band part 1191 and 1192 can be picked and place adjacent to each other on secondary band 1195, so that each main band part 1191
Bottom with 1192 is sealed to the secondary adhesive agent of secondary band 1195.Secondary band 1195 is exposed to a gap, described
Gap separates main band part 1191 and 1192 and unit part 1011 and unit part 1012 is separated from one another.
When the pickup and placement operation are completed, EMI shielded layer 1160 is applied.In the present embodiment, EMI shielded layer
1160 are applied as continuous coating, and it includes EMI shielding 1660, EMI to shield 1660 ' and remaining EMI shielding 1163.
EMI shields 1660 capping unit parts 1011, lateral comprising encapsulant top surface 942, encapsulant lateral surfaces 943 and substrate
Surface 913.EMI shields the correspondence component of 1660 ' capping unit parts 1012.The 1163 main band part of covering of remaining EMI shielding
The side wall and secondary band 1195 of 1191 side wall, main band part 1192.In the present embodiment, secondary band 1195 is by main band
The place that part 1191 or 1192 is exposed is covered by remaining EMI shielding 1163, comprising being covered on main band part 1191
On the gap separated with main band part 1192.
The advantages of such configuration provides is similar to the description above in connection with Figure 11 E, so that the thickness of EMI shielded layer 1160
Degree does not swell, but the interface of the main adhesive agent at substrate surrounding edge 914 and across main band part 1191
Place keeps substantially constant.
Particularly because the side wall of main band part 1191 is, EMI shielded layer coplanar with substrate lateral surfaces 913
1160 are not bent at substrate surrounding edge 914, but are real to the side wall of main band part 1191 from substrate lateral surfaces 913
Continuous straight plane in matter.There is no such bending, this bending usually occurs if in main band 1190 and substrate transverse direction table
Interface between face 913 is when being replaced with right angle, and EMI shielded layer 1160 is not accumulated adjacent to substrate surrounding edge 914 or protrusion.
Therefore, main adhesive agent of the thickness of EMI shielded layer 1160 at substrate surrounding edge 914 and across main band part 1191
The interface keep substantially it is constant.
As shown in fig. 17 c be applied with EMI shielded layer 1160, unit part 1011 can be from main 1191 quilt of band part
It pulls out, leaves substrate bottom surface 912 and external interconnection 1480, and generate semiconductor packages together with EMI shielding 1660
1600 (Figure 16).During this removal, main band part 1191 remains attached to secondary band 1195, and EMI shielded layer
1160 accurately rupture along the interface of itself and the main adhesive agent of main band part 1191, thus by EMI shielding 1660 and remaining
EMI shielding 1163 separates.Unit part 1012 can be pulled out similarly from main band part 1192, so that remaining EMI is shielded
1163 remain attached to main band part 1191 and 1192, and are attached to secondary band 1195.In certain embodiments, from master
After the removal for wanting the unit part 1011 at band part 1191, compartment shielding 1690 can be applied.
The characteristic of main band 1190 and secondary band 1195 is kept as above for shown in Figure 11 E, to realize EMI shielded layer
1160 constant thickness and controlled rupture, to allow the increase of substrate lateral surfaces 913 and consistent covering.Therefore, from base
Board bottom surface 912 and along 0 to 50 μm of exposure height is no more than measured by substrate lateral surfaces 913 shielded from EMI
1660 exposures.This is avoided the rupture of EMI shielded layer 1160 by substrate surrounding edge 914, leaves the overhang of EMI shielding 1660
The problem of, and also avoid EMI shielded layer 1160 from excessively rupturing above substrate surrounding edge 914, leave substrate lateral surfaces
913 from EMI shielding 1660 by over-exposure the problem of.
Figure 18 icon is according to the sectional view of the semiconductor packages 1800 of one embodiment.Semiconductor packages 1800 and its group
Part can be similar to the corresponding component of any one or more or they of other semiconductor packages described herein, and
And the characteristic of semiconductor packages 1800 will be further illustrated below.For example, semiconductor packages 1800 can be relevant to
Semiconductor packages 900 described in text, it includes substrates 910, electronic device 920,9201,9202 and 970, driven member
931,932 and 933 and encapsulant 940 and each corresponding portion and component, and be described above about semiconductor package
Fill 900 other character pairs or component.There can be embodiment, wherein semiconductor packages 1800 may include the difference of these components
Combination.The method of feature for construction semiconductor packages 1800 can also be similar to other being described in the present invention to construction
The method of the corresponding feature of one or more of semiconductor packages.
Semiconductor packages 1800 includes electronic device 1875, and the electronic device 1875 is coupled in 970 He of electronic device
Between substrate 910.Electronic device 1875 can be similar to electronic device 970, as shown in Figure 18, but can also have embodiment
It is that wherein electronic device 1875 can for example be similar to passive device 933.Make electronic device using chip-covered boss in the present embodiment
1875 are coupled to the apparatus surface 971 of electronic device 970.
Semiconductor packages 1800 further includes electronic device 1876, and the electronic device 1876 is coupled in electronic device 970
Between substrate 910.Electronic device 1876 can be similar to electronic device 1875, but it is coupled to substrate in the present embodiment
Bottom surface 912.There are also embodiments to be, wherein electronic device 1875 and/or electronic device 1876 can be omitted.
Semiconductor packages 1800 also may include external interconnection 1480, and in the present embodiment, outside interconnection 1480 is rendered as welding
Pellet.As described above, outside, which interconnects 1480, can be similar to external interconnection 980, and it includes any corresponding to external mutual
The even external interconnection of any interconnection option or any other description described in 980 in this article.For example, semiconductor package
It fills 1800 and includes external interconnection 1880, be also similar to outside interconnection 980, but according to for mutual described in external interconnection 980
One kind of item is reelected, outside interconnection 1880 is rendered as the metal column with solder tip.
Semiconductor packages 1800 further includes EMI shielding 1460, compartment shielding 990 and encapsulant 1850, can be similar
In being described in one or more of corresponding bottom encapsulant described herein.There can be other embodiments, wherein in this way
One or more of component can be omitted or replace.For example, one embodiment can omit encapsulant 1850 and/or
The shielding that EMI shielding 1460 can be similar to 1660 (Figure 16-17) of EMI shielding substitutes.Identical or other embodiments can
Compartment shielding 990 is omitted, or can use and be similar to the compartment shielding substitution compartment shielding that compartment shields 1690 (Figure 16-17)
990。
Figure 19 icon is according to the sectional view of the semiconductor packages 1900 of one embodiment.Semiconductor packages 1900 is similar to half
Conductor encapsulates 1800 (Figure 18), but includes substrate 1910.Substrate 1910 can be similar to substrate 910, but include substrate depression
1919, one or more components can be coupled to the height that encapsulation 1900 is further reduced in substrate depression 1919.Substrate
1910 base plate bottom section 1912 defines the substrate of substrate depression 1919, and can be considered as the one of substrate bottom surface 912
Part.In the present embodiment, electronic device 970,1875,1876 and driven member 933 can be inserted in substrate depression 1919 it
In, but can be also by other embodiments, wherein one or more components can not be inserted in wherein.There can be other implementations
Example, wherein at least part of one or more of described component being inserted can protrude from the outer of substrate depression 1919
Side.Substrate depression 1919 is at least partly to be encapsulated object 1950 to be filled, encapsulant 1950 can be similar to encapsulant 1850 but
It is only to extend under substrate bottom surface 912.Encapsulant 1950 is at least partly encapsulated the group for being inserted in substrate depression 1919
Part, but can have other embodiments, wherein encapsulant 1950 can be omitted.Semiconductor packages 1900 can also be shown as having
Compartment shielding 1690 can also have other embodiments among substrate depression 1919, and wherein compartment shielding 1690 can be saved
Slightly or to be similar to the compartment shielding of compartment shielding 990 replace.
Figure 20 icon is according to the sectional view of the semiconductor packages 2000 of one embodiment.Semiconductor packages 2000 is similar to partly lead
Body encapsulates 1800 (Figure 18), but includes substrate 2010, is couple to the substrate top surface 911 of substrate 910.Substrate 2010 can phase
Be similar to substrate 910, but include substrate hole 2019, extend across the thickness of substrate 2010 and its at least partly around
A part of the one or more components of semiconductor packages 2000.For example, electronic device 920,9201 and 9202 can be limited
System can further be protruded from substrate 910 among substrate hole 2019, and therefore than the bottom surface of substrate 2010.Substrate
2010 substrate top surface 2011 can be used to couple the additional component of semiconductor packages 2000, such as electronic device 2020,
It can be similar to electronic device 920 or driven member 2030, driven member 2030 can be similar to driven member 931,932 or 933.?
In the present embodiment, substrate 2010 via interconnection 2080 and be coupled to substrate 910, interconnection 2080 can be similar to interconnection 1480 or
One or more of the interconnection of description in this article.Driven member 932 is shown between substrate 910 and substrate 2010, and
And in the present embodiment, it includes terminal 9321 and 9322, the top of each of which contact substrate 910 and the bottoms of substrate 2010
Portion.The terminal 9321 and/or terminal 9322 of driven member 932 can be normally used as interconnecting, and be similar to interconnection 2080 and interconnection
2080 combine and/or replace interconnection 2080 with transmitting signals or voltage between substrate 910 and substrate 2010.
Figure 21 icon is according to the sectional view of the semiconductor packages 2100 of one embodiment.Semiconductor packages 2100 is similar to partly lead
Body encapsulates 2000 (Figure 20), but includes the substrate 2110 for being couple to the substrate top surface 911 of substrate 910.Substrate 2110 can phase
It is similar to substrate 910, but leaves substrate gap 2119 and is opened on the top of substrate 910, from the lateral surfaces of substrate 2110 to being encapsulated
Object lateral surfaces 943.Substrate gap 2119 can be at least partially around the one of the one or more components of semiconductor packages 2100
Part.For example, electronic device 920 and 9202 is limited among substrate gap 2119, and therefore can compare substrate
2110 bottom surface is further prominent from substrate 910.The substrate top surface 2111 of substrate 2110 can be used to couple semiconductor package
Fill 2100 additional component, such as electronic device 2020 or driven member 2030.In the present embodiment, substrate 2110 is via mutual
Connect 2080 and is coupled to substrate 910.Driven member 932 is displayed between substrate 910 and substrate 2110, wherein driven member
932 at least terminal 9321 contacts the top of substrate 910 and the bottom of substrate 2010.Therefore, at least terminal of driven member 932
9321 can be normally used as interconnecting, and are similar to interconnection 2080, combined with interconnection 2080 and/or replace interconnection 2080 with transmitting signals
Or voltage is between substrate 910 and substrate 2110.
Figure 22 A icon is according to the sectional view of the semiconductor packages 2200 of one embodiment.Figure 22 B is illustrated from Figure 22 A's
The amplifier section of semiconductor packages 2200.Semiconductor packages 2200 and its component can be similar to it is described herein other half
The corresponding component of any one or more or they of conductor encapsulation, and the characteristic of semiconductor packages 2200 will be further
Illustrate below.For example, semiconductor packages 2200 can be relevant to semiconductor packages 900, and it includes substrates 910, electronics
Device 920,9201,9202 and 970, driven member 931,932 and 933 and encapsulant 940, and each corresponding portion
Point and component, and other character pairs or component about semiconductor packages are described above.There can be embodiment, wherein
Semiconductor packages 2200 may include the various combination of these components.
Semiconductor packages 2200 also comprising being couple to the liner of base plate bottom second 9122, may also be referred to as being interconnection lining
Pad.Interconnection 2280 includes interconnection internal 2281 and part interconnection remote portion 2282, can accordingly be similar to and above be retouched
External interconnection 980, interconnection internal 981 and the part interconnection remote portion 982 stated.In addition, semiconductor packages 2200 includes capsule
Seal object 2250, the encapsulant 950 and its individual elements that can be similar in described above and part.Interconnection 2280 is comprising mutual
Even prominent section 2287, projects through encapsulant bottom surface 2252.
The encapsulant 2250 at Figure 22 is shown in be encapsulated substrate bottom surface 912 and any be couple to substrate bottom surface
912 component includes electronic device 970 and driven member 933.In the present embodiment, encapsulant 2250 is shown as covering electricity
The lateral surfaces of 933 the two of sub-device 970 and driven member and the bottom surface of driven member 933, and leave electronic device 970
Bottom surface be exposed.In some embodiments, the encapsulant 2250 can also similarly leave the bottom of driven member 933
Surface is exposed.Encapsulant 2250 can surround external interconnection 2280, and the end section 2282 for leaving external interconnection 2280 is encapsulated
Object 2250 exposes, and it is prominent from encapsulant bottom surface 2252 to leave the prominent section 2287 of interconnection.
Figure 22 includes enlarged view, show external interconnection 2280, encapsulant 2250 and electronic device 970 relative to
Mutual details.In the present embodiment, encapsulant bottom surface 2252 is coplanar with the device bottom surface 972 of electronic device 970.
Encapsulant 2250 also may include through-hole 2255, limitation interconnection 2280.In the present embodiment, through-hole 2255 includes through-hole wall
2256 and through-hole flange 2257, but can have other embodiments, wherein through-hole flange 2257 can be omitted, so that through-hole wall
Contact is interconnected 2280 by 2256 inside end.
Figure 22 further displays electromagnetic interference (EMI) shielding 2260, is similar to EMI shielding 960 described above.
The encapsulant top surface 942 of 2260 covering encapsulant 940 of EMI shielding and the base of encapsulant lateral surfaces 943 and substrate 910
Plate lateral surfaces 913.In the present embodiment, EMI shielding 2260 also covers the encapsulant lateral surfaces 2253 of encapsulant 2250, and
And at least part for leaving encapsulant bottom surface 2252 is exposed, so that EMI shielding 2260 is kept and external 2280 points of interconnection
It separates.
In the present embodiment, semiconductor packages 2200 also comprising with compartment side walls 991 and cell bottom barrier 992 every
Room shielding 990 can be EMI shielding if aforementioned, through construction with comprising one or more components, such as electronic device
970, compartment region in provide EMI protection.In the present embodiment, because the device bottom surface 972 of electronic device 970 is sudden and violent
Dew, cell bottom barrier 992 can be formed on and/or the accessible device bottom surface 972 being exposed through.In other embodiments
In, it can be provided that the apparatus surface 972 being exposed through, and cell bottom barrier different from the dielectric layer of encapsulant 2250
992 can then be formed on the dielectric layer.
Semiconductor packages 2200 can be assembled by each stage of assembly, the assembly comprising such as Figure 10 A to 10C
Initial stage.Figure 23 A to 23E diagram is connected in the various back segment stages of the assembly of Figure 10 A to 10C and ultimately forms and partly leads
Body encapsulates 2200 (Figure 22).
Figure 23 A describes the stage of the assembly similar to Figure 13 A, but is for semiconductor packages 2200 (Figure 22).
The interconnection interior section 2281 of outside interconnection 2280 is attached to substrate surface 912 at unit part 1011, and mutually
Even interior section 2281' is attached to substrate surface 912 at unit part 1012.Figure 23 A is also shown across in list
First part 1011 and unit part 1012 and the encapsulant 2250 applied between unit part 1011 and unit part 1012, with
It is encapsulated substrate surface 912 and coupled all components, including electronic device 970 and 970', 933 and of driven member
933', and interconnection interior section 2281 and 2281 ".Figure 23 A further illustrates the lateral barrier 991 of compartment and 991', attached
It is connected to substrate surface 912 and the periphery of neighbouring electronic device 970 out of the ordinary and 970' and is encapsulated object 2250 and is encapsulated.
In the present embodiment, electronic device 970 includes device original depth (when being originally coupled to substrate surface
It when 912, is measured from apparatus surface 971 to device original bottom 2379).Device of this device original depth than electronic device 970
Final thickness is also thick, (measures as shown in Figure 22 from apparatus surface 971 to apparatus surface 972).As described further below
, this device original depth will be reduced, later to minimize the overall thickness of semiconductor packages 2200.Therefore, it is being coupled to substrate
Before and during bottom surface 912, electronic device 970 can more safely handle and operation, with bigger and structure is firmer
Device original depth.It reduce the risk of damage, breakage and/or production loss, if electronic device 970 with it is relatively thin and compared with
No the device final thickness of structural elasticity (resiient) to be processed similarly, then may be damaged, damaged and/or yield damage
It loses.In some embodiments, device original depth or electronic device 970 can be with 125 μm to 175 μm, and for example, about 150 μm.One
In a little or other embodiments, device original depth may include the thickness for being formed with the semiconductor crystal wafer of electronic device 970.Electronics dress
Substrate 910 can be coupled to via convex block out of the ordinary by setting 970, and convex block can be between apparatus surface 971 and substrate surface 912
Convex block gap between 30 μm to 50 μm of restriction, for example, about 40 μm.
Encapsulant 2250 is applied to be encapsulated interconnection 2280, electronic device 970 and driven member 933 completely.Therefore, capsule
Envelope object original bottom 2359 extends beyond interconnection original bottom 2389 and device original bottom 2379, and has than interconnecting just
The beginning bottom 2389 and also high height (being measured from substrate surface 912) of device original bottom 2379.Once being attached to base
The elemental height of the liner of board bottom portion second 9122, the interconnection 2280 measured at interconnection original bottom 2389 can be arrived at 140 μm
Between 170 μm, for example, about 150 μm.(it is initial by the device of convex block and electronic device 970 for the height of device original bottom 2379
Thickness is defined) can be between 165 μm to 215 μm, for example, about 190 μm.Therefore, the height of device original bottom 2379 can be big
In the height of interconnection original bottom 2389.
Figure 23 B describes the stage of the subsequent assembly similar to Figure 13 B, but is for (the figure of semiconductor packages 2200
22).Encapsulant 2250 is partially removed or thinning is with the bottom of the interconnection interior section of exposure interconnection 2280 and electronic device
970 bottom of device surface 972.Thinning or planarization process reduce encapsulant 2250, interconnection 2280 and electronic device 970
Thickness, until encapsulant bottom surface 2252, interconnection intermediate surface 2289 and bottom of device surface 972 are in required minimum constructive height
Until place appears and is coplanar with each other.In some embodiments, planarization can be related to mechanical polishing process and/or one or more
Etch phase.In the present embodiment, planarization has also appeared the bottom of compartment transverse direction barrier 991.
Therefore, electronic device 970 can be thinned to its device final thickness during thinning processing procedure, while by substrate
910 support and are encapsulated by encapsulant 2250, to allow bottom of device surface 972 relative to the height of substrate surface 912
There is the minimum through strengthening.It is opposite, if electronic device 970 is processed and must before being coupled to substrate surface 912
It must be thinned to identical degree in advance, then this minimized height through strengthening is no unacceptable damage risk the case where
Under be not practical or infeasible.
In some embodiments, after thinning processing procedure, bottom of device surface 972, encapsulant bottom surface 2252 and mutually
Even the height of intermediate surface 2289 can be between 90 μm to 110 μm, and for example, about 100 μm.In identical or other embodiments,
After thinning processing procedure, minimize the device final thickness of electronic device 970, so that its device lateral surface 973 can be
Between 50 μm to 65 μm, for example, about 60 μm.Compared with device original depth, this device final thickness indicates that thickness is reduced at least
60%, even as high as 71%, the integrality without damaging electronic device 970.This thinning processing procedure allows electronic device 970
Device final thickness is safely minimized, for example, the height at most twice convex block gap limited by convex block.Identical or
In other embodiments, this thinning processing procedure can permit the device cross that electronic device 970 is safely minimized to electronic device 920
It can vertically than the device lateral surface 973 of electronic device 970 big at least about 1.6 times of degree to surface 923.Identical
Or in other embodiments, this thinning processing procedure can permit electronic device 970 be safely minimized to substrate lateral surfaces 913 can
With big at least about 2 times of degree vertically than device lateral surface 973.
Figure 23 C describes the stage of the subsequent assembly similar to Figure 11 B, but is for (the figure of semiconductor packages 2200
22).Through-hole 2255 is formed into encapsulant bottom surface 2252, and is extended towards substrate surface 912.In some embodiments
In, through-hole 2255 can by laser ablation, by mechanical ablation and/or by etching ablation into encapsulant 2250 come shape
At.Therefore, through-hole wall 2256 is formed to extend from encapsulant bottom surface 2252 towards substrate surface 912, wherein leading to
Hole wall 2256 defines interconnection encirclement section (the interconnect bounded section's) 2286 for surrounding interconnection 2280
Volume.In the present embodiment, after ablation, through-hole wall 2256 keeps separating with interconnection encirclement section 2286.
As can also be seen that in the present embodiment, the diameter of through-hole wall opening 22561 can be limited to be greater than by ablation
The diameter of through-hole wall substrate 22562.In addition, in the present embodiment, through-hole wall 2256 will not extend to substrate surface
912.In contrast, ablation can limit through-hole platform portion 2257, extend to through-hole wall substrate 2252 from interconnection 2280, wherein
2257 limited hole platform facial planes of through-hole platform portion, can be arranged essentially parallel to encapsulant bottom surface 2252.Therefore, 2280 are interconnected
It may include that interconnection is encapsulated section 2285, be encapsulated into being encapsulated between through-hole platform facial planes and substrate surface 912
Object 2250 contacts.
Cell bottom barrier 992 applies after being illustrated in planarization process, and the region of 970 lower section of overlay electronic device
And it is contacted with the bottom of the exposing of compartment transverse direction barrier 991.In some embodiments, dielectric materials layer can also be applied with position
Between the region and cell bottom barrier 992 of 970 lower section of electronic device.If desired, the application of cell bottom barrier can be with
It is carried out in later phases.In other embodiments, it is convenient to omit compartment shielding 990 and/or cell bottom barrier 992.
Figure 23 D describes the stage of the subsequent assembly similar to Figure 13 C, but is for (the figure of semiconductor packages 2200
22).Interconnection remote portion 2282 is coupled to the interconnection intermediate surface 2289 of interconnection interior section 2281 (as extremely schemed by Figure 23 B
The processing procedure exposure of 23C), thus protrude from encapsulant bottom surface 2252.In some embodiments, can be used solder drop or
Globule processing procedure, screen painting processing procedure or plating processing procedure interconnect remote portion 2282 to apply.In identical or other embodiments, mutually
Even once attachment can at least partly reflow for remote portion 2282.
In the present embodiment, the volume for interconnecting interior section 2281 is greater than the volume of interconnection remote portion 2282, so that mutually
Even the periphery of remote portion 2282 is enclosed in the region of interconnection intermediate surface 2289.Therefore, remote portion 2282 is interconnected
Material tends to not overflow in through-hole 2255, so that the separation that through-hole wall 2256 and interconnection are surrounded between section 2286 is still protected
It stays.
Figure 23 E presents the stage for semiconductor packages 2200 (Figure 22) subsequent assembly.Interconnect interior section 2281
It is shown as reflow each other with interconnection remote portion 2282, respective volume combination is to limit the final interconnection volume for interconnecting 2280
And height, wherein interconnecting prominent section 2287 protrudes past at least 50 μm of encapsulant bottom surface 2252, outer when being connected to
There is appropriate gap when portion's substrate or device.Particularly, the interconnection remote portion 2282 implemented in Figure 23 D may be configured so that
When interconnection 2281 reflow of interior section in Figure 23 E, interconnect 2280 final volume and/or height can in Figure 23 A most
The initial volume of the interconnection 2280 just implemented and/or height it is essentially identical or similar or 5% in.
During back welding process, the interval between through-hole wall 2256 and interconnection encirclement section 2286 allows to interconnect interior section
2281 and interconnection the reflow freely with each other of remote portion 2282.This feature, which can be reduced, otherwise will deform or limit interconnection 2280
Final shape and height static friction, and limit any " explosion (blow up) " or eruption of the material of interconnection 2280
(eruption) (when the constraint by relatively narrow aperture other in encapsulant bottom surface 2252, this can tend to pass through pressure
Injection).This feature also allows to realize closer spacing between adjacent interconnection 2280.For example, fewer than half interconnection
2280 elemental height can be thinned in Figure 23 B, and at least half for leaving its initial volume and height is still encapsulated, because slightly
Through-hole 2255 extends the narrow encapsulant hole that in addition can generate the explosion issues in Figure 23 C afterwards.Therefore, when scheming
When applying interconnection 2280 in 23A, lesser interconnection diameter originally can be used, cause interconnection spacing closer.However, if needing
Want, can be used biggish initial diameter interconnection 2280, and/or can in Figure 23 B thinning this be interconnected to interconnection 2280 just
More than half of beginning height, while still benefiting from the reduction of static friction.
The stage of further assembly can be carried out to generate encapsulation 2200 as shown in figure 22, by being similar to
Such as above with respect to the described any processing procedure of any EMI shielding of the present invention (such as EMI shielding Figure 11 D extremely
EMI shielding 2260 is formed in processing procedure 11E).
Here discussion includes many illustrative embodiments, and it illustrates the various pieces of electronic packaging component and its manufacturers
Method.For clarity, these figures do not show that all aspects of each embodiment component.Any embodiment presented herein
Other any or all of any embodiment components and/or method that component and/or method can be presented with the present invention are shared any
Or complete characteristic.
In conclusion the method that various aspects of the invention provide semiconductor packages and manufacture semiconductor packages.As
Non-limiting embodiment, various aspects of the invention provide semiconductor packages and its manufacturing method comprising in its multiple side
On shielding.Although front has been directed to certain aspects and embodiment to be described, art technology personage should be managed
Solution, without departing from the scope of the invention, can carry out various changes and available equivalents to replace.This
Outside, many modify so that specific condition or material adapt to teachings of the present invention, without departing from its range can be carried out.For example, being
The enough volumes of offer will interconnect 980 (Fig. 9,11), 1280 (Figure 12,13) of interconnection or interconnect each of 1480 (Figure 14 to 21)
Other protrusion is encapsulated in the main adhesive agent of main band 1190, and the thickness of this main adhesive agent can according to need change,
Interconnecting parts, and the thickness of the basal layer of typically larger than main band 1190 are protruded to be greater than this.Because of time of secondary band 1195
Adhesive agent is wanted not to be encapsulated these different interconnection, so its thickness is not needed to change in various embodiments and/or can be protected
It holds more thinner than the main adhesive agent of main band 1190.
Therefore, it is desirable to the present invention is not limited to disclosed specific (multiple) embodiments, and the present invention will include falling
Enter all embodiments in scope of the appended claims.
Claims (20)
1. a kind of semiconductor packages characterized by comprising
Substrate comprising:
Substrate top side comprising the liner of substrate top first and substrate top second pad；
Substrate bottom side comprising the liner of base plate bottom first and base plate bottom second pad；
Substrate cross side；
First electronic device on the substrate top side and is coupled to the substrate top first and pads, wherein described the
One electronic device includes:
First device bottom side faces the substrate top side；
First device top side；And
First device cross side；
Driven member on the substrate top side and is coupled to the liner of substrate top second；
First encapsulant is at least encapsulated the substrate top side, the driven member and first electronic device, wherein institute
Stating the first encapsulant includes:
First encapsulant bottom side faces the substrate top side；
First encapsulant top side；And
First encapsulant cross side；
Second electronic device on the substrate bottom side and is coupled to the base plate bottom first and pads, wherein described the
Two electronic devices include:
Second device top side faces the substrate bottom side；
Second device bottom side；And
Second device cross side；
Outside interconnects, and on the substrate bottom side and includes:
Top interconnects end, is coupled to the base plate bottom second and pads；And
Lower section interconnects end；
Second encapsulant is at least encapsulated the substrate bottom side and the second electronic device, wherein second encapsulant
Include:
Second encapsulant top side faces the substrate bottom side；
Second encapsulant bottom side；And
Second encapsulant cross side,
Wherein lower section interconnection end is also lower than second encapsulant bottom side；And
Electromagnetic interference EMI shielding, is at least surrounded:
First encapsulant top side；
The first encapsulant cross side；And
The substrate cross side,
Wherein the electromagnetic interference shield is opened with the external interconnection barriers.
2. semiconductor packages according to claim 1, which is characterized in that at least part of the second device bottom side from
The second encapsulant exposure.
3. semiconductor packages according to claim 2, which is characterized in that the first device cross side is in vertical direction
It is also longer than the second device cross side.
4. semiconductor packages according to claim 1, which is characterized in that first encapsulant includes having molding material
First layer；And
Second encapsulant includes the second layer with the molding material.
5. semiconductor packages according to claim 1, which is characterized in that the outside, which interconnects, includes:
It is encapsulated section, surrounded and contacted with the first part by the first part of second encapsulant；
Exposure section, is surrounded and separated with the second part by the second part of second encapsulant；And
Prominent section is also lower than second encapsulant bottom side.
6. semiconductor packages according to claim 5, which is characterized in that second encapsulant includes platform portion, transverse direction
Around the external interconnection and it is located between the first part and the second part of second encapsulant.
7. semiconductor packages according to claim 1, which is characterized in that the electromagnetic interference shield includes continuous conformal
Coating conforms to first encapsulant top side, the first encapsulant cross side, the substrate cross side and described the
The respective profile of two encapsulant cross sides.
8. semiconductor packages according to claim 1, which is characterized in that the electromagnetic interference shield covers second capsule
Object cross side is sealed, so that in vertical direction derived from second encapsulant bottom side and along the second encapsulant cross side
Measured exposure height is exposed from the electromagnetic interference shield no more than 0 to 50 μm.
9. semiconductor packages according to claim 1, which is characterized in that the second device bottom side and described second is encapsulated
Object bottom side is coplanar.
10. a kind of semiconductor packages characterized by comprising
Substrate comprising:
Substrate top side comprising the liner of substrate top first and substrate top second pad；
Substrate bottom side comprising substrate third liner and substrate interconnection liner；And
Substrate cross side；
First device on the substrate top side and is coupled to the liner of substrate top first, wherein first dress
It sets and includes:
First device bottom side faces the substrate top side；
First device top side；And
First device cross side；
Second device on the substrate top side and is coupled to the liner of substrate top second；
First encapsulant is at least encapsulated the substrate top side, the first device and the second device, wherein described
One encapsulant includes:
First encapsulant bottom side faces the substrate top side；
First encapsulant top side；And
First encapsulant cross side；
3rd device on the substrate bottom side and is coupled to the substrate third liner, wherein the 3rd device packet
It includes:
3rd device top side faces the substrate bottom side；
3rd device bottom side；And
3rd device cross side；
Interconnection, in the substrate bottom side and is coupled to the substrate interconnection liner, wherein described interconnect partly is led to described
Body encapsulation provides external interface and includes:
Top interconnects end, is coupled to the substrate interconnection liner；And
Lower section interconnects end；
Second encapsulant is encapsulated at least part of each in the substrate bottom side and the 3rd device, wherein institute
Stating the second encapsulant includes:
Second encapsulant top side faces the substrate bottom side；
Second encapsulant bottom side；And
Second encapsulant cross side；And
Electromagnetic interference EMI shielding, is at least surrounded:
First encapsulant top side；
The first encapsulant cross side；And
The substrate cross side,
Wherein:
Lower section interconnection end is also lower than second encapsulant bottom side；And
At least one of the first device, the second device or described 3rd device are electronic devices；And
At least one of the first device, the second device or described 3rd device are driven members.
11. semiconductor packages according to claim 10, which is characterized in that it further include bottom electromagnetic interference EMI shielding,
At least:
Around the 3rd device cross side；
Second encapsulant is extended through from the substrate bottom side and towards second encapsulant bottom side；And
It does not include thin-sheet metal.
12. semiconductor packages according to claim 10, which is characterized in that at least part of the 3rd device bottom side
From second encapsulant exposure.
13. semiconductor packages according to claim 10, which is characterized in that first encapsulant includes having molding material
The first layer of material；And
Second encapsulant includes the second layer with the molding material.
14. semiconductor packages according to claim 10, which is characterized in that the outside, which interconnects, includes:
It is encapsulated section, surrounded and contacted with the first part by the first part of second encapsulant；
Exposure section, is surrounded and separated with the second part by the second part of second encapsulant；And
Prominent section is also lower than second encapsulant bottom side.
15. semiconductor packages according to claim 14, which is characterized in that second encapsulant includes platform portion, horizontal
To around the interconnection and between the first part and the second part of second encapsulant.
16. semiconductor packages according to claim 10, which is characterized in that the electromagnetic interference shield includes continuous protects
Shape coating, conforms to first encapsulant top side, the first encapsulant cross side, the substrate cross side and described
The respective profile of second encapsulant cross side.
17. a kind of manufacturing method characterized by comprising
Substrate is provided comprising:
Substrate top side comprising the liner of substrate top first and substrate top second pad；
Substrate bottom side comprising substrate third liner and substrate interconnection liner；And
Substrate cross side；
First device is provided, on the substrate top side and the substrate top first is coupled to and pads, wherein described the
One device includes:
First device bottom side faces the substrate top side；
First device top side；And
First device cross side；
Second device is provided, on the substrate top side and is coupled to the liner of substrate top second；
First encapsulant is encapsulated the substrate top side, the first device and the second device, wherein first capsule
Sealing object includes:
First encapsulant bottom side faces the substrate top side；
First encapsulant top side；And
First encapsulant cross side；
3rd device is provided, on the substrate bottom side and the substrate third liner is coupled to, wherein the third fills
It sets and includes:
3rd device top side faces the substrate bottom side；
3rd device bottom side；And
3rd device cross side；And
Interconnection is provided, on the substrate bottom side and the substrate interconnection liner is coupled to, wherein the interconnection includes:
Top interconnects end, is coupled to the substrate interconnection liner；And
Lower section interconnects end；And
Second encapsulant is provided, is encapsulated in the substrate bottom side, the 3rd device and the interconnection each at least
A part, wherein second encapsulant includes:
Second encapsulant top side faces the substrate bottom side；
Second encapsulant bottom side；And
Second encapsulant cross side,
Wherein:
Lower section interconnection end is also lower than second encapsulant bottom side；And
At least one of the first device, the second device or described 3rd device are electronic devices；And
At least one of the first device, the second device or described 3rd device are driven members.
18. according to the method for claim 17, which is characterized in that second encapsulant is encapsulated at least the one of the interconnection
Part.
19. according to the method for claim 17, which is characterized in that further include forming the first electromagnetic interference EMI shielding, packet
It includes at least:
First encapsulant top side；
The first encapsulant cross side, and
The substrate cross side.
20. according to the method for claim 17, which is characterized in that the interconnection includes:
It is encapsulated section, surrounded and contacted with the first part by the first part of second encapsulant；
Exposure section, is surrounded and separated with the second part by the second part of second encapsulant；And
Prominent section is also lower than second encapsulant bottom side.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/871,617 | 2018-01-15 | ||
| US15/871,617 US10163867B2 (en) | 2015-11-12 | 2018-01-15 | Semiconductor package and manufacturing method thereof |
| US16/037,686 US10872879B2 (en) | 2015-11-12 | 2018-07-17 | Semiconductor package and manufacturing method thereof |
| US16/037,686 | 2018-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110047826A true CN110047826A (en) | 2019-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910037043.XA Pending CN110047826A (en) | 2018-01-15 | 2019-01-15 | Semiconductor packages and its manufacturing method |
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| CN (1) | CN110047826A (en) |
| TW (2) | TWI800591B (en) |
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| CN115632046A (en) * | 2022-12-07 | 2023-01-20 | 江苏长晶浦联功率半导体有限公司 | Chip packaging structure and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
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| TWI839179B (en) | 2024-04-11 |
| TWI800591B (en) | 2023-05-01 |
| TW202333248A (en) | 2023-08-16 |
| TW201933498A (en) | 2019-08-16 |
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