CN110047529B - Signal adaptive amplification multipath audio recording device and method - Google Patents
Signal adaptive amplification multipath audio recording device and method Download PDFInfo
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Abstract
The invention relates to audio recording equipment, in particular to multipath audio recording equipment and a multipath audio recording method for signal adaptive amplification. The invention solves the problems of inconvenient data checking and analysis, high distortion degree of the acquired data, large zero drift and low acquisition precision of the traditional audio recording equipment when the signal intensity is suddenly changed. A multipath audio recording device with signal self-adaptive amplification comprises an FPGA chip, a plurality of BNC interfaces, a plurality of signal self-adaptive amplification circuits, an MIC interface, an ADAU1977 audio analog-to-digital converter, an STM32F103RET6 singlechip, an IMX6QARM processor, a SATA hard disk, a PC upper computer, a first relay, a second relay, an LED display screen, a plurality of operation keys and a plurality of status indicator lamps; the number of BNC interfaces is consistent with that of the signal self-adaptive amplifying circuits; each BNC interface is connected with the input end of each signal self-adaptive amplifying circuit in a one-to-one correspondence manner. The invention is suitable for the collection of audio data.
Description
Technical Field
The invention relates to audio recording equipment, in particular to multipath audio recording equipment and a multipath audio recording method for signal adaptive amplification.
Background
At present, the collection of audio data is commonly implemented by using an audio recording device. However, the conventional audio recording apparatus has the following problems due to its own structure: first, conventional audio recording devices do not have a data monitoring function, and thus data must be derived from the device to be viewed and analyzed, thereby making viewing and analysis of the data inconvenient. Secondly, the traditional audio recording device needs to adjust the amplification factor through a manual mode, but cannot automatically adjust the amplification factor according to the signal intensity, so that when the signal intensity is suddenly changed, the phenomenon that the amplification factor is not matched with the signal intensity can occur, and the distortion degree of the collected data is high. Third, the traditional audio recording equipment has the problems of large zero drift and low acquisition precision. Based on the above, it is necessary to invent a brand new audio recording device and method, so as to solve the problems that the traditional audio recording device is inconvenient for data viewing and analysis, and the acquired data has high distortion degree, large zero drift and low acquisition accuracy when the signal intensity is suddenly changed.
Disclosure of Invention
The invention provides a multipath audio recording device and a multipath audio recording method for signal self-adaptive amplification, which are used for solving the problems that the traditional audio recording device is inconvenient for checking and analyzing data, the distortion degree of the acquired data is high, zero drift is large and the acquisition precision is low when the signal intensity is suddenly changed.
The invention is realized by adopting the following technical scheme:
a multipath audio recording device with signal self-adaptive amplification comprises an FPGA chip, a plurality of BNC interfaces, a plurality of signal self-adaptive amplification circuits, an MIC interface, an ADAU1977 audio analog-to-digital converter, an STM32F103RET6 singlechip, an IMX6QARM processor, a SATA hard disk, a PC upper computer, a first relay, a second relay, an LED display screen, a plurality of operation keys and a plurality of status indicator lamps; the number of BNC interfaces is consistent with that of the signal self-adaptive amplifying circuits; each BNC interface is connected with the input end of each signal self-adaptive amplifying circuit in a one-to-one correspondence manner; the output end of each signal self-adaptive amplifying circuit is connected with the input end of the ADAU1977 audio analog-to-digital converter; the control end of each signal self-adaptive amplifying circuit is connected with the output end of the FPGA chip; the output end of the MIC interface is connected with the input end of the ADAU1977 audio analog-to-digital converter; the output end of the ADAU1977 audio analog-to-digital converter is connected with the input end of the FPGA chip; the STM32F103RET6 singlechip is connected with the FPGA chip in a bidirectional way; the IMX6QARM processor is connected with the STM32F103RET6 singlechip in a bidirectional manner; the SATA hard disk is in bidirectional connection with the IMX6QARM processor; the input end of the first relay is connected with the output end of the STM32F103RET6 singlechip; the normally-closed end of the first relay is connected with the FPGA chip in a bidirectional manner; the normal open end of the first relay is connected with the PC upper computer in a bidirectional way; the public end of the first relay is in bidirectional connection with the IMX6QARM processor; the input end of the second relay is connected with the output end of the STM32F103RET6 singlechip; the normally closed end of the second relay is suspended; the normal open end of the second relay is connected with the PC upper computer in a bidirectional way; the public end of the second relay is connected with the FPGA chip in a bidirectional way; the input end of the LED display screen is connected with the output end of the STM32F103RET6 singlechip; each operation key is connected with the input end of the STM32F103RET6 singlechip; each status indicator lamp is connected with the output end of the STM32F103RET6 singlechip.
A signal self-adaptive amplified multi-channel audio recording method (the method is realized based on a signal self-adaptive amplified multi-channel audio recording device) which is realized by adopting the following steps:
s1: after the equipment is powered on, the equipment defaults to enter a data monitoring mode; in a data monitoring mode, the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to be powered on in real time, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected; then, each path of audio signals to be collected is input to each signal self-adaptive amplifying circuit in real time through each BNC interface, filtered and amplified by each signal self-adaptive amplifying circuit and then input to the ADAU1977 audio analog-to-digital converter in real time, and then input to the FPGA chip in real time after analog-to-digital conversion by the ADAU1977 audio analog-to-digital converter; meanwhile, the environmental noise signals to be collected are input to the ADAU1977 audio analog-to-digital converter in real time through the MIC interface, and are input to the FPGA chip in real time after being subjected to analog-to-digital conversion through the ADAU1977 audio analog-to-digital converter; then, the FPGA chip carries out real-time processing on each path of received audio signals and environment noise signals, and sends the processed audio data and environment noise data to an STM32F103RET6 singlechip on one hand, and sends the processed audio data and environment noise data to an IMX6QARM processor through a first relay on the other hand, and sends the processed audio data and environment noise data to a PC upper computer through a second relay on the other hand; then, the STM32F103RET6 singlechip sends the received audio data and the environmental noise data to the LED display screen in real time for display, the IMX6QARM processor sends the received audio data and the environmental noise data to the SATA hard disk in real time for storage, and the PC upper computer monitors the received audio data and the environmental noise data in real time; in the process, the FPGA chip automatically adjusts the amplification factors of the signal self-adaptive amplification circuits according to the intensity of each received audio signal, so that the amplification factors of the signal self-adaptive amplification circuits are matched with the intensity of each audio signal;
s2: in the data monitoring process, if data export is to be carried out, a user sends out a data export command in real time through a PC upper computer; the data export command is sequentially sent to the STM32F103RET6 singlechip in real time through the second relay and the FPGA chip; the STM32F103RET6 singlechip controls the first relay to be powered on and the second relay to be powered off in real time according to the received data export command, so that the normally-open end and the public end of the first relay are connected, and the normally-closed end and the public end of the second relay are connected, and the equipment enters a data export mode; then, the IMX6QARM processor reads audio data and environmental noise data in the SATA hard disk in real time, and sends the read audio data and environmental noise data to the PC upper computer in real time through the first relay, so that data export is realized;
s3: after the data is exported, a user sends out a data monitoring command in real time through the PC upper computer; the data monitoring command is sequentially transmitted to the STM32F103RET6 singlechip in real time through the first relay and the IMX6QARM processor; the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to obtain power in real time according to the received data monitoring command, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected, and the equipment enters a data monitoring mode again.
Based on the above process, compared with the traditional audio recording device, the signal self-adaptive amplification multipath audio recording device and method of the invention have the following advantages by adopting brand new structure and principle: firstly, the invention has the function of data monitoring, so that the data can be checked and analyzed without exporting the data from the equipment, thereby facilitating the check and analysis of the data. Secondly, the invention realizes automatic adjustment of the amplification factor according to the signal intensity, so that the phenomenon that the amplification factor is not matched with the signal intensity can not occur even if the signal intensity is suddenly changed, and the distortion degree of the acquired data is reduced. Third, the zero drift of the invention is smaller, and the acquisition precision is higher.
The invention has reasonable structure and ingenious design, effectively solves the problems of high distortion degree, large zero drift and low acquisition precision of the acquired data when the traditional audio recording equipment is inconvenient for checking and analyzing the data and the signal intensity is suddenly changed, and is suitable for the acquisition of the audio data.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Fig. 2 is a schematic diagram of a signal adaptive amplifying circuit according to the present invention.
Detailed Description
A multipath audio recording device with signal self-adaptive amplification comprises an FPGA chip, a plurality of BNC interfaces, a plurality of signal self-adaptive amplification circuits, an MIC interface, an ADAU1977 audio analog-to-digital converter, an STM32F103RET6 singlechip, an IMX6QARM processor, a SATA hard disk, a PC upper computer, a first relay, a second relay, an LED display screen, a plurality of operation keys and a plurality of status indicator lamps; the number of BNC interfaces is consistent with that of the signal self-adaptive amplifying circuits; each BNC interface is connected with the input end of each signal self-adaptive amplifying circuit in a one-to-one correspondence manner; the output end of each signal self-adaptive amplifying circuit is connected with the input end of the ADAU1977 audio analog-to-digital converter; the control end of each signal self-adaptive amplifying circuit is connected with the output end of the FPGA chip; the output end of the MIC interface is connected with the input end of the ADAU1977 audio analog-to-digital converter; the output end of the ADAU1977 audio analog-to-digital converter is connected with the input end of the FPGA chip; the STM32F103RET6 singlechip is connected with the FPGA chip in a bidirectional way; the IMX6QARM processor is connected with the STM32F103RET6 singlechip in a bidirectional manner; the SATA hard disk is in bidirectional connection with the IMX6QARM processor; the input end of the first relay is connected with the output end of the STM32F103RET6 singlechip; the normally-closed end of the first relay is connected with the FPGA chip in a bidirectional manner; the normal open end of the first relay is connected with the PC upper computer in a bidirectional way; the public end of the first relay is in bidirectional connection with the IMX6QARM processor; the input end of the second relay is connected with the output end of the STM32F103RET6 singlechip; the normally closed end of the second relay is suspended; the normal open end of the second relay is connected with the PC upper computer in a bidirectional way; the public end of the second relay is connected with the FPGA chip in a bidirectional way; the input end of the LED display screen is connected with the output end of the STM32F103RET6 singlechip; each operation key is connected with the input end of the STM32F103RET6 singlechip; each status indicator lamp is connected with the output end of the STM32F103RET6 singlechip.
The signal self-adaptive amplifying circuit comprises a first TLC2652 operational amplifier, an AD8253 instrument amplifier, a second TLC2652 operational amplifier, first to fourth inductors L1 to L4 and first to fifth capacitors C1 to C5; one end of the first inductor L1 is used as an input end of the signal self-adaptive amplifying circuit, and the other end of the first inductor L1 is connected with a positive input end of the first TLC2652 operational amplifier through a first capacitor C1; the negative input end of the first TLC2652 operational amplifier is grounded; the output end of the first TLC2652 operational amplifier is connected with the positive input end of the AD8253 instrument amplifier through a second capacitor C2; the negative input end of the AD8253 instrument amplifier is grounded; the output end of the AD8253 instrument amplifier is connected with the positive input end of the second TLC2652 operational amplifier through a third capacitor C3; the negative input end of the second TLC2652 operational amplifier is grounded; the output end of the second TLC2652 operational amplifier is connected with one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is used as an output end of the signal self-adaptive amplifying circuit; the control end of the AD8253 instrument amplifier is used as the control end of the signal self-adaptive amplifying circuit; one end of the fifth capacitor C5 is grounded, and the other end of the fifth capacitor C5 is connected with the positive input end of the first TLC2652 operational amplifier through the first capacitor C1; one end of the second inductor L2 is grounded, and the other end of the second inductor L2 is connected with the output end of the first TLC2652 operational amplifier; one end of the third inductor L3 is grounded, and the other end of the third inductor L3 is connected with the output end of the AD8253 instrument amplifier; one end of the fourth inductor L4 is grounded, and the other end is connected to the output end of the second TLC2652 operational amplifier.
A signal self-adaptive amplified multi-channel audio recording method (the method is realized based on a signal self-adaptive amplified multi-channel audio recording device) which is realized by adopting the following steps:
s1: after the equipment is powered on, the equipment defaults to enter a data monitoring mode; in a data monitoring mode, the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to be powered on in real time, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected; then, each path of audio signals to be collected is input to each signal self-adaptive amplifying circuit in real time through each BNC interface, filtered and amplified by each signal self-adaptive amplifying circuit and then input to the ADAU1977 audio analog-to-digital converter in real time, and then input to the FPGA chip in real time after analog-to-digital conversion by the ADAU1977 audio analog-to-digital converter; meanwhile, the environmental noise signals to be collected are input to the ADAU1977 audio analog-to-digital converter in real time through the MIC interface, and are input to the FPGA chip in real time after being subjected to analog-to-digital conversion through the ADAU1977 audio analog-to-digital converter; then, the FPGA chip carries out real-time processing on each path of received audio signals and environment noise signals, and sends the processed audio data and environment noise data to an STM32F103RET6 singlechip on one hand, and sends the processed audio data and environment noise data to an IMX6QARM processor through a first relay on the other hand, and sends the processed audio data and environment noise data to a PC upper computer through a second relay on the other hand; then, the STM32F103RET6 singlechip sends the received audio data and the environmental noise data to the LED display screen in real time for display, the IMX6QARM processor sends the received audio data and the environmental noise data to the SATA hard disk in real time for storage, and the PC upper computer monitors the received audio data and the environmental noise data in real time; in the process, the FPGA chip automatically adjusts the amplification factors of the signal self-adaptive amplification circuits according to the intensity of each received audio signal, so that the amplification factors of the signal self-adaptive amplification circuits are matched with the intensity of each audio signal;
s2: in the data monitoring process, if data export is to be carried out, a user sends out a data export command in real time through a PC upper computer; the data export command is sequentially sent to the STM32F103RET6 singlechip in real time through the second relay and the FPGA chip; the STM32F103RET6 singlechip controls the first relay to be powered on and the second relay to be powered off in real time according to the received data export command, so that the normally-open end and the public end of the first relay are connected, and the normally-closed end and the public end of the second relay are connected, and the equipment enters a data export mode; then, the IMX6QARM processor reads audio data and environmental noise data in the SATA hard disk in real time, and sends the read audio data and environmental noise data to the PC upper computer in real time through the first relay, so that data export is realized;
s3: after the data is exported, a user sends out a data monitoring command in real time through the PC upper computer; the data monitoring command is sequentially transmitted to the STM32F103RET6 singlechip in real time through the first relay and the IMX6QARM processor; the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to obtain power in real time according to the received data monitoring command, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected, and the equipment enters a data monitoring mode again.
Claims (2)
1. A multi-channel audio recording apparatus for adaptive signal amplification, characterized by: the system comprises an FPGA chip, a plurality of BNC interfaces, a plurality of signal self-adaptive amplifying circuits, an MIC interface, an ADAU1977 audio analog-to-digital converter, an STM32F103RET6 singlechip, an IMX6QARM processor, a SATA hard disk, a PC upper computer, a first relay, a second relay, an LED display screen, a plurality of operation keys and a plurality of status indicator lamps; the number of BNC interfaces is consistent with that of the signal self-adaptive amplifying circuits; each BNC interface is connected with the input end of each signal self-adaptive amplifying circuit in a one-to-one correspondence manner; the output end of each signal self-adaptive amplifying circuit is connected with the input end of the ADAU1977 audio analog-to-digital converter; the control end of each signal self-adaptive amplifying circuit is connected with the output end of the FPGA chip; the output end of the MIC interface is connected with the input end of the ADAU1977 audio analog-to-digital converter; the output end of the ADAU1977 audio analog-to-digital converter is connected with the input end of the FPGA chip; the STM32F103RET6 singlechip is connected with the FPGA chip in a bidirectional way; the IMX6QARM processor is connected with the STM32F103RET6 singlechip in a bidirectional manner; the SATA hard disk is in bidirectional connection with the IMX6QARM processor; the input end of the first relay is connected with the output end of the STM32F103RET6 singlechip; the normally-closed end of the first relay is connected with the FPGA chip in a bidirectional manner; the normal open end of the first relay is connected with the PC upper computer in a bidirectional way; the public end of the first relay is in bidirectional connection with the IMX6QARM processor; the input end of the second relay is connected with the output end of the STM32F103RET6 singlechip; the normally closed end of the second relay is suspended; the normal open end of the second relay is connected with the PC upper computer in a bidirectional way; the public end of the second relay is connected with the FPGA chip in a bidirectional way; the input end of the LED display screen is connected with the output end of the STM32F103RET6 singlechip; each operation key is connected with the input end of the STM32F103RET6 singlechip; each state indicator lamp is connected with the output end of the STM32F103RET6 singlechip;
the equipment is realized by the following steps:
s1: after the equipment is powered on, the equipment defaults to enter a data monitoring mode; in a data monitoring mode, the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to be powered on in real time, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected; then, each path of audio signals to be collected is input to each signal self-adaptive amplifying circuit in real time through each BNC interface, filtered and amplified by each signal self-adaptive amplifying circuit and then input to the ADAU1977 audio analog-to-digital converter in real time, and then input to the FPGA chip in real time after analog-to-digital conversion by the ADAU1977 audio analog-to-digital converter; meanwhile, the environmental noise signals to be collected are input to the ADAU1977 audio analog-to-digital converter in real time through the MIC interface, and are input to the FPGA chip in real time after being subjected to analog-to-digital conversion through the ADAU1977 audio analog-to-digital converter; then, the FPGA chip carries out real-time processing on each path of received audio signals and environment noise signals, and sends the processed audio data and environment noise data to an STM32F103RET6 singlechip on one hand, and sends the processed audio data and environment noise data to an IMX6QARM processor through a first relay on the other hand, and sends the processed audio data and environment noise data to a PC upper computer through a second relay on the other hand; then, the STM32F103RET6 singlechip sends the received audio data and the environmental noise data to the LED display screen in real time for display, the IMX6QARM processor sends the received audio data and the environmental noise data to the SATA hard disk in real time for storage, and the PC upper computer monitors the received audio data and the environmental noise data in real time; in the process, the FPGA chip automatically adjusts the amplification factors of the signal self-adaptive amplification circuits according to the intensity of each received audio signal, so that the amplification factors of the signal self-adaptive amplification circuits are matched with the intensity of each audio signal;
s2: in the data monitoring process, if data export is to be carried out, a user sends out a data export command in real time through a PC upper computer; the data export command is sequentially sent to the STM32F103RET6 singlechip in real time through the second relay and the FPGA chip; the STM32F103RET6 singlechip controls the first relay to be powered on and the second relay to be powered off in real time according to the received data export command, so that the normally-open end and the public end of the first relay are connected, and the normally-closed end and the public end of the second relay are connected, and the equipment enters a data export mode; then, the IMX6QARM processor reads audio data and environmental noise data in the SATA hard disk in real time, and sends the read audio data and environmental noise data to the PC upper computer in real time through the first relay, so that data export is realized;
s3: after the data is exported, a user sends out a data monitoring command in real time through the PC upper computer; the data monitoring command is sequentially transmitted to the STM32F103RET6 singlechip in real time through the first relay and the IMX6QARM processor; the STM32F103RET6 singlechip controls the first relay to lose power and the second relay to obtain power in real time according to the received data monitoring command, so that the normally-closed end and the public end of the first relay are connected, and the normally-open end and the public end of the second relay are connected, and the equipment enters a data monitoring mode again.
2. A signal adaptively amplified multi-channel audio recording device according to claim 1, wherein: the signal self-adaptive amplifying circuit comprises a first TLC2652 operational amplifier, an AD8253 instrument amplifier, a second TLC2652 operational amplifier, first to fourth inductors (L1-L4) and first to fifth capacitors (C1-C5); one end of a first inductor (L1) is used as an input end of the signal self-adaptive amplifying circuit, and the other end of the first inductor is connected with a positive input end of a first TLC2652 operational amplifier through a first capacitor (C1); the negative input end of the first TLC2652 operational amplifier is grounded; the output end of the first TLC2652 operational amplifier is connected with the positive input end of the AD8253 instrument amplifier through a second capacitor (C2); the negative input end of the AD8253 instrument amplifier is grounded; the output end of the AD8253 instrument amplifier is connected with the positive input end of the second TLC2652 operational amplifier through a third capacitor (C3); the negative input end of the second TLC2652 operational amplifier is grounded; the output end of the second TLC2652 operational amplifier is connected with one end of a fourth capacitor (C4); the other end of the fourth capacitor (C4) is used as the output end of the signal self-adaptive amplifying circuit; the control end of the AD8253 instrument amplifier is used as the control end of the signal self-adaptive amplifying circuit; one end of the fifth capacitor (C5) is grounded, and the other end of the fifth capacitor is connected with the positive input end of the first TLC2652 operational amplifier through the first capacitor (C1); one end of the second inductor (L2) is grounded, and the other end of the second inductor is connected with the output end of the first TLC2652 operational amplifier; one end of the third inductor (L3) is grounded, and the other end of the third inductor is connected with the output end of the AD8253 instrument amplifier; one end of the fourth inductor (L4) is grounded, and the other end of the fourth inductor is connected with the output end of the second TLC2652 operational amplifier.
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| CN1588966A (en) * | 2004-09-27 | 2005-03-02 | 新太科技股份有限公司 | Method for detecting ADSC line parameter |
| CN104571189A (en) * | 2015-01-09 | 2015-04-29 | 西安交通大学 | Blow molding equipment intelligent temperature control system and method based on DSP and FPGA |
| CN206274366U (en) * | 2016-10-26 | 2017-06-23 | 中国船舶重工集团公司第七二六研究所 | Self-adapting multi-channel power supply real-time monitoring circuit system |
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| AT504164B1 (en) * | 2006-09-15 | 2009-04-15 | Tech Universit T Graz | DEVICE FOR NOISE PRESSURE ON AN AUDIO SIGNAL |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588966A (en) * | 2004-09-27 | 2005-03-02 | 新太科技股份有限公司 | Method for detecting ADSC line parameter |
| CN104571189A (en) * | 2015-01-09 | 2015-04-29 | 西安交通大学 | Blow molding equipment intelligent temperature control system and method based on DSP and FPGA |
| CN206274366U (en) * | 2016-10-26 | 2017-06-23 | 中国船舶重工集团公司第七二六研究所 | Self-adapting multi-channel power supply real-time monitoring circuit system |
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