Gate drive circuit
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit for a display panel.
Background
In the existing display panel structure, a gate driver on array (GOA) technology can be used to fabricate a gate driving circuit in a non-display area of the display panel to replace a conventional external driving chip, which not only can improve productivity and reduce product cost, but also can reduce the frame width of the display panel and realize the aesthetic design of a narrow frame.
In a conventional gate driving circuit structure, a gate driving signal output from a gate driving unit of a current stage is simultaneously used as a reset signal (reset signal) of a gate driving unit of a previous stage and as a trigger signal of a gate driving unit of a next stage. Therefore, if any one of the gate driving units is disconnected, the gate driving signal output from the gate driving unit of the previous stage and the gate driving signal output from the gate driving unit of the next stage are simultaneously affected, resulting in abnormal display.
Therefore, it is necessary to provide a gate driving circuit to solve the above problems.
Disclosure of Invention
The present invention is directed to a gate driving circuit, which can detect and compensate a gate driving signal in real time, thereby ensuring normal display of a display panel.
In order to achieve the aim, the invention provides a gate driving circuit which is characterized by comprising a detection compensation circuit, a control circuit and a control circuit, wherein the detection compensation circuit comprises a plurality of switch circuits and a control chip, and the control chip comprises a first detection input end, a second detection input end and a compensation signal output end; and a plurality of cascaded gate driving units, wherein the gate driving units include a control terminal for outputting a gate control signal, a clock signal input terminal for receiving a clock signal, and a driving signal output terminal for outputting a gate driving signal according to the gate control signal and the clock signal, the control terminal is connected to the first detection input terminal through a corresponding switch circuit, the clock signal input terminal is connected to the second detection input terminal through a corresponding switch circuit, and the driving signal output terminal is connected to the compensation signal output terminal through a corresponding switch circuit; for the gate driving unit of the current stage, after the first detection input end and the second detection input end of the control chip respectively receive the gate control signal and the clock signal, but the clock signal is not used for outputting the clock signal of the gate driving signal, the compensation signal output end of the control chip outputs a compensation signal to the gate driving unit of the next stage.
In some embodiments, the gate driving circuit further includes a plurality of clock signal lines, wherein the clock signal input terminal of the gate driving unit is connected to the control chip through the corresponding clock signal line.
In some embodiments, the gate driving unit further comprises a trigger signal input for receiving a trigger signal.
In some embodiments, the driving signal output terminal is connected to a trigger signal input terminal of the gate driving unit of the next stage.
In some embodiments, for the gate driving unit of the present stage, when the first detection input terminal and the second detection input terminal of the control chip receive the gate control signal and the clock signal respectively, but the clock signal is not a clock signal for outputting the gate driving signal, the trigger signal input terminal of the gate driving unit of the next stage receives the compensation signal.
In some embodiments, the switch circuit includes a first transistor, a second transistor, and a third transistor, wherein a source and a drain of the first transistor are connected to the first detection input terminal and the control terminal, respectively, a source and a drain of the second transistor are connected to the second detection input terminal and the clock signal input terminal, respectively, a source and a drain of the third transistor are connected to the compensation signal output terminal and the driving signal output terminal, respectively, and a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to the trigger signal input terminal.
In some embodiments, the gate driving unit includes a fourth transistor and a fifth transistor, a source and a drain of the fourth transistor are respectively connected to the clock signal input terminal and the driving signal output terminal, a source and a gate of the fifth transistor are connected to the trigger signal input terminal, and a gate of the fourth transistor and a drain of the fifth transistor are connected to the control terminal.
In some embodiments, the drain of the third transistor and the drain of the fourth transistor are connected to the driving signal output terminal.
In some embodiments, the drain of the second transistor and the source of the fourth transistor are connected to the clock signal input terminal.
In some embodiments, the drain of the first transistor, the gate of the fourth transistor, and the drain of the fifth transistor are connected to the control terminal.
In order to make the features and technical contents of the present invention comprehensible, please refer to the following detailed description of the present invention and the accompanying drawings, which are provided for reference and not for limiting the present invention.
Drawings
FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram according to the embodiment shown in fig. 1.
Detailed Description
In order to make the objects, technical means and effects of the present invention more clear and definite, the present invention will be further explained with reference to the accompanying drawings. It is to be understood that the embodiments described herein are only a few embodiments of the present invention, not all embodiments, and are not intended to limit the present invention.
Referring to fig. 1, a functional block diagram of a gate driving circuit according to an embodiment of the invention is shown. The gate driving circuit 1 includes a detection compensation circuit and a plurality of gate driving units GOA1, GOA3 connected in cascade. The detection compensation circuit includes a plurality of switching circuits 10 and a control chip 11. The control chip 11 includes a first detection input 111, a second detection input 112, and a compensation signal output 113.
The gate driving units GOA1, GOA3 include a control terminal 120 for outputting gate control signals GC1, GC3, a clock signal input terminal 121 for receiving clock signals CK1, CK3, and a driving signal output terminal 122 for outputting gate driving signals Out1, Out3 according to the gate control signals GC1, GC3 and the clock signals CK1, CK 3. As shown in fig. 1, the control terminals 120 of the gate driving units GOA1 and GOA3 are connected to the first detection input terminal 111 of the control chip 11 through the corresponding switch circuits 10, the clock signal input terminals 121 of the gate driving units GOA1 and GOA3 are connected to the second detection input terminal 112 of the control chip 11 through the corresponding switch circuits 10, and the driving signal output terminals 122 of the gate driving units GOA1 and GOA3 are connected to the compensation signal output terminal 113 of the control chip 11 through the corresponding switch circuits 10. In the present embodiment, the gate driving circuit 1 further includes a plurality of clock signal lines 13. The clock signal input terminals 121 of the gate driving units GOA1 and GOA3 are connected to the control chip 11 through corresponding clock signal lines 13. Furthermore, the gate driving units GOA1 and GOA3 further include a trigger signal input terminal 123 for receiving a trigger signal. The driving signal output terminal 122 of the gate driving unit GOA1 is connected to the trigger signal input terminal 123 of the next gate driving unit GOA 3. For example, the trigger signal input terminal 123 of the gate driving unit GOA1 is used for receiving an external trigger signal ST, and the trigger signal received by the trigger signal input terminal 123 of the gate driving unit GOA3 is the gate driving signal Out1 of the gate driving unit GOA 1.
For example, with the gate driving unit GOA1 as the gate driving unit of the present stage, when the first detection input terminal 111 and the second detection input terminal 112 of the control chip 11 receive the gate control signal GC1 and the clock signal CK1, respectively, but the clock signal CK1 is not the clock signal for outputting the gate driving signal Out1, the compensation signal output terminal 113 of the control chip 11 outputs the compensation signal Out 1' to the gate driving unit GOA3 of the next stage. That is, the trigger signal input terminal 123 of the gate driving unit GOA3 of the next stage receives the compensation signal Out 1'. Therefore, the gate driving circuit 1 of the present invention can detect whether the gate driving signals Out1 and Out3 of the gate driving units GOA1 and GOA3 are abnormal in real time, and compensate the abnormal gate driving signals, thereby ensuring the normal display of the display panel.
Referring to fig. 2, a circuit structure diagram according to the embodiment shown in fig. 1 is shown. In the present embodiment, the switch circuit 10 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. A source and a drain of the first transistor Q1 are connected to the first detection input terminal 111 and the control terminal 120, respectively, a source and a drain of the second transistor Q2 are connected to the second detection input terminal 112 and the clock signal input terminal 121, respectively, a source and a drain of the third transistor Q3 are connected to the compensation signal output terminal 113 and the driving signal output terminal 122, respectively, and a gate of the first transistor Q1, a gate of the second transistor Q2, and a gate of the third transistor Q3 are connected to the trigger signal input terminal 123.
The gate driving units GOA1, GOA3 include a fourth transistor Q4 and a fifth transistor Q5. In the present embodiment, the source and the drain of the fourth transistor Q4 are connected to the clock signal input terminal 121 and the driving signal output terminal 122, respectively, the source and the gate of the fifth transistor Q5 are connected to the trigger signal input terminal 123, and the gate of the fourth transistor Q4 and the drain of the fifth transistor Q5 are connected to the control terminal 120.
Further, as shown in fig. 2, the drain of the third transistor Q3 and the drain of the fourth transistor Q4 are connected to the driving signal output terminal 122. The drain of the second transistor Q2 and the source of the fourth transistor Q4 are connected to the clock signal input terminal 121. The drain of the first transistor Q1, the gate of the fourth transistor Q4, and the drain of the fifth transistor Q5 are connected to the control terminal 120.
In summary, the gate driving circuit provided by the present invention, when the gate driving signal of the gate driving unit is abnormal, the abnormal gate driving signal is detected in real time by the detection and compensation circuit and compensated, so as to ensure the normal display of the display panel.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.