CN110047420B - Gate drive circuit - Google Patents
Gate drive circuit Download PDFInfo
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- CN110047420B CN110047420B CN201910359642.3A CN201910359642A CN110047420B CN 110047420 B CN110047420 B CN 110047420B CN 201910359642 A CN201910359642 A CN 201910359642A CN 110047420 B CN110047420 B CN 110047420B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
A gate driving circuit includes a detection compensation circuit and a gate driving unit cascaded. The detection compensation circuit comprises a switch circuit and a control chip, and the control chip comprises a first detection input end, a second detection input end and a compensation signal output end. The grid driving unit comprises a control end, a clock signal input end and a driving signal output end, the control end is connected with the first detection input end through a corresponding switch circuit, the clock signal input end is connected with the second detection input end through a corresponding switch circuit, and the driving signal output end is connected with the compensation signal output end through a corresponding switch circuit. For the gate driving unit of the current stage, when the first detection input end and the second detection input end of the control chip respectively receive the gate control signal and the clock signal, but the clock signal is not used for outputting the clock signal of the gate driving signal, the compensation signal output end of the control chip outputs the compensation signal to the gate driving unit of the next stage.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit for a display panel.
Background
In the existing display panel structure, a gate driver on array (GOA) technology can be used to fabricate a gate driving circuit in a non-display area of the display panel to replace a conventional external driving chip, which not only can improve productivity and reduce product cost, but also can reduce the frame width of the display panel and realize the aesthetic design of a narrow frame.
In a conventional gate driving circuit structure, a gate driving signal output from a gate driving unit of a current stage is simultaneously used as a reset signal (reset signal) of a gate driving unit of a previous stage and as a trigger signal of a gate driving unit of a next stage. Therefore, if any one of the gate driving units is disconnected, the gate driving signal output from the gate driving unit of the previous stage and the gate driving signal output from the gate driving unit of the next stage are simultaneously affected, resulting in abnormal display.
Therefore, it is necessary to provide a gate driving circuit to solve the above problems.
Disclosure of Invention
The present invention is directed to a gate driving circuit, which can detect and compensate a gate driving signal in real time, thereby ensuring normal display of a display panel.
In order to achieve the aim, the invention provides a gate driving circuit which is characterized by comprising a detection compensation circuit, a control circuit and a control circuit, wherein the detection compensation circuit comprises a plurality of switch circuits and a control chip, and the control chip comprises a first detection input end, a second detection input end and a compensation signal output end; and a plurality of cascaded gate driving units, wherein the gate driving units include a control terminal for outputting a gate control signal, a clock signal input terminal for receiving a clock signal, and a driving signal output terminal for outputting a gate driving signal according to the gate control signal and the clock signal, the control terminal is connected to the first detection input terminal through a corresponding switch circuit, the clock signal input terminal is connected to the second detection input terminal through a corresponding switch circuit, and the driving signal output terminal is connected to the compensation signal output terminal through a corresponding switch circuit; for the gate driving unit of the current stage, after the first detection input end and the second detection input end of the control chip respectively receive the gate control signal and the clock signal, but the clock signal is not used for outputting the clock signal of the gate driving signal, the compensation signal output end of the control chip outputs a compensation signal to the gate driving unit of the next stage.
In some embodiments, the gate driving circuit further includes a plurality of clock signal lines, wherein the clock signal input terminal of the gate driving unit is connected to the control chip through the corresponding clock signal line.
In some embodiments, the gate driving unit further comprises a trigger signal input for receiving a trigger signal.
In some embodiments, the driving signal output terminal is connected to a trigger signal input terminal of the gate driving unit of the next stage.
In some embodiments, for the gate driving unit of the present stage, when the first detection input terminal and the second detection input terminal of the control chip receive the gate control signal and the clock signal respectively, but the clock signal is not a clock signal for outputting the gate driving signal, the trigger signal input terminal of the gate driving unit of the next stage receives the compensation signal.
In some embodiments, the switch circuit includes a first transistor, a second transistor, and a third transistor, wherein a source and a drain of the first transistor are connected to the first detection input terminal and the control terminal, respectively, a source and a drain of the second transistor are connected to the second detection input terminal and the clock signal input terminal, respectively, a source and a drain of the third transistor are connected to the compensation signal output terminal and the driving signal output terminal, respectively, and a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to the trigger signal input terminal.
In some embodiments, the gate driving unit includes a fourth transistor and a fifth transistor, a source and a drain of the fourth transistor are respectively connected to the clock signal input terminal and the driving signal output terminal, a source and a gate of the fifth transistor are connected to the trigger signal input terminal, and a gate of the fourth transistor and a drain of the fifth transistor are connected to the control terminal.
In some embodiments, the drain of the third transistor and the drain of the fourth transistor are connected to the driving signal output terminal.
In some embodiments, the drain of the second transistor and the source of the fourth transistor are connected to the clock signal input terminal.
In some embodiments, the drain of the first transistor, the gate of the fourth transistor, and the drain of the fifth transistor are connected to the control terminal.
In order to make the features and technical contents of the present invention comprehensible, please refer to the following detailed description of the present invention and the accompanying drawings, which are provided for reference and not for limiting the present invention.
Drawings
FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram according to the embodiment shown in fig. 1.
Detailed Description
In order to make the objects, technical means and effects of the present invention more clear and definite, the present invention will be further explained with reference to the accompanying drawings. It is to be understood that the embodiments described herein are only a few embodiments of the present invention, not all embodiments, and are not intended to limit the present invention.
Referring to fig. 1, a functional block diagram of a gate driving circuit according to an embodiment of the invention is shown. The gate driving circuit 1 includes a detection compensation circuit and a plurality of gate driving units GOA1, GOA3 connected in cascade. The detection compensation circuit includes a plurality of switching circuits 10 and a control chip 11. The control chip 11 includes a first detection input 111, a second detection input 112, and a compensation signal output 113.
The gate driving units GOA1, GOA3 include a control terminal 120 for outputting gate control signals GC1, GC3, a clock signal input terminal 121 for receiving clock signals CK1, CK3, and a driving signal output terminal 122 for outputting gate driving signals Out1, Out3 according to the gate control signals GC1, GC3 and the clock signals CK1, CK 3. As shown in fig. 1, the control terminals 120 of the gate driving units GOA1 and GOA3 are connected to the first detection input terminal 111 of the control chip 11 through the corresponding switch circuits 10, the clock signal input terminals 121 of the gate driving units GOA1 and GOA3 are connected to the second detection input terminal 112 of the control chip 11 through the corresponding switch circuits 10, and the driving signal output terminals 122 of the gate driving units GOA1 and GOA3 are connected to the compensation signal output terminal 113 of the control chip 11 through the corresponding switch circuits 10. In the present embodiment, the gate driving circuit 1 further includes a plurality of clock signal lines 13. The clock signal input terminals 121 of the gate driving units GOA1 and GOA3 are connected to the control chip 11 through corresponding clock signal lines 13. Furthermore, the gate driving units GOA1 and GOA3 further include a trigger signal input terminal 123 for receiving a trigger signal. The driving signal output terminal 122 of the gate driving unit GOA1 is connected to the trigger signal input terminal 123 of the next gate driving unit GOA 3. For example, the trigger signal input terminal 123 of the gate driving unit GOA1 is used for receiving an external trigger signal ST, and the trigger signal received by the trigger signal input terminal 123 of the gate driving unit GOA3 is the gate driving signal Out1 of the gate driving unit GOA 1.
For example, with the gate driving unit GOA1 as the gate driving unit of the present stage, when the first detection input terminal 111 and the second detection input terminal 112 of the control chip 11 receive the gate control signal GC1 and the clock signal CK1, respectively, but the clock signal CK1 is not the clock signal for outputting the gate driving signal Out1, the compensation signal output terminal 113 of the control chip 11 outputs the compensation signal Out 1' to the gate driving unit GOA3 of the next stage. That is, the trigger signal input terminal 123 of the gate driving unit GOA3 of the next stage receives the compensation signal Out 1'. Therefore, the gate driving circuit 1 of the present invention can detect whether the gate driving signals Out1 and Out3 of the gate driving units GOA1 and GOA3 are abnormal in real time, and compensate the abnormal gate driving signals, thereby ensuring the normal display of the display panel.
Referring to fig. 2, a circuit structure diagram according to the embodiment shown in fig. 1 is shown. In the present embodiment, the switch circuit 10 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. A source and a drain of the first transistor Q1 are connected to the first detection input terminal 111 and the control terminal 120, respectively, a source and a drain of the second transistor Q2 are connected to the second detection input terminal 112 and the clock signal input terminal 121, respectively, a source and a drain of the third transistor Q3 are connected to the compensation signal output terminal 113 and the driving signal output terminal 122, respectively, and a gate of the first transistor Q1, a gate of the second transistor Q2, and a gate of the third transistor Q3 are connected to the trigger signal input terminal 123.
The gate driving units GOA1, GOA3 include a fourth transistor Q4 and a fifth transistor Q5. In the present embodiment, the source and the drain of the fourth transistor Q4 are connected to the clock signal input terminal 121 and the driving signal output terminal 122, respectively, the source and the gate of the fifth transistor Q5 are connected to the trigger signal input terminal 123, and the gate of the fourth transistor Q4 and the drain of the fifth transistor Q5 are connected to the control terminal 120.
Further, as shown in fig. 2, the drain of the third transistor Q3 and the drain of the fourth transistor Q4 are connected to the driving signal output terminal 122. The drain of the second transistor Q2 and the source of the fourth transistor Q4 are connected to the clock signal input terminal 121. The drain of the first transistor Q1, the gate of the fourth transistor Q4, and the drain of the fifth transistor Q5 are connected to the control terminal 120.
In summary, the gate driving circuit provided by the present invention, when the gate driving signal of the gate driving unit is abnormal, the abnormal gate driving signal is detected in real time by the detection and compensation circuit and compensated, so as to ensure the normal display of the display panel.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (8)
1. A gate drive circuit, comprising:
the detection compensation circuit comprises a plurality of switch circuits and a control chip, wherein the control chip comprises a first detection input end, a second detection input end and a compensation signal output end; and
a plurality of cascaded gate driving units, wherein the gate driving units include a control terminal for outputting a gate control signal, a clock signal input terminal for receiving a clock signal, a driving signal output terminal for outputting a gate driving signal according to the gate control signal and the clock signal, and a trigger signal input terminal for receiving a trigger signal, the control terminal is connected to the first detection input terminal through a corresponding switch circuit, the clock signal input terminal is connected to the second detection input terminal through a corresponding switch circuit, and the driving signal output terminal is connected to the compensation signal output terminal through a corresponding switch circuit; wherein,
for the gate driving unit of the current stage, when the first detection input end and the second detection input end of the control chip respectively receive the gate control signal and the clock signal, but the clock signal is not used for outputting the clock signal of the gate driving signal, the compensation signal output end of the control chip outputs a compensation signal to the gate driving unit of the next stage;
the switch circuit comprises a first transistor, a second transistor and a third transistor, wherein a source electrode and a drain electrode of the first transistor are respectively connected with the first detection input end and the control end, a source electrode and a drain electrode of the second transistor are respectively connected with the second detection input end and the clock signal input end, a source electrode and a drain electrode of the third transistor are respectively connected with the compensation signal output end and the driving signal output end, and a grid electrode of the first transistor, a grid electrode of the second transistor and a grid electrode of the third transistor are connected with the trigger signal input end.
2. The gate driving circuit of claim 1, further comprising a plurality of clock signal lines, wherein the clock signal input terminals of the gate driving units are connected to the control chip through the respective clock signal lines.
3. A gate drive circuit as claimed in claim 1, wherein the drive signal output terminal is connected to a trigger signal input terminal of the gate drive unit of the next stage.
4. The gate driving circuit according to claim 1, wherein for the gate driving unit of the current stage, when the first detection input terminal and the second detection input terminal of the control chip receive the gate control signal and the clock signal respectively, but the clock signal is not a clock signal for outputting the gate driving signal, the trigger signal input terminal of the gate driving unit of the next stage receives the compensation signal.
5. The gate driving circuit according to claim 1, wherein the gate driving unit includes a fourth transistor and a fifth transistor, a source and a drain of the fourth transistor are connected to the clock signal input terminal and the driving signal output terminal, respectively, a source and a gate of the fifth transistor are connected to the trigger signal input terminal, and a gate of the fourth transistor and a drain of the fifth transistor are connected to the control terminal.
6. The gate drive circuit according to claim 5, wherein a drain of the third transistor and a drain of the fourth transistor are connected to the drive signal output terminal.
7. A gate drive circuit as claimed in claim 5, wherein the drain of the second transistor and the source of the fourth transistor are connected to the clock signal input terminal.
8. A gate drive circuit as claimed in claim 5, wherein the drain of the first transistor, the gate of the fourth transistor and the drain of the fifth transistor are connected to the control terminal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910359642.3A CN110047420B (en) | 2019-04-30 | 2019-04-30 | Gate drive circuit |
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| CN201910359642.3A CN110047420B (en) | 2019-04-30 | 2019-04-30 | Gate drive circuit |
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| CN110047420A CN110047420A (en) | 2019-07-23 |
| CN110047420B true CN110047420B (en) | 2022-04-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060082128A (en) * | 2005-01-11 | 2006-07-14 | 삼성전자주식회사 | Substrate for display panel |
| CN106448522A (en) * | 2016-10-20 | 2017-02-22 | 京东方科技集团股份有限公司 | Detection circuit, gate drive circuit and display panel |
| CN108831360A (en) * | 2018-06-22 | 2018-11-16 | 京东方科技集团股份有限公司 | Gate drive signal detection circuit, method and display device |
| CN109147690A (en) * | 2018-08-24 | 2019-01-04 | 惠科股份有限公司 | Control method and device and controller |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI424401B (en) * | 2009-11-02 | 2014-01-21 | Chunghwa Picture Tubes Ltd | Display and gate driver circuit thereof |
| KR102290915B1 (en) * | 2014-12-18 | 2021-08-19 | 삼성디스플레이 주식회사 | Gate driver and display apparatus having them |
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- 2019-04-30 CN CN201910359642.3A patent/CN110047420B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060082128A (en) * | 2005-01-11 | 2006-07-14 | 삼성전자주식회사 | Substrate for display panel |
| CN106448522A (en) * | 2016-10-20 | 2017-02-22 | 京东方科技集团股份有限公司 | Detection circuit, gate drive circuit and display panel |
| CN108831360A (en) * | 2018-06-22 | 2018-11-16 | 京东方科技集团股份有限公司 | Gate drive signal detection circuit, method and display device |
| CN109147690A (en) * | 2018-08-24 | 2019-01-04 | 惠科股份有限公司 | Control method and device and controller |
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| CN110047420A (en) | 2019-07-23 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Denomination of invention: gate drive circuit Effective date of registration: 20231113 Granted publication date: 20220401 Pledgee: Industrial and Commercial Bank of China Limited Shenzhen Guangming Sub branch Pledgor: TCL China Star Optoelectronics Technology Co.,Ltd. Registration number: Y2023980065368 |