CN110046875A - A kind of siacoin digs the hardware implementation method and device of mine algorithm - Google Patents
A kind of siacoin digs the hardware implementation method and device of mine algorithm Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
- G06F7/4833—Logarithmic number system
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- G—PHYSICS
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- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/04—Payment circuits
- G06Q20/06—Private payment circuits, e.g. involving electronic currency used among participants of a common payment scheme
- G06Q20/065—Private payment circuits, e.g. involving electronic currency used among participants of a common payment scheme using e-cash
Abstract
The present invention relates to ideal moneys to dig mine technical field, disclose the hardware implementation method and device of a kind of siacoin digging mine algorithm, by obtaining the input data of 80 bytes, and the input data is input in the first register of 10 64 bit bit wides according to one group of 64 bit；Every 4 the second registers and 2 third registers are divided into one group, is separately input into corresponding logic calculation module and carries out logical operation, to obtain the logic calculation value of 16 64 bits；When the numerical value of counter is less than 48, selector is according to the numerical value of counter, selection output is carried out to the numerical value in the logic calculation value and the first register of current 16 64 bits, to obtain the input value of 16 new second registers and the input value of 8 third registers, and continue iteration execution；When the numerical value of counter is equal to 48, final result is calculated according to the logic calculation value of current 16 64 bits.The present invention siacoin that GPU video card is realized compared to the prior art digs mine algorithm, calculates Li Genggao, power consumption is lower.
Description
Technical field
Mine technical field is dug the present invention relates to ideal money more particularly to a kind of siacoin digs the hardware realization of mine algorithm
Method and device.
Background technique
Siacoin is a kind of virtual digital cash, using the digging mine algorithm of POW (proofofwork).POW digs mine and calculates
Method focuses on, and within the unit time, calculation power is higher, and the ideal money of acquisition is more, and power consumption is smaller, and the electricity charge of cost are got over
Few, then the income obtained is more.
The mainstream equipment of the digging siacoin of the prior art is GPU video card, and calculation power is not high, and about 1GHash/s is that is, per second complete
At the operation of 1G siacoin algorithm defined, power consumption is larger, about 135W, waste of energy.
Summary of the invention
The present invention provides the hardware implementation method and device of a kind of siacoin digging mine algorithm, and mine is dug in solution in the prior art
The technical issues of equipment calculation power is not high, power consumption is larger, waste of energy.
The purpose of the present invention is what is be achieved through the following technical solutions:
A kind of siacoin digs the hardware implementation method of mine algorithm, comprising:
Step S1, the input data of 80 bytes is obtained, and the input data is input to 10 for one group according to 64 bit
In first register of 64 bit bit wides, wherein first register number is 16, and preceding 10 first registers are used
In storage input data, the numerical value that rear 6 first registers store is zero；
Step S2, every 4 the second registers and 2 third registers are divided into one group, are separately input into corresponding logic
Logical operation is carried out in computing module, to obtain the logic calculation value of 16 64 bits, wherein the quantity of the second register is 16
A, bit wide is 64 bits, and the quantity of third register is 8, and bit wide is 64 bits；
Step S3, when the numerical value of counter is less than 48, selector is according to the numerical value of counter, to current 16 64 bits
Logic calculation value and the first register in numerical value carry out selection output, to obtain the defeated of 16 new second registers
Enter the input value of value and 8 third registers, and the S2 that gos to step is continued to execute, wherein the counter is each
Clock cycle increases by 1；
Step S4, it when the numerical value of counter is equal to 48, is calculated most according to the logic calculation value of current 16 64 bits
Terminate fruit.
A kind of siacoin digs the hardware realization apparatus of mine algorithm, comprising: the first register, the second register, third deposit
Device, counter, output module, logic calculation module and selector, wherein
First register number is 16, and preceding 10 first registers are for storing input data, rear 6 institutes
The numerical value for stating the storage of the first register is zero；
The quantity of second register is 16, and bit wide is 64 bits, and the quantity of third register is 8, and bit wide is
64 bits；Every 4 the second registers and 2 third registers are divided into one group, and input connects with corresponding logic calculation module respectively
It connects；
The quantity of the logic calculation module is 4, and the logic calculation module is used for according to every 4 the second registers and 2
The storing data of a third register carries out logical operation, to obtain the logic calculation value of 16 64 bits；
The counter, for increasing by 1 in each clock cycle；
The selector, for according to the numerical value of counter, comparing current 16 64 when the numerical value of counter is less than 48
Numerical value in special logic calculation value and the first register carries out selection output, to obtain 16 new second registers
The input value of input value and 8 third registers；When the numerical value of counter is equal to 48, according to current 16 64 bits
Logic calculation value calculates final result, and is sent to the output module.
The present invention provides the hardware implementation method and device of a kind of siacoin digging mine algorithm, passes through and obtains the defeated of 80 bytes
Enter data, and the input data is input in the first register of 10 64 bit bit wides according to one group of 64 bit；By every 4
A second register and 2 third registers are divided into one group, are separately input into progress logic fortune in corresponding logic calculation module
It calculates, to obtain the logic calculation value of 16 64 bits；When the numerical value of counter is less than 48, selector is according to the number of counter
Value, carries out selection output to the numerical value in the logic calculation value and the first register of current 16 64 bits, to obtain new 16
The input value of a second register and the input value of 8 third registers, and continue iteration execution；When counter
When numerical value is equal to 48, final result is calculated according to the logic calculation value of current 16 64 bits.The present invention is compared with prior art
The siacoin that middle GPU video card is realized digs mine algorithm, calculates Li Genggao, and power consumption is lower.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without any creative labor, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the flow chart that a kind of siacoin of the embodiment of the present invention digs the hardware implementation method of mine algorithm；
Fig. 2 is the structure chart that a kind of siacoin of the embodiment of the present invention digs the hardware realization apparatus of mine algorithm.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
As shown in Figure 1, for a kind of hardware implementation method process of siacoin digging mine algorithm provided in an embodiment of the present invention
Figure, comprising:
Step S1, the input data of 80 bytes is obtained, and the input data is input to 10 for one group according to 64 bit
In first register of 64 bit bit wides；
Wherein, first register number is 16, and respectively m0 to m15, m0 to m9 are used to store input data,
The numerical value that m10 to m15 is stored is that zero, m0 to m15 is number to the first register, and being applied not only to marker register also can be used
In the data for indicating to store in the register；
Step S2, every 4 the second registers and 2 third registers are divided into one group, are separately input into corresponding logic
Logical operation is carried out in computing module, to obtain the logic calculation value of 16 64 bits；
Wherein, the quantity of the second register is 16, and bit wide is 64 bits, and the quantity of third register is 8, and bit wide is
64 bits；
Step S2 specifically can also include:
Step S2-1, by the data of a, b, c, d and 2 third registers of the data storage of every 4 the second registers storage
M0, m1 points are one group；
Step S2-2, it calculates every group of intermediate result a_r, b_r, c_r, d_r and is stored in temporary register, wherein a_r
=a+b+m0, d_r=(d^a_r) > > 32 (recycling of the result of d or a_r moves to right 32bit), c_r=c+d_r, b_r=(c_r
^b) > > 24 (recycling of the result of d or a_r moves to right 24bit)；
Step S2-3, according to every group of intermediate result a_r, b_r, c_r, d_r, patrolling for every group of 4 64 bits is calculated
Volume calculated value, a_o=a_r+b_r+m1, d_o=(d_r^a_o) > > 16, c_o=c_r+d_o, b_o=(c_o^b_r) > > 63.
Step S3, when the numerical value of counter is less than 48, selector is according to the numerical value of counter, to current 16 64 bits
Logic calculation value and the first register in numerical value carry out selection output, to obtain the defeated of 16 new second registers
Enter the input value of value and 8 third registers, and the S2 that gos to step is continued to execute；
Wherein, the counter increases by 1 in each clock cycle；
When calculating just beginning, the value of first time is that (there are no the logic calculations for calculating 16 64 bits at this time for default value
Value after 2 clock cycle, when counter was 2 moment, can just calculate the logic calculation of 16 64 bits of the first round
Value), therefore, when the numerical value of counter is equal to 0 or 1, input value gf_i0, gf_i1 of 16 new second registers,
gf_i2、gf_i3、gf_i4、gf_i5、gf_i6、gf_i7、gf_i8、gf_i9、gf_i10、gf_i11、gf_i12、gf_i13、
Input value G_m0, G_m1, G_m2, G_m3, G_m4, G_m5, G_m6, G_ of gf_i14, gf_i15 and 8 third registers
M7 is default value, wherein
Gf_i0=64'h6A09E667F3BCC908^ { 32'h0,32'h01010000 } ^64'h20；
Gf_i4=64'hBB67AE8584CAA73B；
Gf_i8=64'h3C6EF372FE94F82B；
Gf_i12=64'hA54FF53A5F1D36F1；
Gf_i1=64'h510E527FADE682D1；
Gf_i5=64'h9B05688C2B3E6C1F；
Gf_i9=64'h1F83D9ABFB41BD6B；
Gf_i13=64'h5BE0CD19137E2179；
Gf_i2=64'h6A09E667F3BCC908；
Gf_i6=64'hBB67AE8584CAA73B；
Gf_i10=64'h3C6EF372FE94F82B；
Gf_i14=64'hA54FF53A5F1D36F1；
Gf_i3=64'h510E527FADE682D1^64 ' h50；
Gf_i7=64'h9B05688C2B3E6C1F；
Gf_i11=~(64'h1F83D9ABFB41BD6B) step-by-step negates；
Gf_i15=64'h5BE0CD19137E2179；
G_m0=m0；
G_m1=m1；
G_m2=m2；
G_m3=m3；
G_m4=m4；
G_m5=m5；
G_m6=m6；
G_m7=m7.
When counter numerical value be 2,3,6,7,10,11,14,15,18,19,22,23,26,27,30,31,34,35,38,
39,42,43,46,47 when, input value gf_i0=gf_o0, gf_i1=gf_o5, gf_i2=of 16 second registers
Gf_o10, gf_i3=gf_o15, gf_i4=gf_o4, gf_i5=gf_o9, gf_i6=gf_o14, gf_i7=gf_o3, gf_
I8=gf_o8, gf_i9=gf_o13, gf_i10=gf_o2, gf_i11=gf_o7, gf_i12=gf_o12, gf_i13=
Gf_o1, gf_i14=gf_o6, gf_i15=gf_o11, and the S2 that gos to step continues to execute the iteration for preparing next round；
When counter be 4,5,8,9,12,14,16,17,20,21,24,25,28,29,32,33,36,37,40,41,44,
When 45, input value gf_i0=gf_o0, gf_i1=gf_o13, gf_i2=gf_o10, gf_i3 of 16 second registers
=gf_o7, gf_i4=gf_o4, gf_i5=gf_o1, gf_i6=gf_o14, gf_i7=gf_o11, gf_i8=gf_o8,
Gf_i9=gf_o5, gf_i10=gf_o2, gf_i11=gf_o15, gf_i12=gf_o12, gf_i13=gf_o9, gf_i14
=gf_o6, gf_i15=gf_o3, and the S2 that gos to step continues to execute the iteration for preparing next round；
Wherein, gf_o0, gf_o1, gf_o2, gf_o3, gf_o4, gf_o5, gf_o6, gf_o7, gf_o8, gf_o9, gf_
O10, gf_o11, gf_o12, gf_o13, gf_o14, gf_o15 are the logic calculation value of 16 64 bits obtained in step S2；
The installation of the input value of 8 third registers such as under type obtains:
When the numerical value of counter is 2,3,42,43, the value of the input value G_m0 to G_m7 of 8 third registers
It is respectively as follows: m8~m15；
When the numerical value of counter is 4,5,44,45, the value of the input value G_m0 to G_m7 of 8 third registers
Respectively m14, m10, m4, m8, m9, m15, m13, m6；
When the numerical value of counter is 6,7,46,47, the value of the input value G_m0 to G_m7 of 8 third registers
Respectively m1, m12, m0, m2, m11, m7, m5, m3；
When the numerical value of counter is 8,9, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m11,m8,m12,m0,m5,m2,m15,m13；
When the numerical value of counter is 10,11, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m10, m14, m3, m6, m7, m1, m9, m4；
When the numerical value of counter is 12,13, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m7, m9, m3, m1, m13, m12, m11, m14；
When the numerical value of counter is 14,15, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m2, m6, m5, m10, m4, m0, m15, m8；
When the numerical value of counter is 16,17, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m9, m0, m5, m7, m2, m4, m10, m15；
When the numerical value of counter is 18,19, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m14, m1, m11, m12, m6, m8, m3, m13；
When the numerical value of counter is 20,21, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m2, m12, m6, m10, m0, m11, m8, m3；
When the numerical value of counter is 22,23, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m4, m13, m7, m5, m15, m14, m1, m9；
When the numerical value of counter is 24,25, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m12, m5, m1, m15, m14, m13, m4, m10；
When the numerical value of counter is 26,27, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m0, m7, m6, m3, m9, m2, m8, m11；
When the numerical value of counter is 28,29, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m13, m11, m7, m14, m12, m1, m3, m9；
When the numerical value of counter is 30,31, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m5, m0, m15, m4, m8, m6, m2, m10；
When the numerical value of counter is 32,33, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m6, m15, m14, m9, m11, m3, m0, m8；
When the numerical value of counter is 34,35, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m12, m2, m13, m7, m1, m4, m10, m5；
When the numerical value of counter is 36,37, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m15, m11, m9, m14, m3, m12, m13, m0；
When the numerical value of counter is 38,39, the value difference of the input value G_m0 to G_m7 of 8 third registers
For c15, c11, c9, c14, c3, c12, c13, c0；
When the numerical value of counter is 40,41, the value difference of the input value G_m0 to G_m7 of 8 third registers
Are as follows: m0~m7.
Step S4, it when the numerical value of counter is equal to 48, is calculated most according to the logic calculation value of current 16 64 bits
Terminate fruit.
Wherein, the logic of current 16 64 bits is obtained when the numerical value of counter is equal to 48 after iterating 12 times
Calculated value gf_o0, gf_o1, gf_o2, gf_o3, gf_o4, gf_o5, gf_o6, gf_o7, gf_o8, gf_o9, gf_o10, gf_
o11,gf_o12,gf_o13,gf_o14,gf_o15；
According to the logic calculation value of current 16 64 bits, calculate 8 64 bits cryptographic Hash Hash0, Hash1,
Hash2, Hash3, Hash4, Hash5, Hash6, Hash7, wherein
Hash0=64'h6A09E667F3BCC908^gf_o0^gf_o10；
Hash1=64'hBB67AE8584CAA73B^gf_o4^gf_o14；
Hash2=64'h3C6EF372FE94F82B^gf_o8^gf_o2；
Hash3=64'hA54FF53A5F1D36F1^gf_o12^gf_o6；
Hash4=64'h510E527FADE682D1^gf_o13^gf_o7；
Hash5=64'h9B05688C2B3E6C1F^gf_o1^gf_o11；
Hash6=64'h1F83D9ABFB41BD6B^gf_o5^gf_o15；
Hash7=64'h5BE0CD19137E2179^gf_o9^gf_o3.
Cryptographic Hash Hash0, Hash1 of 8 final 64 bits, Hash2, Hash3, Hash4, Hash5, Hash6,
The 512bit Hash result of Hash7 composition is final calculated result.
The embodiment of the present invention provides a kind of hardware implementation method of siacoin digging mine algorithm, passes through and obtains the defeated of 80 bytes
Enter data, and the input data is input in the first register of 10 64 bit bit wides according to one group of 64 bit；By every 4
A second register and 2 third registers are divided into one group, are separately input into progress logic fortune in corresponding logic calculation module
It calculates, to obtain the logic calculation value of 16 64 bits；When the numerical value of counter is less than 48, selector is according to the number of counter
Value, carries out selection output to the numerical value in the logic calculation value and the first register of current 16 64 bits, to obtain new 16
The input value of a second register and the input value of 8 third registers, and continue iteration execution；When counter
When numerical value is equal to 48, final result is calculated according to the logic calculation value of current 16 64 bits.The present invention is compared with prior art
The siacoin that middle GPU video card is realized digs mine algorithm, calculates Li Genggao, and power consumption is lower.
The embodiment of the invention also provides the hardware realization apparatus that a kind of siacoin digs mine algorithm, as shown in Figure 2, comprising:
First register 210, the second register 220, third register 230, counter 240, output module 250, logic calculation module
260 and selector 270, wherein
First register number is 16, and preceding 10 first registers are for storing input data, rear 6 institutes
The numerical value for stating the storage of the first register is zero；
The quantity of second register is 16, and bit wide is 64 bits, and the quantity of third register is 8, and bit wide is
64 bits；Every 4 the second registers and 2 third registers are divided into one group, and input connects with corresponding logic calculation module respectively
It connects；
The quantity of the logic calculation module is 4, and the logic calculation module is used for according to every 4 the second registers and 2
The storing data of a third register carries out logical operation, to obtain the logic calculation value of 16 64 bits；
The counter, for increasing by 1 in each clock cycle；
The selector, for according to the numerical value of counter, comparing current 16 64 when the numerical value of counter is less than 48
Numerical value in special logic calculation value and the first register carries out selection output, to obtain 16 new second registers
The input value of input value and 8 third registers；When the numerical value of counter is equal to 48, according to current 16 64 bits
Logic calculation value calculates final result, and is sent to the output module.
Wherein, the logic calculation module includes:
Receiving unit, what a, b, c, d and 2 third registers of data for storing every 4 the second registers stored
M0, m1 points of data are one group；
Temporary register, for calculating every group of intermediate result a_r, b_r, c_r, d_r and storing, wherein a_r=a+
B+m0, d_r=(d^a_r) > > 32, c_r=c+d_r, b_r=(c_r^b) > > 24；
Computing unit, for calculating every group of 4 64 bits according to every group of intermediate result a_r, b_r, c_r, d_r
Logic calculation value, a_o=a_r+b_r+m1, d_o=(d_r^a_o) > > 16, c_o=c_r+d_o, b_o=(c_o^b_r) > >
63。
50 clk cycle of the present apparatus go out a solution, and chip occupying area is small, and dominant frequency is high, and single chip can accommodate largely
The corresponding calculating core of the present apparatus calculates power and is up to 5G Hash/s, and power consumption is only 5W, and GPU video card is realized compared to the prior art
Siacoin digs mine algorithm, calculates Li Genggao, and power consumption is lower.
Through the above description of the embodiments, those skilled in the art can be understood that the present invention can be by
Software adds the mode of required hardware platform to realize, naturally it is also possible to all implemented by hardware, but in many cases before
Person is more preferably embodiment.Based on this understanding, technical solution of the present invention contributes to background technique whole or
Person part can be embodied in the form of software products, which can store in storage medium, such as
ROM/RAM, magnetic disk, CD etc., including some instructions are used so that a computer equipment (can be personal computer, service
Device or the network equipment etc.) execute method described in certain parts of each embodiment of the present invention or embodiment.
The present invention is described in detail above, specific case used herein is to the principle of the present invention and embodiment party
Formula is expounded, and the above description of the embodiment is only used to help understand the method for the present invention and its core ideas；Meanwhile it is right
In those of ordinary skill in the art, according to the thought of the present invention, change is had in specific embodiments and applications
Place, in conclusion the contents of this specification are not to be construed as limiting the invention.
Claims (7)
1. the hardware implementation method that a kind of siacoin digs mine algorithm characterized by comprising
Step S1, the input data of 80 bytes is obtained, and the input data is input to 10 64 ratios according to one group of 64 bit
In first register of special bit wide, wherein it is respectively m0 to m15 that first register number, which is 16, and m0 to m9 is for depositing
Input data is stored up, the numerical value that m10 to m15 is stored is zero；
Step S2, every 4 the second registers and 2 third registers are divided into one group, are separately input into corresponding logic calculation
Logical operation being carried out in module, to obtain the logic calculation value of 16 64 bits, wherein the quantity of the second register is 16,
Bit wide is 64 bits, and the quantity of third register is 8, and bit wide is 64 bits；
Step S3, when the numerical value of counter is less than 48, selector patrols current 16 64 bits according to the numerical value of counter
The numerical value collected in calculated value and the first register carries out selection output, to obtain the input value of 16 new second registers
With the input value of 8 third registers, and the S2 that gos to step is continued to execute, wherein the counter is in each clock
Period increases by 1；
Step S4, it when the numerical value of counter is equal to 48, is calculated according to the logic calculation value of current 16 64 bits and is most terminated
Fruit.
2. the hardware implementation method that siacoin according to claim 1 digs mine algorithm, which is characterized in that step S2 includes:
M0, m1 points of data by a, b, c, d and 2 third register storages of data of every 4 the second registers storage are one group；
It calculates every group of intermediate result a_r, b_r, c_r, d_r and is stored in temporary register, wherein a_r=a+b+m0, d_r
=(d^a_r) > > 32, c_r=c+d_r, b_r=(c_r^b) > > 24；
According to every group of intermediate result a_r, b_r, c_r, d_r, the logic calculation value of every group of 4 64 bits, a_o=are calculated
A_r+b_r+m1, d_o=(d_r^a_o) > > 16, c_o=c_r+d_o, b_o=(c_o^b_r) > > 63.
3. the hardware implementation method that siacoin according to claim 1 digs mine algorithm, which is characterized in that step S3 includes:
When the numerical value of counter is equal to 0 or 1, input value gf_i0, gf_i1 of 16 new second registers, gf_i2,
gf_i3、gf_i4、gf_i5、gf_i6、gf_i7、gf_i8、gf_i9、gf_i10、gf_i11、gf_i12、gf_i13、gf_i14、
Input value G_m0, G_m1, G_m2, G_m3, G_m4, G_m5, G_m6, G_m7 of gf_i15 and 8 third register are pre-
If numerical value, wherein gf_i0=64'h6A09E667F3BCC908^ { 32'h0,32'h01010000 } ^64'h20；
Gf_i4=64'hBB67AE8584CAA73B；
Gf_i8=64'h3C6EF372FE94F82B；
Gf_i12=64'hA54FF53A5F1D36F1；
Gf_i1=64'h510E527FADE682D1；
Gf_i5=64'h9B05688C2B3E6C1F；
Gf_i9=64'h1F83D9ABFB41BD6B；
Gf_i13=64'h5BE0CD19137E2179；
Gf_i2=64'h6A09E667F3BCC908；
Gf_i6=64'hBB67AE8584CAA73B；
Gf_i10=64'h3C6EF372FE94F82B；
Gf_i14=64'hA54FF53A5F1D36F1；
Gf_i3=64'h510E527FADE682D1^64 ' h50；
Gf_i7=64'h9B05688C2B3E6C1F；
Gf_i11=~(64'h1F83D9ABFB41BD6B)；
Gf_i15=64'h5BE0CD19137E2179；
G_m0=m0；
G_m1=m1；
G_m2=m2；
G_m3=m3；
G_m4=m4；
G_m5=m5；
G_m6=m6；
G_m7=m7.
4. the hardware implementation method that siacoin according to claim 1 digs mine algorithm, which is characterized in that step S3 includes:
When counter numerical value be 2,3,6,7,10,11,14,15,18,19,22,23,26,27,30,31,34,35,38,39,
42,43,46,47 when, input value gf_i0=gf_o0, gf_i1=gf_o5, gf_i2=gf_ of 16 second registers
O10, gf_i3=gf_o15, gf_i4=gf_o4, gf_i5=gf_o9, gf_i6=gf_o14, gf_i7=gf_o3, gf_i8
=gf_o8, gf_i9=gf_o13, gf_i10=gf_o2, gf_i11=gf_o7, gf_i12=gf_o12, gf_i13=gf_
O1, gf_i14=gf_o6, gf_i15=gf_o11；
When counter is 4,5,8,9,12,14,16,17,20,21,24,25,28,29,32,33,36,37,40,41,44,45
When, input value gf_i0=gf_o0, gf_i1=gf_o13, gf_i2=gf_o10, gf_i3=of 16 second registers
Gf_o7, gf_i4=gf_o4, gf_i5=gf_o1, gf_i6=gf_o14, gf_i7=gf_o11, gf_i8=gf_o8, gf_
I9=gf_o5, gf_i10=gf_o2, gf_i11=gf_o15, gf_i12=gf_o12, gf_i13=gf_o9, gf_i14=
Gf_o6, gf_i15=gf_o3；
When the numerical value of counter is 2,3,42,43, the value difference of the input value G_m0 to G_m7 of 8 third registers
Are as follows: m8~m15；
When the numerical value of counter is 4,5,44,45, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m14, m10, m4, m8, m9, m15, m13, m6；
When the numerical value of counter is 6,7,46,47, the value difference of the input value G_m0 to G_m7 of 8 third registers
For m1, m12, m0, m2, m11, m7, m5, m3；
When the numerical value of counter be 8,9 when, the value of the input value G_m0 to G_m7 of 8 third registers be respectively m11,
m8,m12,m0,m5,m2,m15,m13；
When the numerical value of counter is 10,11, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m10,m14,m3,m6,m7,m1,m9,m4；
When the numerical value of counter is 12,13, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m7,m9,m3,m1,m13,m12,m11,m14；
When the numerical value of counter is 14,15, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m2,m6,m5,m10,m4,m0,m15,m8；
When the numerical value of counter is 16,17, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m9,m0,m5,m7,m2,m4,m10,m15；
When the numerical value of counter is 18,19, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m14,m1,m11,m12,m6,m8,m3,m13；
When the numerical value of counter is 20,21, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m2,m12,m6,m10,m0,m11,m8,m3；
When the numerical value of counter is 22,23, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m4,m13,m7,m5,m15,m14,m1,m9；
When the numerical value of counter is 24,25, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m12,m5,m1,m15,m14,m13,m4,m10；
When the numerical value of counter is 26,27, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m0,m7,m6,m3,m9,m2,m8,m11；
When the numerical value of counter is 28,29, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m13,m11,m7,m14,m12,m1,m3,m9；
When the numerical value of counter is 30,31, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m5,m0,m15,m4,m8,m6,m2,m10；
When the numerical value of counter is 32,33, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m6,m15,m14,m9,m11,m3,m0,m8；
When the numerical value of counter is 34,35, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m12,m2,m13,m7,m1,m4,m10,m5；
When the numerical value of counter is 36,37, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
m15,m11,m9,m14,m3,m12,m13,m0；
When the numerical value of counter is 38,39, the value of the input value G_m0 to G_m7 of 8 third registers is respectively
c15,c11,c9,c14,c3,c12,c13,c0；
When the numerical value of counter is 40,41, the value of the input value G_m0 to G_m7 of 8 third registers is respectively as follows:
M0~m7；
Wherein, gf_o0, gf_o1, gf_o2, gf_o3, gf_o4, gf_o5, gf_o6, gf_o7, gf_o8, gf_o9, gf_o10,
Gf_o11, gf_o12, gf_o13, gf_o14, gf_o15 are the logic calculation value of 16 64 bits obtained in step S2.
5. the hardware implementation method that siacoin according to claim 1 digs mine algorithm, which is characterized in that step S4 includes:
When the numerical value of counter is equal to 48, obtain logic calculation value gf_o0, gf_o1 of current 16 64 bits, gf_o2,
gf_o3、gf_o4、gf_o5、gf_o6、gf_o7、gf_o8、gf_o9、gf_o10、gf_o11、gf_o12、gf_o13、gf_o14、
gf_o15；
According to the logic calculation value of current 16 64 bits, calculate cryptographic Hash Hash0, Hash1 of 8 64 bits, Hash2,
Hash3, Hash4, Hash5, Hash6, Hash7, wherein
Hash0=64'h6A09E667F3BCC908^gf_o0^gf_o10；
Hash1=64'hBB67AE8584CAA73B^gf_o4^gf_o14；
Hash2=64'h3C6EF372FE94F82B^gf_o8^gf_o2；
Hash3=64'hA54FF53A5F1D36F1^gf_o12^gf_o6；
Hash4=64'h510E527FADE682D1^gf_o13^gf_o7；
Hash5=64'h9B05688C2B3E6C1F^gf_o1^gf_o11；
Hash6=64'h1F83D9ABFB41BD6B^gf_o5^gf_o15；
Hash7=64'h5BE0CD19137E2179^gf_o9^gf_o3.
6. the hardware realization apparatus that a kind of siacoin digs mine algorithm characterized by comprising the first register, the second deposit
Device, third register, counter, output module, logic calculation module and selector, wherein
First register number is 16, and for storing input data, m10 to m15 is deposited by respectively m0 to m15, m0 to m9
The numerical value of storage is zero；；
The quantity of second register is 16, and bit wide is 64 bits, and the quantity of third register is 8, and bit wide is 64 ratios
It is special；Every 4 the second registers and 2 third registers are divided into one group, and input is connected with corresponding logic calculation module respectively；
The quantity of the logic calculation module is 4, and the logic calculation module is used for according to every 4 the second registers and 2 the
The storing data of three registers carries out logical operation, to obtain the logic calculation value of 16 64 bits；
The counter, for increasing by 1 in each clock cycle；
The selector, for when the numerical value of counter is less than 48, according to the numerical value of counter, to current 16 64 bits
Numerical value in logic calculation value and the first register carries out selection output, to obtain the input of 16 new second registers
The input value of value and 8 third registers；When the numerical value of counter is equal to 48, according to the logic of current 16 64 bits
Calculated value calculates final result, and is sent to the output module.
7. the hardware realization apparatus that siacoin according to claim 6 digs mine algorithm, which is characterized in that the logic meter
Calculating module includes:
Receiving unit, the data of a, b, c, d and 2 third registers of the data storage for storing every 4 the second registers
M0, m1 points are one group；
Temporary register, for calculating every group of intermediate result a_r, b_r, c_r, d_r and storing, wherein a_r=a+b+
M0, d_r=(d^a_r) > > 32, c_r=c+d_r, b_r=(c_r^b) > > 24；
Computing unit, for calculating patrolling for every group of 4 64 bits according to every group of intermediate result a_r, b_r, c_r, d_r
Volume calculated value, a_o=a_r+b_r+m1, d_o=(d_r^a_o) > > 16, c_o=c_r+d_o, b_o=(c_o^b_r) > > 63.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835389A (en) * | 2005-03-14 | 2006-09-20 | 华为技术有限公司 | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator |
| JP4723586B2 (en) * | 2004-09-10 | 2011-07-13 | カビウム・ネットワークス・インコーポレーテッド | Packet queuing, scheduling, and ordering |
| CN104915249A (en) * | 2015-05-21 | 2015-09-16 | 北京比特大陆科技有限公司 | Method and device for digging virtual digital coins in mining pool |
| CN106407008A (en) * | 2016-08-31 | 2017-02-15 | 北京比特大陆科技有限公司 | Mining business processing method, device and system |
-
2018
- 2018-01-15 CN CN201810036214.2A patent/CN110046875B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4723586B2 (en) * | 2004-09-10 | 2011-07-13 | カビウム・ネットワークス・インコーポレーテッド | Packet queuing, scheduling, and ordering |
| CN1835389A (en) * | 2005-03-14 | 2006-09-20 | 华为技术有限公司 | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator |
| CN104915249A (en) * | 2015-05-21 | 2015-09-16 | 北京比特大陆科技有限公司 | Method and device for digging virtual digital coins in mining pool |
| CN106407008A (en) * | 2016-08-31 | 2017-02-15 | 北京比特大陆科技有限公司 | Mining business processing method, device and system |
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