CN110046875B - Hardware implementation method and device of siacoin ore excavation algorithm - Google Patents
Hardware implementation method and device of siacoin ore excavation algorithm Download PDFInfo
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Abstract
The invention relates to the technical field of virtual currency mining, and discloses a hardware implementation method and device of a siacoin mining algorithm, wherein 80 bytes of input data are acquired, and the input data are input into 10 first registers with 64-bit width according to a group of 64 bits; dividing every 4 second registers and 2 third registers into a group, and respectively inputting the group into corresponding logic calculation modules for logic operation to obtain 16 logic calculation values with 64 bits; when the value of the counter is smaller than 48, the selector selects and outputs the current 16 logic calculation values with 64 bits and the value in the first register according to the value of the counter so as to obtain new input values of 16 second registers and 8 third registers, and the iteration is continued; when the counter value equals 48, the final result is calculated based on the current 16 logical calculated values of 64 bits. Compared with the siacoin ore excavation algorithm realized by the GPU display card in the prior art, the method has the advantages of higher computational power and lower power consumption.
Description
Technical Field
The invention relates to the technical field of virtual currency excavation, in particular to a hardware implementation method and device of a siacoin excavation algorithm.
Background
siacoin is a virtual digital currency, and adopts the mining algorithm of POW (proof of work). The key point of the POW mining algorithm is that the higher the computing power is, the more virtual money is obtained, the lower the power consumption is, and the lower the electricity fee is, the more income is obtained.
The mainstream equipment for digging the siacoin in the prior art is a GPU (graphics processing Unit) display card, the calculation power is not high and is about 1GHash/s, namely, 1G times of calculation specified by the siacoin algorithm is finished every second, the power consumption is large and is about 135W, and energy is wasted.
Disclosure of Invention
The invention provides a hardware implementation method and device of a siacoin ore excavation algorithm, and solves the technical problems of low computing power, high power consumption and energy waste of ore excavation equipment in the prior art.
The purpose of the invention is realized by the following technical scheme:
a hardware implementation method of a siacoin ore-mining algorithm comprises the following steps:
step S1, obtaining input data of 80 bytes, and inputting the input data into 10 first registers with 64-bit width according to a group of 64 bits, where the number of the first registers is 16, the first 10 first registers are used for storing input data, and the last 6 first registers store values of zero;
step S2, dividing each of 4 second registers and 2 third registers into a group, and inputting the group into corresponding logic calculation modules for logic operation to obtain 16 logic calculation values with 64 bits, where the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits;
step S3, when the counter is less than 48, the selector selects and outputs the current 16 logic calculated values of 64 bits and the value in the first register according to the counter value to obtain new input values of 16 second registers and 8 third registers, and go to step S2 to continue execution, wherein the counter is incremented by 1 in each clock cycle;
in step S4, when the counter value is equal to 48, the final result is calculated according to the current 16 logic calculation values of 64 bits.
A hardware implementation device of a siacoin ore-mining algorithm comprises: a first register, a second register, a third register, a counter, an output module, a logic calculation module and a selector, wherein,
the number of the first registers is 16, the first 10 first registers are used for storing input data, and the numerical values stored by the last 6 first registers are zero;
the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits; dividing every 4 second registers and 2 third registers into a group, wherein each group is respectively connected with a corresponding logic calculation module;
the number of the logic calculation modules is 4, and the logic calculation modules are used for performing logic operation according to the storage data of every 4 second registers and 2 third registers to obtain 16 logic calculation values with 64 bits;
the counter is used for increasing by 1 in each clock cycle;
the selector is used for selecting and outputting current 16 logic calculated values of 64 bits and the value in the first register according to the value of the counter when the value of the counter is smaller than 48, so as to obtain new input values of 16 second registers and new input values of 8 third registers; when the value of the counter is equal to 48, a final result is calculated according to the current 16 logic calculation values of 64 bits and is sent to the output module.
The invention provides a hardware implementation method and a hardware implementation device of a siacoin mining algorithm, which are characterized in that 80 bytes of input data are obtained, and the input data are input into 10 first registers with 64-bit width according to a group of 64 bits; dividing every 4 second registers and 2 third registers into a group, and respectively inputting the group into corresponding logic calculation modules for logic operation to obtain 16 logic calculation values with 64 bits; when the value of the counter is smaller than 48, the selector selects and outputs the current 16 logic calculation values with 64 bits and the value in the first register according to the value of the counter so as to obtain new input values of 16 second registers and 8 third registers, and the iteration is continued; when the counter value equals 48, the final result is calculated based on the current 16 logical calculated values of 64 bits. Compared with the siacoin ore excavation algorithm realized by the GPU display card in the prior art, the method has the advantages of higher computational power and lower power consumption.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a flowchart of a hardware implementation method of a siacoin mining algorithm according to an embodiment of the present invention;
fig. 2 is a structural diagram of a hardware implementation apparatus of the siacoin excavation algorithm according to the embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, a flowchart of a hardware implementation method of a siacoin mining algorithm provided in an embodiment of the present invention includes:
step S1, acquiring 80 bytes of input data, and inputting the input data into 10 first registers with 64-bit width according to a group of 64 bits;
the number of the first registers is 16, and the first registers are m 0-m 15, m 0-m 9 are used for storing input data, the values stored by m 10-m 15 are zero, and m 0-m 15 are numbers of the first registers, and the numbers are not only used for identifying the registers but also used for representing the data stored in the registers;
step S2, dividing each of the 4 second registers and the 2 third registers into a group, and inputting the group into corresponding logic calculation modules for logic operation, so as to obtain 16 logic calculation values with 64 bits;
the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits;
step S2 may further include:
step S2-1, grouping the data a, b, c and d stored in each 4 second registers and the data m0 and m1 stored in each 2 third registers into a group;
step S2-2, calculating intermediate results a _ r, b _ r, c _ r, d _ r of each group and storing them in a temporary register, wherein a _ r ═ a + b + m0, d _ r ═ d a _ r > 32 (the result of d xor a _ r is cyclically shifted to the right by 32 bits), c _ r ═ c + d _ r, b _ r ═ c _ r ^ b > 24 (the result of d xor a _ r is cyclically shifted to the right by 24 bits);
in step S2-3, 4 logic calculated values of 64 bits for each group are calculated according to the intermediate results a _ r, b _ r, c _ r, d _ r for each group, where a _ o ═ a _ r + b _ r + m1, d _ o ═ d _ r _ o > 16, c _ o ═ c _ r + d _ o, and b _ o ^ b _ r > 63.
Step S3, when the counter is smaller than 48, the selector selects and outputs the current 16 logic calculated values of 64 bits and the value in the first register according to the counter value to obtain new input values of 16 second registers and 8 third registers, and go to step S2 to continue execution;
wherein the counter is incremented by 1 each clock cycle;
the first time of calculation is a preset value (16 64-bit logic calculation values are not calculated at this time, and 16 64-bit logic calculation values of the first round are calculated when the counter is at 2 times after 2 clock cycles), so when the value of the counter is equal to 0 or 1, new 16 input values gf _ i0, gf _ i1, gf _ i2, gf _ i3, gf _ i4, gf _ i5, gf _ i6, gf _ i7, gf _ i8, gf _ i9, gf _ i10, gf _ i11, gf _ i12, gf _ i13, gf _ i14, gf _ i15, and 8 input values G _ m0, G _ m1, G _ m2, G _ m9, G _ m4, G _ m 69556, G _ m 8653, wherein the preset value is G _ m 86 6,
gf_i0＝64′h6A09E667F3BCC908^{32′h0、32′h01010000}^64′h20；
gf_i4＝64′hBB67AE8584CAA73B；
gf_i8＝64′h3C6EF372FE94F82B；
gf_i12＝64′hA54FF53A5F1D36F1；
gf_i1＝64′h510E527FADE682D1；
gf_i5＝64′h9B05688C2B3E6C1F；
gf_i9＝64′h1F83D9ABFB41BD6B；
gf_i13＝64′h5BE0CD19137E2179；
gf_i2＝64′h6A09E667F3BCC908；
gf_i6＝64′hBB67AE8584CAA73B；
gf_i10＝64′h3C6EF372FE94F82B；
gf_i14＝64′hA54FF53A5F1D36F1；
gf_i3＝64′h510E527FADE682D1^64’h50；
gf_i7＝64′h9B05688C2B3E6C1F；
negation is carried out on gf _ i11 (64' h1F83D9ABFB41BD6B) in a bitwise manner;
gf_i15＝64′h5BE0CD19137E2179；
G_m0＝m0；
G_m1＝m1；
G_m2＝m2；
G_m3＝m3；
G_m4＝m4；
G_m5＝m5；
G_m6＝m6；
G_m7＝m7。
when the counter has a value of 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39, 42, 43, 46, 47, the input values gf _ i0 ═ gf _ o0, gf _ i _ gf _ o0, gf _ o0, gf _ o0, and a new iteration 0, gf _ o0, gf _ o 36i _ 0, gf _ o0, gf _ gf;
when the counters are 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29, 32, 33, 36, 37, 40, 41, 44, 45, the input values gf _ i0 ═ gf _ o0, gf _ i0 ═ gf _ o0, gf _ i _ gf _ o0, gf _ o0, gf _ gf;
wherein gf _ o0, gf _ o1, gf _ o2, gf _ o3, gf _ o4, gf _ o5, gf _ o6, gf _ o7, gf _ o8, gf _ o9, gf _ o10, gf _ o11, gf _ o12, gf _ o13, gf _ o14, gf _ o15 are logical calculation values of 16 bits obtained in step S2;
the installation of the input values of the 8 third registers is obtained as follows:
when the counter has a value of 2, 3, 42, 43, the input values G _ m0 to G _ m7 of the 8 third registers take the following values: m8, m9, m10, m11, m12, m13, m14, m 15;
when the value of the counter is 4, 5, 44 and 45, the input values G _ m0 to G _ m7 of the 8 third registers respectively take on the values of m14, m10, m4, m8, m9, m15, m13 and m 6;
when the value of the counter is 6, 7, 46 and 47, the input values G _ m0 to G _ m7 of the 8 third registers respectively take on the values of m1, m12, m0, m2, m11, m7, m5 and m 3;
when the value of the counter is 8 and 9, the input values G _ m 0-G _ m7 of the 8 third registers are respectively m11, m8, m12, m0, m5, m2, m15 and m 13;
when the value of the counter is 10 and 11, the input values G _ m0 to G _ m7 of the 8 third registers take the values of m10, m14, m3, m6, m7, m1, m9 and m4 respectively;
when the value of the counter is 12 and 13, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m7, m9, m3, m1, m13, m12, m11 and m 14;
when the value of the counter is 14 and 15, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m2, m6, m5, m10, m4, m0, m15 and m 8;
when the value of the counter is 16 and 17, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m9, m0, m5, m7, m2, m4, m10 and m 15;
when the value of the counter is 18 and 19, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m14, m1, m11, m12, m6, m8, m3 and m 13;
when the value of the counter is 20 and 21, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m2, m12, m6, m10, m0, m11, m8 and m 3;
when the value of the counter is 22 and 23, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m4, m13, m7, m5, m15, m14, m1 and m 9;
when the value of the counter is 24 and 25, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m12, m5, m1, m15, m14, m13, m4 and m 10;
when the value of the counter is 26 and 27, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m0, m7, m6, m3, m9, m2, m8 and m 11;
when the value of the counter is 28 and 29, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m13, m11, m7, m14, m12, m1, m3 and m 9;
when the value of the counter is 30 and 31, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m5, m0, m15, m4, m8, m6, m2 and m 10;
when the value of the counter is 32 and 33, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m6, m15, m14, m9, m11, m3, m0 and m 8;
when the value of the counter is 34 and 35, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m12, m2, m13, m7, m1, m4, m10 and m 5;
when the value of the counter is 38 and 39, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m15, m11, m9, m14, m3, m12, m13 and m 0;
when the counter has the values of 40 and 41, the input values G _ m0 to G _ m7 of the 8 third registers take the values of: m0, m1, m2, m3, m4, m5, m6 and m 7.
In step S4, when the counter value is equal to 48, the final result is calculated according to the current 16 logic calculation values of 64 bits.
Wherein, after repeating iteration for 12 times, that is, when the value of the counter is equal to 48, the current 16 logical calculated values gf _ o0, gf _ o1, gf _ o2, gf _ o3, gf _ o4, gf _ o5, gf _ o6, gf _ o7, gf _ o8, gf _ o9, gf _ o10, gf _ o11, gf _ o12, gf _ o13, gf _ o14, gf _ o15 are obtained;
according to the current 16 logic calculation values of 64 bits, 8 Hash values of 64 bits, namely Hash0, Hash1, Hash2, Hash3, Hash4, Hash5, Hash6 and Hash7 are calculated, wherein,
Hash0＝64′h6A09E667F3BCC908^gf_o0^gf_o10；
Hash1＝64′hBB67AE8584CAA73B^gf_o4^gf_o14；
Hash2＝64′h3C6EF372FE94F82B^gf_o8^gf_o2；
Hash3＝64′hA54FF53A5F1D36F1^gf_o12^gf_o6；
Hash4＝64′h510E527FADE682D1^gf_o13^gf_o7；
Hash5＝64′h9B05688C2B3E6C1F^gf_o1^gf_o11；
Hash6＝64′h1F83D9ABFB41BD6B^gf_o5^gf_o15；
Hash7＝64′h5BE0CD19137E2179^gf_o9^gf_o3。
and the final 512bit Hash results consisting of 8 64-bit Hash values of Hash0, Hash1, Hash2, Hash3, Hash4, Hash5, Hash6 and Hash7 are final calculation results.
The embodiment of the invention provides a hardware implementation method of a siacoin mining algorithm, which comprises the steps of obtaining 80 bytes of input data, and inputting the input data into 10 first registers with 64 bit widths according to a group of 64 bits; dividing every 4 second registers and 2 third registers into a group, and respectively inputting the group into corresponding logic calculation modules for logic operation to obtain 16 logic calculation values with 64 bits; when the value of the counter is smaller than 48, the selector selects and outputs the current 16 logic calculation values with 64 bits and the value in the first register according to the value of the counter so as to obtain new input values of 16 second registers and 8 third registers, and the iteration is continued; when the counter value equals 48, the final result is calculated based on the current 16 logical calculated values of 64 bits. Compared with the siacoin ore excavation algorithm realized by the GPU display card in the prior art, the method has the advantages of higher computational power and lower power consumption.
The embodiment of the present invention further provides a hardware implementation apparatus for a siacoin excavation algorithm, as shown in fig. 2, including: a first register 210, a second register 220, a third register 230, a counter 240, an output module 250, a logic calculation module 260, and a selector 270, wherein,
the number of the first registers is 16, the first 10 first registers are used for storing input data, and the numerical values stored by the last 6 first registers are zero;
the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits; dividing every 4 second registers and 2 third registers into a group, wherein each group is respectively connected with a corresponding logic calculation module;
the number of the logic calculation modules is 4, and the logic calculation modules are used for performing logic operation according to the storage data of every 4 second registers and 2 third registers to obtain 16 logic calculation values with 64 bits;
the counter is used for increasing by 1 in each clock cycle;
the selector is used for selecting and outputting current 16 logic calculated values of 64 bits and the value in the first register according to the value of the counter when the value of the counter is smaller than 48, so as to obtain new input values of 16 second registers and new input values of 8 third registers; when the value of the counter is equal to 48, a final result is calculated according to the current 16 logic calculation values of 64 bits and is sent to the output module.
Wherein the logic computation module comprises:
a receiving unit for grouping the data a, b, c, d stored in each of the 4 second registers and the data m0, m1 stored in the 2 third registers;
a temporary register for calculating and storing intermediate results a _ r, b _ r, c _ r, d _ r for each group, wherein a _ r ═ a + b + m0, d _ r ^ a _ r > 32, c _ r ^ c + d _ r, b _ r ^ c _ r > 24;
and a calculating unit, configured to calculate, according to the intermediate results a _ r, b _ r, c _ r, d _ r of each group, a _ o ═ a _ r + b _ r + m1, d _ o ═ d _ r ^ a _ o > 16, c _ o ^ c _ r + d _ o, and b _ o ^ b _ r) > 63, the logical calculated values of the 4 bits of each group.
The device has the advantages that 50 clk cycles are solved, the occupied chip area is small, the main frequency is high, a single chip can contain a large number of computing cores corresponding to the device, the computing power is up to 5G Hash/s, the power consumption is only 5W, and compared with a siacoin ore digging algorithm realized by a GPU video card in the prior art, the computing power is higher, and the power consumption is lower.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by software plus a necessary hardware platform, and certainly may be implemented by hardware, but in many cases, the former is a better embodiment. With this understanding in mind, all or part of the technical solutions of the present invention that contribute to the background can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments or some parts of the embodiments of the present invention.
The present invention has been described in detail, and the principle and embodiments of the present invention are explained herein by using specific examples, which are only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. A hardware implementation method of a siacoin ore-mining algorithm is characterized by comprising the following steps:
step S1, acquiring 80 bytes of input data, and inputting the input data into 10 first registers with 64-bit widths according to a 64-bit group, wherein the number of the first registers is 16, the data stored in the 16 first registers are m0 to m15 respectively, m0 to m9 are input data, and the numerical values of m10 to m15 are zero;
step S2, dividing every 4 second registers and every 2 third registers into a group, and inputting the group into corresponding logic calculation modules for logic calculation to obtain 16 logic calculation values with 64 bits, where the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits;
step S3, when the counter is less than 48, the selector selects and outputs the current 16 logic calculated values of 64 bits and the value in the first register according to the counter value to obtain new input values of 16 second registers and 8 third registers, and go to step S2 to continue execution, wherein the counter is incremented by 1 in each clock cycle;
in step S4, when the counter value is equal to 48, the final result is calculated according to the current 16 logic calculation values of 64 bits.
2. The hardware implementation method of the siacoin mining algorithm of claim 1, wherein step S2 includes:
grouping data a, b, c and d stored in every 4 second registers and data m0 and m1 stored in every 2 third registers, wherein the data m0 and m1 stored in the third registers are data m0 and m1 stored in the first registers respectively;
calculating intermediate results a _ r, b _ r, c _ r and d _ r of each group and storing the intermediate results into a temporary register, wherein a _ r is a + b + m0, d _ r is (d ^ a _ r) > 32, c _ r is c + d _ r, b _ r is (c _ r ^ b) > 24;
according to the intermediate result a _ r, b _ r, c _ r, d _ r of each group, 4 logic calculation values of 64 bits of each group are calculated, a _ o ═ a _ r + b _ r + m1, d _ o ═ d _ r ^ a _ o > 16, c _ o ═ c _ r + d _ o, b _ o ═ b _ r > 63.
3. The hardware implementation method of the siacoin mining algorithm of claim 1, wherein step S3 includes:
when the value of the counter is equal to 0 or 1, the input values gf _ i0, gf _ i1, gf _ i2, gf _ i3, gf _ i4, gf _ i5, gf _ i6, gf _ i7, gf _ i8, gf _ i9, gf _ i10, gf _ i11, gf _ i12, gf _ i13, gf _ i14, gf _ i15 and the input values G _ m0, G _ m1, G _ m2, G _ m3, G _ m4, G _ m5, G _ m6, G _ m7 of the new 16 said second registers are preset values, wherein gf _ i0 is 64 ' BCC h6a09E F3F 908 h 908 {32 ' h0, 32 ' 10000 h } 20 a/64;
gf_i4＝64＇hBB67AE8584CAA73B；
gf_i8＝64＇h3C6EF372FE94F82B；
gf_i12＝64＇hA54FF53A5F1D36F1；
gf_i1＝64＇h510E527FADE682D1；
gf_i5＝64＇h9B05688C2B3E6C1F；
gf_i9＝64＇h1F83D9ABFB41BD6B；
gf_i13＝64＇h5BE0CD19137E2179；
gf_i2＝64＇h6A09E667F3BCC908；
gf_i6＝64＇hBB67AE8584CAA73B；
gf_i10＝64＇h3C6EF372FE94F82B；
gf_i14＝64＇hA54FF53A5F1D36F1；
gf_i3＝64＇h510E527FADE682D1＾64’h50；
gf_i7＝64＇h9B05688C2B3E6C1F；
gf_i11＝～(64＇h1F83D9ABFB41BD6B)；
gf_i15＝64＇h5BE0CD19137E2179；
G_m0＝m0；
G_m1＝m1；
G_m2＝m2；
G_m3＝m3；
G_m4＝m4；
G_m5＝m5；
G_m6＝m6；
G_m7＝m7。
4. the hardware implementation method of the siacoin mining algorithm of claim 1, wherein step S3 includes:
when the counter has a value of 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39, 42, 43, 46, 47, the input values gf _ i0 ═ gf _ o0, gf _ i1 ═ gf _ o5, gf _ i5 ═ gf _ o5, gf _ i _ gf _ o5, gf _ o5, gf _ i _ gf _ o5, gf _ o5, gf _ 5, gf _ o5, gf _;
when the counter is 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29, 32, 33, 36, 37, 40, 41, 44, 45, the input values gf _ i0 ═ gf _ o0, gf _ i1 ═ gf _ o13, gf _ i13 ═ gf _ o13, gf _ i _ gf _ o13, gf _ gf;
when the counter has a value of 2, 3, 42, 43, the input values G _ m0 to G _ m7 of the 8 third registers take the following values: m8, m9, m10, m11, m12, m13, m14, m 15;
when the value of the counter is 4, 5, 44 and 45, the input values G _ m0 to G _ m7 of the 8 third registers respectively take on the values of m14, m10, m4, m8, m9, m15, m13 and m 6;
when the value of the counter is 6, 7, 46 and 47, the input values G _ m0 to G _ m7 of the 8 third registers respectively take on the values of m1, m12, m0, m2, m11, m7, m5 and m 3;
when the value of the counter is 8 and 9, the input values G _ m 0-G _ m7 of the 8 third registers are respectively m11, m8, m12, m0, m5, m2, m15 and m 13;
when the value of the counter is 10 and 11, the input values G _ m0 to G _ m7 of the 8 third registers take the values of m10, m14, m3, m6, m7, m1, m9 and m4 respectively;
when the value of the counter is 12 and 13, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m7, m9, m3, m1, m13, m12, m11 and m 14;
when the value of the counter is 14 and 15, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m2, m6, m5, m10, m4, m0, m15 and m 8;
when the value of the counter is 16 and 17, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m9, m0, m5, m7, m2, m4, m10 and m 15;
when the value of the counter is 18 and 19, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m14, m1, m11, m12, m6, m8, m3 and m 13;
when the value of the counter is 20 and 21, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m2, m12, m6, m10, m0, m11, m8 and m 3;
when the value of the counter is 22 and 23, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m4, m13, m7, m5, m15, m14, m1 and m 9;
when the value of the counter is 24 and 25, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m12, m5, m1, m15, m14, m13, m4 and m 10;
when the value of the counter is 26 and 27, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m0, m7, m6, m3, m9, m2, m8 and m 11;
when the value of the counter is 28 and 29, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m13, m11, m7, m14, m12, m1, m3 and m 9;
when the value of the counter is 30 and 31, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m5, m0, m15, m4, m8, m6, m2 and m 10;
when the value of the counter is 32 and 33, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m6, m15, m14, m9, m11, m3, m0 and m 8;
when the value of the counter is 34 and 35, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m12, m2, m13, m7, m1, m4, m10 and m 5;
when the value of the counter is 36 and 37, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m15, m11, m9, m14, m3, m12, m13 and m 0;
when the value of the counter is 38 and 39, the input values G _ m0 to G _ m7 of the 8 third registers are respectively m15, m11, m9, m14, m3, m12, m13 and m 0;
when the counter has the values of 40 and 41, the input values G _ m0 to G _ m7 of the 8 third registers take the values of: m0, m1, m2, m3, m4, m5, m6, m 7;
wherein, gf _ o0, gf _ o1, gf _ o2, gf _ o3, gf _ o4, gf _ o5, gf _ o6, gf _ o7, gf _ o8, gf _ o9, gf _ o10, gf _ o11, gf _ o12, gf _ o13, gf _ o14, gf _ o15 are logical calculation values of 16 bits obtained in step S2.
5. The hardware implementation method of the siacoin mining algorithm of claim 1, wherein step S4 includes:
when the value of the counter is equal to 48, obtaining current 16 logical calculation values of 64 bits, gf _ o0, gf _ o1, gf _ o2, gf _ o3, gf _ o4, gf _ o5, gf _ o6, gf _ o7, gf _ o8, gf _ o9, gf _ o10, gf _ o11, gf _ o12, gf _ o13, gf _ o14, gf _ o 15;
according to the current 16 logic calculation values of 64 bits, 8 Hash values of 64 bits, namely Hash0, Hash1, Hash2, Hash3, Hash4, Hash5, Hash6 and Hash7 are calculated, wherein,
Hash0＝64＇h6A09E667F3BCC908＾gf_o0＾gf_o10；
Hash1＝64＇hBB67AE8584CAA73B＾gf_o4＾gf_o14；
Hash2＝64＇h3C6EF372FE94F82B＾gf_o8＾gf_o2；
Hash3＝64＇hA54FF53A5F1D36F1＾gf_o12＾gf_o6；
Hash4＝64＇h510E527FADE682D1＾gf_o13＾gf_o7；
Hash5＝64＇h9B05688C2B3E6C1F＾gf_o1＾gf_o11；
Hash6＝64＇h1F83D9ABFB41BD6B＾gf_o5＾gf_o15；
Hash7＝64＇h5BE0CD19137E2179＾gf_o9＾gf_o3。
6. a hardware implementation device of a siacoin ore-mining algorithm is characterized by comprising the following components: a first register, a second register, a third register, a counter, an output module, a logic calculation module and a selector, wherein,
the number of the first registers is 16, wherein the data stored in the 16 first registers are m 0-m 15, m 0-m 9 are input data, and the values of m 10-m 15 are zero;
the number of the second registers is 16, the bit width is 64 bits, the number of the third registers is 8, and the bit width is 64 bits; dividing every 4 second registers and every 2 third registers into a group, and respectively connecting each group with a corresponding logic calculation module;
the number of the logic calculation modules is 4, and the logic calculation modules are used for performing logic operation according to the storage data of every 4 second registers and every 2 third registers to obtain 16 logic calculation values with 64 bits;
the counter is used for increasing in each clock cycle1；
The selector is used for selecting and outputting current 16 logic calculated values of 64 bits and the value in the first register according to the value of the counter when the value of the counter is smaller than 48, so as to obtain new input values of 16 second registers and new input values of 8 third registers; when the value of the counter is equal to 48, a final result is calculated according to the current 16 logic calculation values of 64 bits and is sent to the output module.
7. The hardware implementation of the siacoin mining algorithm of claim 6, wherein the logic computation module comprises:
a receiving unit, configured to group data a, b, c, d stored in every 4 second registers and data m0, m1 stored in every 2 third registers, where the data m0 and m1 stored in the third registers are data m0 and m1 stored in the first registers, respectively;
a temporary register for calculating and storing intermediate results a _ r, b _ r, c _ r, d _ r of each group, wherein a _ r ═ a + b + m0, d _ r ═ d ^ a _ r > 32, c _ r ═ c + d _ r, b _ r ═ c _ r ^ b > 24;
and a calculating unit, configured to calculate, according to the intermediate results a _ r, b _ r, c _ r, and d _ r of each group, 4 logic calculated values of 64 bits for each group, where a _ o ═ a _ r + b _ r + m1, d _ o ═ d _ r ^ a _ o > 16, c _ o ═ c _ r + d _ o, and b _ o ═ c _ o ^ b _ r > 63.
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