CN110413257A - Random number generation circuit - Google Patents
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- CN110413257A CN110413257A CN201910693756.1A CN201910693756A CN110413257A CN 110413257 A CN110413257 A CN 110413257A CN 201910693756 A CN201910693756 A CN 201910693756A CN 110413257 A CN110413257 A CN 110413257A
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- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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Abstract
The invention discloses a kind of random number generation circuits, comprising: real random number generator for receiving the first clock signal, and generates a true random number under the control of first clock signal；Linear feedback shift register for receiving second clock signal, and generates m pseudo random numbers, and export output result of the m pseudo random number as random number generation circuit under the control of the second clock signal；Processing circuit is connected with the linear feedback shift register, the real random number generator respectively, for being calculated according to the true random number and m pseudo random numbers, and calculated result is fed back to the linear feedback shift register.Random number generation circuit provided by the invention makes the position the m TRNG random number of output have unpredictability, meets the needs of random number high security by introducing true random number TRNG_A.
Description
Technical field
The present invention relates to information security fields, especially with regard to a kind of random number generation circuit.
Background technique
Random number is the basis of cryptography, and most cryptographic algorithms need the random number of superperformance to support.Random number point
For two classes, pseudo random number and true random number.
Pseudo random number is generated by numerical algorithm, has limit cycle, meets the algorithm of certain determination, can use determination
Formula describes.The advantages of pseudo random number, is generated by digital algorithm, and randomness is not influenced by voltage, temperature, process corner.
The shortcomings that pseudo random number is the algorithm for meeting certain determination, so being substantially foreseeable.Once attacker can predict
Random number sequence, then the safety of cryptographic system cannot just ensure.True random number results from noise or chaos, has nothing
The periodicity of limit does not meet determining algorithm.Compared to pseudo random number, true random number has better safety.But it is possible to make
The true random-number generating method realized with integrated circuit is few, and main at present includes concussion sampling, thermal noise amplification, chaos circuit
Etc. several circuits.
Randomizer in the prior art, as seed, is then used usually using the data of real random number generator
Digital technology is post-processed.For example, can first acquire the truly random of 32bits using the random number of 1048576bits to be generated
Number, then uses this 32bits true random number data as seed, obtains remaining (1048576- using pseudorandom algorithm
32) data of bits.The source of n true random number is either used, each source is calculated using different pseudo-random algorithms, then
Calculated result is combined.
But be based on this inventors of the present application found that it is in the prior art using real random number generator as seed,
Pseudo random number operation method, if it is known that Pseudo-Random Number, by acquiring one piece of data, subsequent mass data is practical
On can be predicted by pseudo-random algorithm, be unable to satisfy the demand of random number high security.
The information disclosed in the background technology section is intended only to increase the understanding to general background of the invention, without answering
When being considered as recognizing or imply that the information constitutes the prior art already known to those of ordinary skill in the art in any form.
Summary of the invention
The purpose of the present invention is to provide a kind of random number generation circuits, can satisfy the need of random number high security
It asks.
To achieve the above object, the present invention provides a kind of random number generation circuits, comprising: real random number generator is used
In receiving the first clock signal, and a true random number is generated under the control of first clock signal；Linear feedback shift
Register for receiving second clock signal, and generates m pseudo random numbers, and defeated under the control of the second clock signal
Output result of the m pseudo random number as random number generation circuit out；Processing circuit, respectively with the linear feedback shift
Register, the real random number generator are connected, for being calculated according to the true random number and m pseudo random numbers,
And calculated result is fed back into the linear feedback shift register, wherein the linear feedback shift register is used for basis
Calculated result updates the value of the position the m pseudo random number generated in next second clock signal, the linear feedback shift register
Digit includes n bit shift register, 1≤m≤n/2.
In a preferred embodiment, the linear feedback shift register is used in the second clock signal
It rises after arriving, continuously does m operation, generate m TRNG, wherein the m TRNG includes TRNG1, TRNG2 ...
TRNGm-1, TRNGm.
In a preferred embodiment, the real random number generator the first clock signal rising edge arrive after,
Generate 1 true random number TRNG_A.
In a preferred embodiment, described to be calculated according to the true random number and m pseudo random numbers, and will
It includes: the control lower linear feedback for receiving current second clock signal that calculated result, which feeds back to the linear feedback shift register,
The TRNG_ that real random number generator generates under the control of m position TRNG and current first clock signal that shift register generates
A；Judge the TRNG_A and upper one first clock signal that real random number generator generates under the control of current first clock signal
Whether identical control the TRNG_A ' that lower real random number generator generates；If it is not the same, then judging whether TRNG_A is equal to linearly
The output valve TRNGm of feedback shift register；If unequal, by shift LD each in the linear feedback shift register
The value of device successively moves to left 1, and enabling the value for the shift register that position is preset in linear feedback shift register is TRNG_A,
In, the corresponding primitive polynomial of shift register of the default position is 1.
In a preferred embodiment, the output valve for judging TRNG_A and whether being equal to linear feedback shift register
After TRNGm, further includes: if equal, enable in linear feedback shift register preset position shift register value be 0 or
Person 1.
In a preferred embodiment, the value by shift register each in the linear feedback shift register according to
It is secondary to move to left 1, and the value for the shift register for presetting position in linear feedback shift register is enabled to be TRNG_A or enable linear anti-
After the value for presenting the shift register of default position in shift register is 0, further includes: judge the linear feedback shift register
In each shift register value whether all zero；If all zero, would enable appointing in the linear feedback shift register
The value of single place shift register is equal to nonzero value.
In a preferred embodiment, first clock signal and the second clock signal are identical clock letter
Number.
Compared with prior art, random number generation circuit according to the present invention is made by introducing true random number TRNG_A
The position the m TRNG random number of output has unpredictability, and randomness is high, meets the needs of random number high security.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of random number generation circuit according to an embodiment of the present invention.
Fig. 2 is the workflow schematic diagram of random number generation circuit according to an embodiment of the present invention.
Fig. 3 is the structural schematic diagram of linear feedback shift register according to an embodiment of the present invention.
Fig. 4 is the workflow schematic diagram of processing circuit according to an embodiment of the present invention.
Fig. 5 is a kind of structural schematic diagram of the implementation of processing circuit according to an embodiment of the present invention.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in detail, it is to be understood that guarantor of the invention
Shield range is not limited by the specific implementation.
Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " includes " or its change
Changing such as "comprising" or " including " etc. will be understood to comprise stated element or component, and not exclude other members
Part or other component parts.
As shown in Figure 1, it is such as to be schemed according to the structural schematic diagram of the random number generation circuit of the preferred embodiment for the present invention
Shown in 2, for according to the workflow schematic diagram of the random number generation circuit of the preferred embodiment for the present invention, the present embodiment with
Machine number generation circuit includes: linear feedback shift register 1, real random number generator 2 and processing circuit 3.
Real random number generator 2 generates under the control of first clock signal for receiving the first clock signal
One true random number.
Specifically, real random number generator 2, which can be, makes concussion sampling, thermal noise amplification or chaos circuit etc..It is described
Real random number generator 2 is specifically used for after the rising edge of the first clock signal arrives, and generates 1 true random number TRNG_A.
Linear feedback shift register 1 is used to receive second clock signal, and under the control of the second clock signal
M pseudo random numbers are generated, and export output result of the m pseudo random number as random number generation circuit.
It can set linear feedback shift register 1 to after the rising edge of the second clock signal arrives, continuously
M operation is done, generates m TRNG, wherein the m TRNG includes TRNG1, TRNG2 ... TRNGm-1, TRNGm.It is described
First clock signal and the second clock signal can be identical clock signal, or different clock signals.
It can set linear feedback shift register 1 to after the failing edge of the second clock signal arrives, continuously do m fortune
It calculates.
The processing circuit 3 is connected with the linear feedback shift register 1, the real random number generator 2, is used for
It is calculated according to the true random number and m pseudo random numbers, and calculated result is fed back into the linear feedback shift and is posted
Storage 1, wherein the linear feedback shift register 1 is used to be updated according to calculated result and generate in next second clock signal
The position m pseudo random number value, the digit of the linear feedback shift register 1 includes n bit shift register, 1≤m≤n/2.
Specifically, m value is closer to n, then the corresponding output data of every true random number is more, but easier is predicted；m
For value closer to 1, then the corresponding output data of every true random number is fewer, is less susceptible to be predicted.It will be according to practical application scene
Determine m value.According to the principle of linear shift register, success prediction to go out one group of data, at least needs m >=n data, because
For m≤n/2 in this patent, it is possible to guarantee the random number generated after attacker can not successfully predict.
Specifically, the input of processing circuit 3 is m TRNG and 1 TRNG_A, after carrying out operation, according to operation result pair
The content of registers of linear feedback shift register is operated.
Random number generation circuit provided in this embodiment as a result, makes the position m of output by introducing true random number TRNG_A
TRNG random number has unpredictability, and randomness is high, meets the needs of random number high security.
The data of real random number generator are more uniformly inserted into pseudo-random algorithm generation by the method for the present embodiment
In the process, the data of such real random number generator are not only only used as seed, work in the beginning part of data, but make
During having used entire generating random number.So the random number that method provided in this embodiment generates, even if known pseudo-random
Several generating algorithms, the random number also having no idea by acquiring one section of random number, after predicting.And it is provided in this embodiment
The random number that method generates has good randomness, is also not readily susceptible to the influence of voltage, temperature, process corner.
Further, TRNG_A has the characteristics that infinite period, does not meet the truly random of determining algorithm, so this patent
Volume result also has the characteristics that infinite period, does not meet determining algorithm.The TRNG short cycle of output is pseudo random number, long week
Phase is uncertain true random number.For concussion sampling, at least needs to acquire n data, can be predicted.Cause
For m≤n/2 short enough of pseudorandom period of this patent, so can not be predicted by the so short period, so this
The random number that patent generates has unpredictability.By introducing true random number TRNG_A, linear feedback shift register is changed
The value of device, so the shortcomings that this patent overcomes linear feedback shift register, can be detected by rank of matrix and the linearity.Benefit
With the stochastic behaviour of pseudo random number, so that the true random number TRNG_ of the detections such as 01 balance or playing card detection cannot be passed through
A can pass through the detections such as 01 balance or playing card detection after pseudo-random process.
As shown in figure 3, it is the structural schematic diagram according to the linear feedback shift register of the preferred embodiment for the present invention,
Linear feedback shift register in the present embodiment can be 32 linear feedback shift registers.Wherein X1 to X32 is n=
32 shift registers, n0 to n32 are 33 nodes, and p1 to p32 is 32 selecting units determined by primitive polynomial,
TRNG is output position, and seed is seed.If having selected suitable primitive polynomial, the period longest of output sequence claims
For M sequence.Here setting seed seed is hexadecimal non-zero number, by taking FDEAB565 as an example.Circuit is by register x1~x32
It is set as seed.I.e.
X32=1, x31=1, x30=1, x29=1
X28=1, x27=1, x26=0, x25=1
X24=1, x23=1, x22=1, x21=0
X20=1, x19=0, x18=1, x17=0
X16=1, x15=0, x14=1, x13=1
X12=0, x11=1, x10=0, x09=1
X08=0, x07=1, x06=1, x05=0
X04=0, x03=1, x02=0, x01=1
After one CLK clock cycle, value x1~x32 is output to node n1~n32 by register.N1~n32 respectively and this
Former multinomial step-by-step does XOR operation and obtains p1~p32.Output valve TRNG=p32+p31+p30+ ...+p3+p2+p1, it is therein
Addition is modular arithmetic, as XOR operation.
It calculates every time, register array moves to left one.It moves to left and refers to X32=X31, X31=X30 ..., X2=X1, X1=
n0.Notice that its Central Plains x32 value is given up, x1 value is equal to n0 nodal value.
Further, as shown in figure 4, it is to be illustrated according to the workflow of the processing circuit of the preferred embodiment for the present invention
Scheme, the processing circuit in the present embodiment is specifically used for executing following steps.
In step S41, the position m that the control lower linear feedback shift register of current second clock signal generates is received
The TRNG_A that real random number generator generates under the control of TRNG and current first clock signal；
In step S42, judge TRNG_A that real random number generator under the control of current first clock signal generates with
Whether the TRNG_A ' that real random number generator generates under the control of upper one first clock signal is identical；
Wherein it is possible to realize above-mentioned judgement by judging whether TRNG_A overturns.If TRNG_A and TRNG_A ' be not identical,
Then it is judged as overturning.
In step S43, if it is not the same, then judging whether TRNG_A is equal to the output valve of linear feedback shift register
TRNGm。
In step S44, if unequal, by the value of shift register each in the linear feedback shift register according to
It is secondary to move to left 1, and enabling the value for the shift register that position is preset in linear feedback shift register is TRNG_A, wherein it is described pre-
If the corresponding primitive polynomial of the shift register of position is 1.
Such as 32 one of primitive polynomial Y [32:0] of bit shift register be 0b1,000 0,000 0,000 0000
0000 0000 0101 0111 1.Then being equal to 1 according to shift register principle Y [0] can ignore, other positions for being equal to 1 are
Y[1],Y[2],Y[3],Y[5],Y[7],Y[32].According to shift register principle, value p [i]=Y [i] and X [i] of p, institute
The position for being 0 with those Y [i], p [i] value are 0.P [i] value is 0, then can ignore in the XOR operation below.So choosing
Selecting these positions assignment TRNG_A will lead to failure.
The corresponding primitive polynomial of shift register of the default position, refers to the value of Y [i].The displacement of default position is posted
Storage corresponding Y [i] value is 1.
If the position that the shift register of default position can choose is i according to the example of above-mentioned primitive polynomial
=1,2,3,5,7,32.It can enable X [1], X [2], X [3], X [5], X [7], the one of value of X [32] is equal to TRNG_A.
In step S45, if equal, the value of shift register for presetting position in linear feedback shift register is enabled to be
0 or 1.
In step S46, the value whether all zero of each shift register in the linear feedback shift register is judged.
In step S47, if all zero, enable any bit shift LD in the linear feedback shift register
The value of device is equal to 1.After processing circuit is to the data manipulation of linear feedback shift register as a result, linear feedback shift should ensure that
The value of register is not all zero.
In cycles, then each clock CLK rising edge arrives above procedure, exports m random number TRNG.
As shown in figure 5, it is to be shown according to a kind of structure of the implementation of processing circuit of the preferred embodiment for the present invention
It is intended to, processing circuit may include finite state machine and multiple selector MUX.It is realized using two finite state machines suitable
Sequence executes, and the state of two finite state machines is two binary codes of S1 and S2.The sequence that jumps of finite state machine is S1S2=
00, S1S2=01, S1S2=10, S1S2=11.
The judgement whether TRNG_A overturns is realized by multiple selector MUX1, MUX1 is for receiving the first XOR gate
Output signal, when TRNG_A ' and TRNG_A are unequal, output 1, when TRNG_A ' is equal with TRNG_A, output 0.When
When TRNG_A ' exclusive or TRNG_A is equal to 1, illustrate that TRNG_A is overturn；When TRNG_A ' exclusive or TRNG_A is equal to 0, illustrate TRNG_A
Do not overturn.MUX1 also receives the output signal of the second XOR gate, and when TRNGm and TRNG_A are unequal, TRNGm is worked as in output 1
When equal with TRNG_A, output 0.Realize whether TRNG_A is equal to the judgement of TRNGm with TRNG_A exclusive or TRNGm.
Above four states successively sequentially execute.Processing circuit process is as follows:
First determine whether the state of finite state machine.When S1S2=00 state, multiple selector MUX1 selects different branch
Data be assigned to X [32:1].Execute the first step.Pass through TRNGA ' exclusive or TRNG_A first to realize whether TRNG_A overturns
Judgement.Secondly, realizing whether TRNG_A is equal to the judgement of TRNGm with TRNG_A exclusive or TRNGm.Work as TRNG_A ' exclusive or
TRNGA be equal to 1, and TRNG_A exclusive or TRNGm be equal to 1 when, multiple selector MUX1 selection by X [32:1] < < 1 as a result,
It is assigned to X [32:1]；In the case of other, X [32:1] is assigned to X [32:1] by selection.
When S1S2=01 state, X [1] is assigned to using the data of multiple selector MUX2 selection different branch.
TRNG_A ' exclusive or TRNG_A and TRNG_A exclusive or TRNGm is connected to the selection end of MUX2.Work as TRNG_A ' exclusive or TRNG_A and be equal to 1,
And when TRNG_A exclusive or TRNGm is equal to 1, TRNG_A is assigned to X [1] by multiple selector MUX2 selection；It is different to work as TRNG_A '
Or TRNG_A is equal to 1, and when TRNG_A exclusive or TRNGm is equal to 0, multiple selector MUX2 selection by 0 is assigned to X [1]；Its
In the case of him, X [1] is assigned to X [1] by multiple selector MUX2 selection.
When S1S2=10 state, X [1] is assigned to using the data of multiple selector MUX3 selection different branch.
TRNG_A ' exclusive or TRNG_A and X [32] or X [31] or... | X [2] or X [1] is connected to the selection end of MUX2.Work as TRNG_A '
Exclusive or TRNG_A is equal to 1, and X [32] or X [31] or... | when X [2] or X [1] is equal to 0, X [1] is assigned to by 1；Other
In the case of, X [1] is assigned to X [1].
When S1S2=11 state, illustrating to calculate terminates.
The random number generation circuit provided in the present embodiment as a result, can make the good of linear feedback shift register
Stochastic behaviour is maintained；The value of linear feedback shift register will not be all 0；True random number TRNG_A is introduced, output
M short cycles of TRNG are predictable pseudo random number, and long period is unpredictable true random number.When true random number TRNG_A is full 0
Or it is complete 1 when, output TRNG be pure linear feedback shift register, can satisfy primary demand.Simulate true random number hair
The clock of raw device a1 is CLK, and each CLK clock is along m TRNG of output, so when the frequency of output random number TRNG is m times
Clock frequency.Circuit related with m times of clock frequency is all digital circuit, and digital circuit needs charge and discharge there is no bulky capacitor, institute
Has the characteristics that low-power consumption with this circuit.
It should be understood by those skilled in the art that, embodiments herein can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the application, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The application is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The aforementioned description to specific exemplary embodiment of the invention is in order to illustrate and illustration purpose.These descriptions
It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can much be changed
And variation.The purpose of selecting and describing the exemplary embodiment is that explaining specific principle of the invention and its actually answering
With so that those skilled in the art can be realized and utilize a variety of different exemplary implementation schemes of the invention and
Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.
Claims (7)
1. a kind of random number generation circuit characterized by comprising
Real random number generator for receiving the first clock signal, and generates one under the control of first clock signal
True random number；
Linear feedback shift register generates m for receiving second clock signal, and under the control of the second clock signal
Position pseudo random number, and export output result of the m pseudo random number as random number generation circuit；
Processing circuit is connected with the linear feedback shift register, the real random number generator respectively, for according to institute
It states true random number and m pseudo random numbers is calculated, and calculated result is fed back into the linear feedback shift register,
In, the linear feedback shift register be used for according to calculated result update the position m that next second clock signal generates puppet with
The value of machine number, the digit of the linear feedback shift register include n bit shift register, 1≤m≤n/2.
2. random number generation circuit as described in claim 1, which is characterized in that the linear feedback shift register is used for
After the rising edge of the second clock signal arrives, m operation, m TRNG of generation are continuously, wherein the m TRNG include
TRNG1, TRNG2 ... TRNGm-1, TRNGm.
3. random number generation circuit as described in claim 1, which is characterized in that the real random number generator is in the first clock
After the rising edge of signal arrives, 1 true random number TRNG_A is generated.
4. random number generation circuit as described in claim 1, which is characterized in that described according to the true random number and m
Pseudo random number is calculated, and calculated result is fed back to the linear feedback shift register and includes:
Receive current second clock signal control lower linear feedback shift register generation m position TRNG and it is current first when
The TRNG_A that real random number generator generates under the control of clock signal；
Judge the TRNG_A and upper one first clock signal that real random number generator generates under the control of current first clock signal
Control under real random number generator generate TRNG_A ' it is whether identical；
If it is not the same, then judging whether TRNG_A is equal to the output valve TRNGm of linear feedback shift register；
If unequal, the value of shift register each in the linear feedback shift register is successively moved to left 1, and enable line
Property feedback shift register in preset position shift register value be TRNG_A, wherein the shift register of the default position
Corresponding primitive polynomial is 1.
5. random number generation circuit as described in claim 1, which is characterized in that described to judge whether TRNG_A is equal to linearly instead
After the output valve TRNGm for presenting shift register, further includes:
If equal, enabling the value for the shift register that position is preset in linear feedback shift register is 0 or 1.
6. random number generation circuit as claimed in claim 4, which is characterized in that described by the linear feedback shift register
In the value of each shift register successively move to left 1, and enable the value that the shift register of position is preset in linear feedback shift register
For TRNG_A or enable in linear feedback shift register preset position shift register value be 0 after, further includes:
Judge the value whether all zero of each shift register in the linear feedback shift register；
If all zero, would enable the value of any bit shift register in the linear feedback shift register be equal to non-zero
Value.
7. random number generation circuit as described in claim 1, which is characterized in that when first clock signal is with described second
Clock signal is identical clock signal.
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Cited By (5)
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| CN110989972A (en) * | 2019-12-05 | 2020-04-10 | 清华大学 | Random number generation method and random number generator |
| CN111540102A (en) * | 2020-04-30 | 2020-08-14 | 华南师范大学 | Dynamic password circuit, access control system and access control method |
| CN112130808A (en) * | 2020-08-28 | 2020-12-25 | 新华三大数据技术有限公司 | Random number generation method and device |
| CN114244397A (en) * | 2022-02-25 | 2022-03-25 | 北京智芯微电子科技有限公司 | Frequency hopping communication device, method, chip, transmitter and storage medium |
| CN116069295A (en) * | 2022-12-22 | 2023-05-05 | 海光集成电路设计(北京)有限公司 | True random number generation circuit, true random number generation method and electronic equipment |
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