CN110034748B - Design method of TDICMOS imaging unit - Google Patents

Design method of TDICMOS imaging unit Download PDF

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CN110034748B
CN110034748B CN201910293610.8A CN201910293610A CN110034748B CN 110034748 B CN110034748 B CN 110034748B CN 201910293610 A CN201910293610 A CN 201910293610A CN 110034748 B CN110034748 B CN 110034748B
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tdicmos
detector
resistor
output
imaging unit
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CN110034748A (en
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余达
刘金国
徐东
苗健宇
杨亮
胡庆龙
王玉龙
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A design method of a TDICMOS imaging unit relates to a design method of a TDICMOS imaging unit, solves the problems of complex design and poor stability of the existing TDICMOS imaging unit, and comprises a controller unit and a detector unit; the controller unit generates control signals required by the detector unit and receives digital image data output by the detector unit; the detector unit comprises a TDICMOS detector, an operational amplifier, an LDO, a driver with a Schmitt function and a level shifter with the Schmitt function; the invention designs the pixel part power supply with the current drawing and filling function, the transmission of digital input control signals, the generation mode of charge transfer driving signals, the placement mode of high-density area via holes and the processing of a multilayer ground plane respectively, thereby improving the utilization area of a circuit board to the maximum extent, improving the integrity of the control driving signals and a power supply and avoiding the risks of voltage breakdown, cold solder and the like.

Description

Design method of TDICMOS imaging unit
Technical Field
The invention relates to a design method of a TDICMOS imaging unit, in particular to a design method of a TDICMOS imaging unit with high reliability in application under a size-limited environment.
Background
For the imaging design of the charge domain TDICMOS, the detector internally comprises a light sensing part of the TDICCD detector and a charge transfer grid, and also comprises a related double sampling and digital-to-analog conversion circuit, a time sequence generator, a bias, an SPI register, an LVDS receiving and transmitting device and the like, so that the functional part is various. Because the functional part of the TDICMOS detector is various, the TDICMOS imaging design is complex, careful design and inspection are needed, and stable and reliable work can be ensured.
Disclosure of Invention
The invention provides a design method of a TDICMOS imaging unit, aiming at solving the problems of complex design and poor stability of the existing TDICMOS imaging unit.
A method of designing a TDICMOS imaging unit, the imaging unit comprising a controller unit and a detector unit; the controller unit generates control signals required by the detector unit and receives digital image data output by the detector unit; the detector unit comprises a TDICMOS detector, an operational amplifier, an LDO, a driver with a Schmitt function and a level shifter with the Schmitt function;
the operational amplifier and the LDO provide working voltage for the TDICMOS detector, the driver provides a driving signal for the TDICMOS detector, and the level converter with the Schmidt function provides a control signal for the TDICMOS detector; the LDO comprises an internal input end, a variable resistor, an output end, an error amplifier and an internal reference source VrefAnd ground terminal and external divider resistor and divider resistor RrefFilter capacitor CequAnd a bleed-off resistance R;
the input end and the error amplifier are connected with the variable resistor, the divider resistor is connected with the output end and the negative end of the error amplifier, and the divider resistor RrefA filter capacitor C connected with the negative terminal and the ground terminal of the error amplifierequAnd a bleeder resistor R connected in parallel between the output terminal and the ground terminal, the positive terminal of the error amplifier and an internal reference source VrefConnecting;
setting a voltage dividing resistance RrefAnd the total absorption current of the discharge resistor R is more than or equal to the sink current IsinkWhile a filter capacitor CequHas a large value and is in one line period tHInternal current IsinkDuring the duration of the current flowingsinkThe internal accumulated charge is less than or equal to the source current IsourceAt source current duration DeltatsourceDissipated charge and voltage dividing resistor RrefAnd the bleeder resistor R is in one line period tHConsumed charge, and the variation of the output peak voltage of the LDO output end is less than or equal to the maximum voltage delta V allowed by the detectormaxThe amplitude of variation;
Figure GDA0002623053210000021
Voutis LThe voltage of the DO output.
The invention has the beneficial effects that:
firstly, the LDO is adopted to supply power to the pixel part with the pull-in and fill-in current, so that the difficulty in obtaining high-current operational amplifier is avoided, and the LDO is convenient to obtain; the special bleeder resistor is adopted to absorb the sink current output by the detector, so that the problem of resistance drift caused by resistance heating caused by absorbing the sink current by adopting a divider resistor at the reference voltage end of the LDO is solved; on the other hand, the phenomenon that the voltage change amplitude of the output end of the LDO is too large due to the current flowing can be avoided.
The controller outputs higher voltage, so that the influence degree of external interference can be reduced; the series matching resistor reduces the rising edge and the falling edge, and reduces the interference to the outside; the detector end adopts a level conversion chip with a Schmidt function, so that the interference in the transmission process can be reduced and restrained; the whole signal transmission process is controlled according to single-end 50 ohm, and signal reflection caused by impedance mismatching can be restrained.
Thirdly, segmented impedance control is carried out on the driving signals, so that not only is enough driving capability of the detector ensured, but also the impedance continuity of the driving signals is ensured, and reflection is avoided;
and fourthly, the placement mode of the via holes in the high-density area can improve the utilization area of the circuit board to the maximum extent, and meanwhile, breakdown or short circuit caused by overlarge pressure difference is avoided.
And fifthly, the integrity of signals and power supplies can be ensured by processing the multiple layers of ground planes, and meanwhile, cold joint in the welding process is avoided.
Drawings
Fig. 1 is a topological structure diagram of an imaging unit in the TDICMOS imaging unit design method according to the present invention;
FIG. 2 is a schematic diagram of the LDO performing current pumping and sinking power supply in the design method of the TDICMOS imaging unit according to the present invention;
FIG. 3 is a block diagram illustrating the transmission of digital input control signals in the design method of the TDICMOS imaging unit according to the present invention;
FIG. 4 is a schematic diagram of the generation of a charge transfer driving signal in the design method of the TDICMOS imaging unit according to the present invention;
fig. 5 is a schematic diagram illustrating a placement mode of high-density area via holes in the TDICMOS imaging unit design method according to the present invention.
Detailed Description
First embodiment, the method for designing a TDICMOS imaging unit according to this embodiment is described with reference to fig. 1 to 5, and includes two parts, namely a controller unit and a detection unit. The detector unit comprises a TDICMOS detector, an operational amplifier, an LDO, a driver with a Schmitt function and a level shifter with the Schmitt function. The controller unit generates control signals required by the detector unit and receives digital image data output by the detector unit. The operational amplifier and the LDO generate the working voltage required by the detector, the driver with the Schmidt function generates the driving signal required by the TDICMOS detector, and the level shifter with the Schmidt function generates the control signal required by the TDICMOS detector.
In this embodiment, the pixel part with the pull-in and fill-in current is powered by two modes, the first mode is the existing mode and is generated by a mode of 'reference source + low-temperature drift voltage dividing resistor + high-current operational amplifier'; the maximum source current I of the high-current operational amplifier is larger than the maximum source current I of the loadsource_max2 times of the maximum allowable sinking current I, which is larger than the maximum sinking current I of the loadsink_max2 times of the total weight of the powder.
The second way is generated by means of LDO + bleeder resistor + filter capacitor, in conjunction with fig. 2. Conventional LDOs have only a current sourcing capability, but no current sinking capability. The LDO comprises an internal input end, a variable resistor, an output end, an error amplifier and an internal reference source VrefAnd ground terminal and external divider resistor and divider resistor RrefFilter capacitor CequAnd a bleed-off resistance R;
the input end and the error amplifier are connected with the variable resistor, the divider resistor is connected with the output end and the negative end of the error amplifier, and the divider resistor RrefA filter capacitor C connected with the negative terminal and the ground terminal of the error amplifierequAnd a bleeder resistor R connected in parallel between the output terminal and the ground terminal, and a positive terminal of the error amplifierAnd an internal reference source VrefConnecting; when the voltage of the output end is reduced due to the source current, the output of the error amplifier is a high level, and the output is switched on; when the sink current is larger than the consumed current of the circuit, the voltage on the capacitor is increased, the output of the error amplifier is at a low level, the output is disconnected, the current cannot be absorbed, and the voltage value is still increased continuously.
Thus setting the voltage dividing resistance RrefAnd the total absorption current of the discharge resistor R is more than or equal to the sink current IsinkWhile a filter capacitor CequHas a large value and is in one line period tHInternal current IsinkDuring the duration of the current flowingsinkThe internal accumulated charge is less than or equal to the source current IsourceAt source current duration DeltatsourceDissipated charge and voltage dividing resistor RrefAnd the bleeder resistor R is in one line period tHConsumed charge, and the variation of the output peak voltage of the LDO output end is less than or equal to the maximum voltage delta V allowed by the detectormaxThe amplitude of variation;
Figure GDA0002623053210000041
Voutis the voltage of the LDO output.
The present embodiment is described with reference to fig. 3, and in the present embodiment, the transmission method of the digital input control signal is: for long-distance transmission, the controller outputs higher voltage, the voltage is reduced under the influence of external interference, and the series resistance value is usually not more than 50 ohms (r is 50-r)out) The first matching resistor reduces the rising edge and the falling edge, and reduces the interference to the outside; the detector end adopts a level converter with a Schmidt function to convert the level converter into a required level value, and the whole signal transmission process is controlled according to single-ended 50 ohm. r isoutIs the output resistance value of the controller.
The present embodiment will be described with reference to fig. 4, and in the present embodiment, the charge transfer drive signal is generated by: the controller outputs higher voltage to reduce the influence of interference, and the series resistance value is usually not more than 50 ohms (r is 50-r)out) The second matching resistor reduces the rising and falling edges, minusSmall interference to nearby; the detector end adopts a driver with a Schmidt function to convert the level value required by the TDICMOS detector, and a third matching resistor with the resistance value not exceeding 10k for reducing the rising and falling edge time is connected in series with the output end of the driver. At the input end from the controller to the driver, the signal is controlled according to single end 50 ohm; the signal output by the driver to the TDICMOS detector has an impedance Z of less than 50 ohms0And (5) managing and controlling.
The impedance Z0And the determination of the line width of the inner layer and the outer layer comprises the following steps;
(1) according to the magnitude of the peak value driving current and the thickness t of the inner layer conductor of the circuit boardcoreDetermining the line width w of the inner layer of the circuit boardcore；
(2) According to the thickness t of the inner layercoreAnd line width w of the inner layercoreDetermination of the impedance Z0；
Figure GDA0002623053210000042
In the formula hcoreThe distance between two adjacent conductive layers of the inner electric layer is defined; w is acoreIs the line width of the inner layer; t is tcoreIs the thickness of the inner layer of the conductor;
(3) according to the determined impedance Z0And the thickness t of the surface layersurfaceDetermining the line width w of the surface layersurface。
Figure GDA0002623053210000051
In the formula hsurfaceIs the thickness of the medium under the surface layer; w is asurfaceThe line width of the surface layer; t is tsurfaceIs the thickness of the conductor at the surface.
In this embodiment, the placement of the via holes in the high-density area on the circuit board is as follows: for the via connected to pad a, it can be placed in the blank area in fig. 5 (a); while vias not connected to pads a and B may not be routed within the capacitor package near the pads, outside the device package, or within the device, it is suggested to be located away from the pads, near the center of the capacitor device, as in the empty area of fig. 5 (B).
Wherein the safe distance wtAB between the via hole connected with the pad A and the pad B is (mm) not less than the pressure difference between the via hole and the network of the pads A and B multiplied by 0.013 mm/V;
meanwhile, the safety distance wtA (mm) between the via hole which is not connected with the bonding pads A and B and the bonding pad A is not less than the pressure difference multiplied by 0.013mm/V between the via hole network and the bonding pad A network;
and meanwhile, the safety distance wtB (mm) between the via hole which is not connected with the bonding pads A and B and the bonding pad B is not less than the pressure difference between the via hole network and the bonding pad B network multiplied by 0.013 mm/V.
In this embodiment, the multilayer ground plane of the wiring board is processed in the following manner: in order to ensure the integrity of the signal and the power supply of the rigid-flex board, one of the two layers of each flex tape is a ground reference plane. In order to avoid that the multi-layer ground planes are connected with the direct-insert device to cause that the false welding occurs because the heat dissipation is too fast in the welding process, the ground planes of the two outermost layers and the three middle layers of the flexible band are connected with the grounding pin of the direct-insert element, and the ground planes of the other layers are not connected with the grounding pin of the direct-insert device; to avoid islanding the ground plane layer near the in-line device, ground vias are opened at interstitial locations near the in-line device to connect all of the ground layers together.
In the present embodiment, the CMOS detector is a TDICMOS product of long optical core corporation; the LDO adopts TPS7H1101 of TI company; the shipper adopts AD8629 of ADI company; the driver adopts ISL7457 of Intersil company; the level shifter with schmitt function employs 54AC163245 by ST corporation.

Claims (4)

  1. A method of designing a TDICMOS imaging unit comprising a controller unit and a detector unit; the controller unit generates control signals required by the detector unit and receives digital image data output by the detector unit; the detector unit comprises a TDICMOS detector, an operational amplifier, an LDO, a driver with a Schmitt function and a level shifter with the Schmitt function;
    the operational amplifier and the LDO provide working voltage for the TDICMOS detector, the driver provides a driving signal for the TDICMOS detector, and the level converter with the Schmidt function provides a control signal for the TDICMOS detector; it is characterized in that;
    the LDO comprises an internal input end, a variable resistor, an output end, an error amplifier and an internal reference source VrefAnd ground terminal and external divider resistor and divider resistor RrefFilter capacitor CequAnd a bleed-off resistance R;
    the input end and the error amplifier are connected with the variable resistor, the divider resistor is connected with the output end and the negative end of the error amplifier, and the divider resistor RrefA filter capacitor C connected with the negative terminal and the ground terminal of the error amplifierequAnd a bleeder resistor R connected in parallel between the output terminal and the ground terminal, the positive terminal of the error amplifier and an internal reference source VrefConnecting;
    setting a voltage dividing resistance RrefAnd the total absorption current of the discharge resistor R is more than or equal to the sink current IsinkWhile a filter capacitor CequHas a large value and is in one line period tHInternal current IsinkDuring the duration of the current flowingsinkThe internal accumulated charge is less than or equal to the source current IsourceAt source current duration DeltatsourceDissipated charge and voltage dividing resistor RrefAnd the bleeder resistor R is in one line period tHConsumed charge, and the variation of the output peak voltage of the LDO output end is less than or equal to the maximum voltage delta V allowed by the detectormaxThe amplitude of variation;
    Figure FDA0002623053200000011
    Voutis the voltage of the LDO output.
  2. 2. The method of designing a TDICMOS imaging unit according to claim 1, wherein: the voltage signal output by the controller is transmitted to the TDICMOS detector after passing through the first matching resistor and the level shifter with the Schmidt function; the resistance value r of the first matching resistor is 50-rout，routIs the output resistance value of the controller; said voltage signal is transmittedThe overall input process is controlled according to a single-ended 50 ohm impedance.
  3. 3. The method of designing a TDICMOS imaging unit according to claim 1, wherein: the voltage signal output by the controller is converted into a level value required by the TDICMOS detector through the second matching resistor and the driver with the Schmitt function, the output end of the driver with the Schmitt function is connected with the third matching resistor, and the voltage signal is controlled according to the impedance of 50 ohms at a single end at the input end of the driver with the Schmitt function from the controller; the signal received at the output of the driver with Schmidt function to the TDICMOS probe follows an impedance Z of less than 50 ohms0Controlling; the resistance value of the third matching resistor is less than or equal to 10k omega.
  4. 4. The method of designing a TDICMOS imaging unit according to claim 3, wherein:
    the impedance Z0And the determination of the line width of the inner layer and the outer layer comprises the following steps;
    firstly, according to the magnitude of the peak driving current and the thickness t of an inner layer lead of the circuit boardcoreDetermining the line width w of the inner layer of the circuit boardcore；
    Secondly, according to the thickness t of the inner layer of the conducting wirecoreAnd line width w of the inner layercoreDetermination of the impedance Z0；
    Figure FDA0002623053200000021
    In the formula hcoreThe distance between two adjacent conducting layers of the inner layer is defined as the distance between the two adjacent conducting layers of the inner layer;
    thirdly, according to the determined impedance Z0And the thickness t of the surface layersurfaceDetermining the line width w of the surface layersurface；
    Figure FDA0002623053200000022
    In the formula hsurfaceIs a watchThe thickness of the medium under the layer.
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CN111510647B (en) * 2020-04-27 2021-08-31 中国科学院长春光学精密机械与物理研究所 Uniform charge transfer control method for multi-spectral-segment TDICMOS
CN111741243B (en) * 2020-06-23 2021-06-29 中国科学院长春光学精密机械与物理研究所 Non-uniform correction method for TDICMOS detector
CN113054642B (en) * 2021-04-21 2022-08-26 中国科学院长春光学精密机械与物理研究所 Power supply method of TDICMOS imaging system
CN113452939B (en) * 2021-06-29 2022-05-10 中国科学院长春光学精密机械与物理研究所 Imaging effect evaluation method under TDICMOS rolling row period

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US7923763B2 (en) * 2007-03-08 2011-04-12 Teledyne Licensing, Llc Two-dimensional time delay integration visible CMOS image sensor
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CN110058632A (en) * 2014-12-29 2019-07-26 意法半导体研发(深圳)有限公司 Low voltage difference amplifier
US10156862B2 (en) * 2015-12-08 2018-12-18 Dialog Semiconductor (Uk) Limited Output transistor temperature dependency matched leakage current compensation for LDO regulators
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