CN110034748A - The design method of TDICMOS imaging unit - Google Patents
The design method of TDICMOS imaging unit Download PDFInfo
- Publication number
- CN110034748A CN110034748A CN201910293610.8A CN201910293610A CN110034748A CN 110034748 A CN110034748 A CN 110034748A CN 201910293610 A CN201910293610 A CN 201910293610A CN 110034748 A CN110034748 A CN 110034748A
- Authority
- CN
- China
- Prior art keywords
- tdicmos
- detector
- schmidt
- imaging unit
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000003384 imaging method Methods 0.000 title claims abstract description 24
- 238000013461 design Methods 0.000 title claims abstract description 23
- 239000000523 sample Substances 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 17
- 238000012358 sourcing Methods 0.000 claims description 9
- 239000002344 surface layer Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 238000010521 absorption reaction Methods 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims 3
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 238000012546 transfer Methods 0.000 abstract description 4
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 abstract description 3
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000002835 absorbance Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
Abstract
The design method of TDICMOS imaging unit is related to a kind of design method of TDICMOS imaging unit, solves existing TDICMOS imaging unit design complexity, there is a problem of stability difference, including controller unit and detector cells；Control signal needed for the controller unit generates detector cells, and the digital image data of pick-up probe unit output；The detector cells include TDICMOS detector, transport and placing device, LDO, the driver with Schmidt's function and the level translator with Schmidt's function；The present invention is directed to pixel portion power supply, the transmission of digital input control signal, the processing of the producing method of electric charge transfer driving signal, the modes of emplacement of high-density region via hole and multilayer ground plane with drawing sink current respectively and is designed, that improves wiring board to the maximum extent utilizes area, the integrality of control driving signal and power supply is improved, while avoiding the risks such as voltage breakdown and rosin joint.
Description
Technical field
The present invention relates to a kind of design methods of TDICMOS imaging unit, and in particular to high under a kind of size-constrained environment
The design method of the TDICMOS imaging unit of reliability application.
Background technique
It not only include the photosensitive part of TDICCD detector for charge-domain TDICMOS imaging design, inside detector
With the grid of electric charge transfer, and correlated-double-sampling and D/A converting circuit, clock generator, biasing, SPI deposit are further comprised
Device and LVDS send and receive device etc., and funtion part is various.Since the funtion part of TDICMOS detector is various, TDICMOS at
As design complexity, careful design review (check) (DR) is needed, can guarantee reliablely and stablely to work.
Summary of the invention
The present invention is to solve existing TDICMOS imaging unit design complexity, there is a problem of stability difference, provides one kind
The design method of TDICMOS imaging unit.
The design method of TDICMOS imaging unit, the imaging unit include controller unit and detector cells；It is described
Control signal needed for controller unit generates detector cells, and the digital image data of pick-up probe unit output；Institute
Stating detector cells includes TDICMOS detector, transport and placing device, LDO, the driver with Schmidt's function and with Schmidt's function
Level translator；
The transport and placing device and LDO provide operating voltage for TDICMOS detector, and driver provides for TDICMOS detector
Driving signal, the level translator with Schmidt's function provide control signal for TDICMOS detector；The LDO includes inside
Input terminal, variable resistance, output end, error amplifier, internal reference source VrefWith ground terminal and outside divider resistance,
Divider resistance Rref, filter capacitor CequWith aerial drainage capacitor R；
The input terminal and error amplifier are connect with variable resistance, the divider resistance and output end and error amplifier
Negative terminal connection, divider resistance RrefIt is connect with the negative terminal of error amplifier and ground terminal, filter capacitor CequSimultaneously with aerial drainage capacitor R
Row is connected between output and ground, the anode and internal reference source V of the error amplifierrefConnection；
Set divider resistance RrefIt is more than or equal to sink current I with total absorption electric current of bleeder resistor Rsink, while filter capacitor
CequValue is very big, and in a row period tHInterior sink current IsinkIn sink current duration of Δ tsinkInterior accumulative charge is less than
Equal to sourcing current IsourceIn sourcing current duration of Δ tsourceThe charge and divider resistance R of consumptionrefAnd bleeder resistance R is one
A row period tHThe charge of consumption, while the variation of LDO output end output crest voltage is less than or equal to the maximum that detector allows
Voltage Δ VmaxAmplitude of variation；
VoutFor the voltage of LDO output.
Beneficial effects of the present invention:
One, the present invention is given using LDO with the pixel portion power supply for drawing sink current, and the acquisition for avoiding high current amplifier is tired
Difficulty, LDO obtain convenient；On the one hand the sink current exported using special bleeder resistance come absorbance detector is avoided using LDO
The divider resistance of reference voltage end absorbs the problem of sink current bring resistance heating causes resistance value to be drifted about；On the other hand it can keep away
Exempting from sink current causes the voltage change amplitude of LDO output end excessive.
Two, controller exports higher voltage, can reduce the influence degree by external interference；Sealing in build-out resistor reduces
Liter and failing edge reduce to extraneous interference；Detector end uses the electrical level transferring chip with Schmidt's function, can reduce inhibition
Interference in transmission process；Signal transmission overall process is managed according to single-ended 50 Europe, can inhibit signal caused by impedance mismatch
Reflection.
Three, segment impedance control is carried out to driving signal, not only ensure that enough driving capabilities to detector, Er Qiebao
The impedance for having demonstrate,proved driving signal is continuous, avoids reflecting；
Four, the modes of emplacement of high-density region via hole, can improve wiring board to greatest extent utilizes area, keeps away simultaneously
The excessive caused breakdown of pressure difference or short circuit are exempted from.
Five, the processing of multilayer ground plane, it is ensured that the integrality of signal and power supply, while avoiding going out in welding process
Existing rosin joint.
Detailed description of the invention
Fig. 1 is the topology diagram of imaging unit in the design method of TDICMOS imaging unit of the present invention；
Fig. 2 is the principle that LDO draw sink current power supply in the design method of TDICMOS imaging unit of the present invention
Figure；
Fig. 3 is that the transmission of digital input control signal in the design method of TDICMOS imaging unit of the present invention is former
Manage block diagram；
Fig. 4 is that the generation of electric charge transfer driving signal in the design method of TDICMOS imaging unit of the present invention is former
Reason figure；
Fig. 5 is the modes of emplacement of the design method middle-high density region via hole of TDICMOS imaging unit of the present invention
Schematic diagram.
Specific embodiment
Specific embodiment one illustrates present embodiment in conjunction with Fig. 1 to Fig. 5, the design method of TDICMOS imaging unit,
Including controller unit and probe unit two parts.It is applied in detector cells comprising TDICMOS detector, transport and placing device, LDO, band
The driver and level translator with Schmidt's function of close spy's function.Control needed for controller unit generates detector cells
Signal, and the digital image data of pick-up probe unit output.Operating voltage needed for transport and placing device and LDO generate detector,
Driving signal needed for driver with Schmidt's function generates TDICMOS detector, the level translator with Schmidt's function
Control signal needed for generating TDICMOS detector.
In present embodiment, there is the pixel portion power supply for drawing sink current to use two ways, first way is existing
Mode, generated using " a reference source+Low Drift Temperature divider resistance+high current amplifier " mode；It is required that the maximum of high current amplifier
Sourcing current, which is greater than, loads maximum sourcing current Isource_max2 times, maximum allowable sink current be greater than load maximum sink current
Isink_max2 times.
Second way combination Fig. 2 is generated by the way of " LDO+ bleeder resistor+filter capacitor ".Conventional LDO is only
Has the ability of sourcing current, without having the ability of sink current.The LDO includes internal input terminal, variable resistance, output
End, error amplifier, internal reference source VrefWith ground terminal and the divider resistance of outside, divider resistance Rref, filter capacitor Cequ
With aerial drainage capacitor R；
The input terminal and error amplifier are connect with variable resistance, the divider resistance and output end and error amplifier
Negative terminal connection, divider resistance RrefIt is connect with the negative terminal of error amplifier and ground terminal, filter capacitor CequSimultaneously with aerial drainage capacitor R
Row is connected between output and ground, the anode and internal reference source V of the error amplifierrefConnection；It is electric when occurring drawing
When flowing and the voltage of output end being caused to decline, error amplifier output is high level, opens output；And it is greater than when there is sink current
When circuit itself consumes electric current, the voltage on capacitor is increased, and error amplifier output is low level, disconnects output, not
Electric current can be absorbed, voltage value still will continue to increase.
Therefore setting divider resistance RrefIt is more than or equal to sink current I with total absorption electric current of bleeder resistor Rsink, filter simultaneously
Capacitor CequValue is very big, and in a row period tHInterior sink current IsinkIn sink current duration of Δ tsinkInterior accumulative charge
Less than or equal to sourcing current IsourceIn sourcing current duration of Δ tsourceThe charge and divider resistance R of consumptionrefAnd bleeder resistance R
In a row period tHThe charge of consumption, while the variation of LDO output end output crest voltage is less than or equal to what detector allowed
Maximum voltage Δ VmaxAmplitude of variation；
VoutFor the voltage of LDO output.
Embodiment is described with reference to Fig. 3, in present embodiment, the transmission mode of digital input control signal are as follows: for
Remote transmission, controller exports higher voltage reduction to be influenced by external interference, usually seals in resistance value no more than 50 Europe (r
=50-rout) the first build-out resistor reduction rising and falling edges, reduce to extraneous interference；Detector end uses band Schmidt's function
The level translator of energy is converted to required level value, and signal transmission overall process is managed according to single-ended 50 Europe.routFor controller
Output resistance.
Embodiment is described with reference to Fig. 4, in present embodiment, the producing method of electric charge transfer driving signal are as follows: control
Device, which exports higher voltage, reduces the influence of interference, usually seals in resistance value no more than 50 Europe (r=50-rout) the second build-out resistor
Rising and falling edges are reduced, are reduced to neighbouring interference；Detector end is converted to using the driver with Schmidt's function
Level value required for TDICMOS detector, the resistance value that the output end of driver seals in the reduction rising and falling edges time do not surpass
Cross the third build-out resistor of 10k.In the input terminal of controller to driver, signal is managed according to single-ended 50 Europe；Driver
The signal of TDICMOS detector is output to according to the impedance Z less than 50 Europe0It is managed.
The impedance Z0Steps are as follows for determination with ectonexine line width；
(1) according to the inner conductor thickness t of the size of peak drive current and wiring boardcore, determine the internal layer of wiring board
Line width wcore；
(2) according to the conductor thickness t of internal layercoreWith the line width w of internal layercoreDetermine impedance Z0；
H in formulacoreFor the distance of adjacent two conductive layer of the internal planes；wcoreFor the line width of internal layer；tcoreFor the conducting wire of internal layer
Thickness；
(3) according to determining impedance Z0With the conductor thickness t on surface layersurface, determine the line width w on surface layersurface。
H in formulasurfaceFor the thickness of the medium under surface layer；wsurfaceFor the line width on surface layer；tsurfaceIt is thick for the conducting wire on surface layer
Degree.
In present embodiment, the modes of emplacement of high-density region via hole on wiring board are as follows: for the mistake being connected with pad A
Hole, the white space that can be placed in Fig. 5 (a) figure；It can not be beaten in capacitor encapsulation without connecting via hole with pad A and B
It close to the position of pad, is placed on outside device encapsulation, if being placed in device, it is proposed that far from pad, close to capacitor element center
Position, such as the white space of Fig. 5 (b).
The pressure difference of the safe distance wtAB (mm) of the via hole and pad B that are wherein connected with pad A >=and pad A and B network
×0.013mm/V；
Safe distance wtA (the mm) >=mistake pore network and pad A net of the via hole and pad A that are not connected simultaneously with pad A and B
Pressure difference × 0.013mm/V of network；
Safe distance wtB (the mm) >=mistake pore network and pad B net of the via hole and pad B that are not connected simultaneously with pad A and B
Pressure difference × 0.013mm/V of network.
In present embodiment, the processing mode of the multilayer ground plane of wiring board are as follows: in order to guarantee the signal of rigid-flex board with
Power Integrity scratches for every and takes in two layers one layer as ground reference planes.In order to avoid multilayer ground level is connected with direct inserting device,
Cause to radiate too fast in welding process and rosin joint occur, thus will scratch three layers of the ground level with outermost two layers and middle layer with
The ground pin connection of direct plug-in element, and the ground level of remainder layer is not connected with the ground pin of direct inserting device；In order to avoid
Nearby ground plane layer becomes isolated island to direct inserting device, and the clearance position near direct inserting device beats ground via and all stratum are connected
It is connected together.
In present embodiment, cmos detector uses the TDICMOS product of Chang Guangchen core company；LDO is using TI company
TPS7H1101；Transport and placing device uses the AD8629 of ADI company；Driver uses the ISL7457 of intersil company；Band Schmidt
The level translator of function uses the 54AC163245 of ST company.
Claims (4)
- The design method of 1.TDICMOS imaging unit, the imaging unit include controller unit and detector cells；The control Control signal needed for device unit processed generates detector cells, and the digital image data of pick-up probe unit output；It is described Detector cells include TDICMOS detector, transport and placing device, LDO, the driver with Schmidt's function and the electricity with Schmidt's function Flat turn parallel operation；The transport and placing device and LDO provide operating voltage for TDICMOS detector, and driver provides driving for TDICMOS detector Signal, the level translator with Schmidt's function provide control signal for TDICMOS detector；It is characterized in that；The LDO includes internal input terminal, variable resistance, output end, error amplifier, internal reference source VrefAnd ground terminal And divider resistance, the divider resistance R of outsideref, filter capacitor CequWith aerial drainage capacitor R；The input terminal and error amplifier are connect with variable resistance, the divider resistance and output end and error amplifier it is negative End connection, divider resistance RrefIt is connect with the negative terminal of error amplifier and ground terminal, filter capacitor CequConnect parallel with aerial drainage capacitor R It connects between output and ground, the anode and internal reference source V of the error amplifierrefConnection；Set divider resistance RrefIt is more than or equal to sink current I with total absorption electric current of bleeder resistor Rsink, while filter capacitor CequValue It is very big, and in a row period tHInterior sink current IsinkIn sink current duration of Δ tsinkInterior accumulative charge is less than or equal to Sourcing current IsourceIn sourcing current duration of Δ tsourceThe charge and divider resistance R of consumptionrefAnd bleeder resistance R is in a row Period tHThe charge of consumption, while the variation of LDO output end output crest voltage is less than or equal to the maximum voltage that detector allows ΔVmaxAmplitude of variation；VoutFor the voltage of LDO output.
- 2. the design method of TDICMOS imaging unit according to claim 1, it is characterised in that: further include the first matching Resistance, the voltage signal of controller output are sent to after the first build-out resistor and level translator with Schmidt's function TDICMOS detector；The resistance value r=50-r of first build-out resistorout, routFor the output resistance of controller；The electricity Pressure signal transmission overall process is controlled according to single-ended impedance according to 50 Europe.
- 3. the design method of TDICMOS imaging unit according to claim 1, it is characterized in that: further including the second matching electricity Resistance and third build-out resistor, driver of the voltage signal through the second build-out resistor and with Schmidt's function of the controller output The level value of TDICMOS detector needs is converted to, the output end of the driver with Schmidt's function connects third build-out resistor, In controller to the input terminal of the driver with Schmidt's function, voltage signal is controlled according to single-ended impedance according to 50 Europe； In the driver output end with Schmidt's function to TDICMOS detector received signal according to the impedance Z less than 50 Europe0It carries out Control；The resistance value of third build-out resistor is less than or equal to 10k Ω.
- 4. the design method of TDICMOS imaging unit according to claim 3, it is characterised in that:The impedance Z0Steps are as follows for determination with ectonexine line width；One, according to the inner conductor thickness t of the size of peak drive current and wiring boardcore, determine the line width of the internal layer of wiring board wcore；Two, according to the conductor thickness t of internal layercoreWith the line width w of internal layercoreDetermine impedance Z0；H in formulacoreFor the distance of adjacent two conductive layer of the internal planes；Three, according to determining impedance Z0With the conductor thickness t on surface layersurface, determine the line width w on surface layersurface；H in formulasurfaceFor the thickness of the medium under surface layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910293610.8A CN110034748B (en) | 2019-04-12 | 2019-04-12 | Design method of TDICMOS imaging unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910293610.8A CN110034748B (en) | 2019-04-12 | 2019-04-12 | Design method of TDICMOS imaging unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110034748A true CN110034748A (en) | 2019-07-19 |
| CN110034748B CN110034748B (en) | 2020-10-16 |
Family
ID=67238167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910293610.8A Expired - Fee Related CN110034748B (en) | 2019-04-12 | 2019-04-12 | Design method of TDICMOS imaging unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110034748B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510647A (en) * | 2020-04-27 | 2020-08-07 | 中国科学院长春光学精密机械与物理研究所 | Uniform charge transfer control method for multi-spectral-segment TDICMOS |
| CN111741243A (en) * | 2020-06-23 | 2020-10-02 | 中国科学院长春光学精密机械与物理研究所 | Non-uniform correction method for TDICMOS detector |
| CN113054642A (en) * | 2021-04-21 | 2021-06-29 | 中国科学院长春光学精密机械与物理研究所 | Power supply method of TDICMOS imaging system |
| CN113452939A (en) * | 2021-06-29 | 2021-09-28 | 中国科学院长春光学精密机械与物理研究所 | Imaging effect evaluation method under TDICMOS rolling line period |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080217661A1 (en) * | 2007-03-08 | 2008-09-11 | Teledyne Licensing, Llc | Two-dimensional time delay integration visible cmos image sensor |
| CN103546729A (en) * | 2013-10-24 | 2014-01-29 | 天津大学 | Gray-color dual-mode TDI-CMOS image sensor and control method |
| US20160187902A1 (en) * | 2014-12-29 | 2016-06-30 | STMicroelectronics (Shenzhen) R&D Co. Ltd | Two-stage error amplifier with nested-compensation for ldo with sink and source ability |
| CN107451957A (en) * | 2017-07-26 | 2017-12-08 | 国家测绘地理信息局卫星测绘应用中心 | A kind of spaceborne TDI CMOS camera imagings emulation mode and equipment |
| CN108776502A (en) * | 2018-06-26 | 2018-11-09 | 南京微盟电子有限公司 | A kind of reverse-filling protection circuit of LDO linear voltage regulators |
| CN108965752A (en) * | 2018-06-22 | 2018-12-07 | 中国科学院长春光学精密机械与物理研究所 | Virtual big completely trap TDI cmos imaging system based on small pixel dimension detector |
| US10156862B2 (en) * | 2015-12-08 | 2018-12-18 | Dialog Semiconductor (Uk) Limited | Output transistor temperature dependency matched leakage current compensation for LDO regulators |
-
2019
- 2019-04-12 CN CN201910293610.8A patent/CN110034748B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080217661A1 (en) * | 2007-03-08 | 2008-09-11 | Teledyne Licensing, Llc | Two-dimensional time delay integration visible cmos image sensor |
| CN103546729A (en) * | 2013-10-24 | 2014-01-29 | 天津大学 | Gray-color dual-mode TDI-CMOS image sensor and control method |
| US20160187902A1 (en) * | 2014-12-29 | 2016-06-30 | STMicroelectronics (Shenzhen) R&D Co. Ltd | Two-stage error amplifier with nested-compensation for ldo with sink and source ability |
| US10156862B2 (en) * | 2015-12-08 | 2018-12-18 | Dialog Semiconductor (Uk) Limited | Output transistor temperature dependency matched leakage current compensation for LDO regulators |
| CN107451957A (en) * | 2017-07-26 | 2017-12-08 | 国家测绘地理信息局卫星测绘应用中心 | A kind of spaceborne TDI CMOS camera imagings emulation mode and equipment |
| CN108965752A (en) * | 2018-06-22 | 2018-12-07 | 中国科学院长春光学精密机械与物理研究所 | Virtual big completely trap TDI cmos imaging system based on small pixel dimension detector |
| CN108776502A (en) * | 2018-06-26 | 2018-11-09 | 南京微盟电子有限公司 | A kind of reverse-filling protection circuit of LDO linear voltage regulators |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510647A (en) * | 2020-04-27 | 2020-08-07 | 中国科学院长春光学精密机械与物理研究所 | Uniform charge transfer control method for multi-spectral-segment TDICMOS |
| CN111510647B (en) * | 2020-04-27 | 2021-08-31 | 中国科学院长春光学精密机械与物理研究所 | Uniform charge transfer control method for multi-spectral-segment TDICMOS |
| CN111741243A (en) * | 2020-06-23 | 2020-10-02 | 中国科学院长春光学精密机械与物理研究所 | Non-uniform correction method for TDICMOS detector |
| CN111741243B (en) * | 2020-06-23 | 2021-06-29 | 中国科学院长春光学精密机械与物理研究所 | Non-uniform correction method for TDICMOS detector |
| CN113054642A (en) * | 2021-04-21 | 2021-06-29 | 中国科学院长春光学精密机械与物理研究所 | Power supply method of TDICMOS imaging system |
| CN113452939A (en) * | 2021-06-29 | 2021-09-28 | 中国科学院长春光学精密机械与物理研究所 | Imaging effect evaluation method under TDICMOS rolling line period |
| CN113452939B (en) * | 2021-06-29 | 2022-05-10 | 中国科学院长春光学精密机械与物理研究所 | Imaging effect evaluation method under TDICMOS rolling row period |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110034748B (en) | 2020-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110034748A (en) | The design method of TDICMOS imaging unit | |
| US7408256B2 (en) | Integrated circuit chip module | |
| US7035302B2 (en) | Optical transmission module | |
| JP2015019137A (en) | Receiving circuit and transmitting circuit, and communication system and communication method | |
| CN107707277B (en) | Oil well communication system based on broadband power line carrier communication | |
| US6021499A (en) | Isolated ground reference DC power supply | |
| EP1602998A1 (en) | Voltage regulator with multiple feedback | |
| US20100115349A1 (en) | Misalignment compensation for proximity communication | |
| JPS61283981A (en) | Integrated circuit card | |
| JP4275583B2 (en) | Electronic module | |
| CN101983003A (en) | Circuit board | |
| Kovacs et al. | Front-end hybrid designs for the CMS Phase-2 Upgrade towards the production phase | |
| CN211859070U (en) | Power supply station and connector device thereof | |
| CN104267572B (en) | A kind of projection screen and optical projection system | |
| CN209150335U (en) | Link block between PCBA board | |
| JP2012230176A (en) | Optical module | |
| JP2008277332A (en) | Communication substrate and semiconductor integrated circuit | |
| US11533077B2 (en) | Pseudo-differential signaling for modified single-ended interface | |
| CN113128170B (en) | Via hole structure implementation method and device for effectively compensating capacitive sudden change | |
| CN220457407U (en) | Electric power and communication shared cable transmission architecture and electric surfboard | |
| CN201345561Y (en) | Conversion framework of redundant electric power system | |
| CN114658412B (en) | Logging device and logging system | |
| Loh et al. | Capacitive proximity communication with distributed alignment sensing for origami biomedical implants | |
| US11454997B2 (en) | Dynamic voltage compensation circuit and method thereof | |
| TWI539292B (en) | Usb external device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20201016 |