CN110032792A - A kind of superconducting digital circuits design method - Google Patents
A kind of superconducting digital circuits design method Download PDFInfo
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- CN110032792A CN110032792A CN201910278235.XA CN201910278235A CN110032792A CN 110032792 A CN110032792 A CN 110032792A CN 201910278235 A CN201910278235 A CN 201910278235A CN 110032792 A CN110032792 A CN 110032792A
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- G06F30/30—Circuit design
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Abstract
The present invention provides a kind of superconducting digital circuits design method, comprising: the design requirement of based superconductive digital circuit carries out generative circuit design netlist after the design of system architecture Design and Features；Magnetic flux storage capacity detection is carried out to all of the port of all element circuits on any data access in the circuit design netlist, and when port has magnetic flux storage capacity, a buffer cell is added at the port, the timing optimization to the circuit design netlist is realized with this, to obtain terminating circuit design netlist；Superconducting digital circuits domain is generated after carrying out logical function verification and timing verification to the terminating circuit design netlist, and physical verification is carried out to the superconducting digital circuits domain to complete superconducting digital circuits design.When solving the existing progress superconducting digital circuits design using cell library design method through the invention, the lower problem of superconducting digital circuits Time-Series analysis accuracy because caused by same superconduction digital units circuit is followed by different loads.
Description
Technical field
The present invention relates to superconducting digital circuits fields, more particularly to a kind of superconducting digital circuits design method.
Background technique
Single flux quantum device (SFQ:Single Flux Quantum) is to utilize the single magnetic flux in Josephson junction
Son is reachable to indicate the superconducting circuit technology of logical one He " 0 ", superconducting digital circuits clock frequency based on this
770GHz can be used for the ultra wide band D and D/A converter of radar and communication system, broadband network exchanger, radio astronomy
Digital autocorrelator and superconducting computer etc..
The discovery when the temporal characteristics parameter to a superconduction digital units circuit extracts, the same superconduction number are single
First circuit can show different temporal characteristics parameters (delay of such as superconduction digital units circuit, letter when connecing different loads
Number establish the time etc. used).It can be with and in the design of extensive superconducting digital circuits, after a superconduction digital units circuit
Different loads is connected, if the same superconduction digital units circuit is followed by the obtained temporal characteristics Parameters variation of different loads
Very big, this variation will have a direct impact on the accuracy to Time-Series analysis in a data transmission path (path).Because when
What the specific time that sequence analysis mainly leans on signal to reach was judged, and the variation of signal time delay will lead to Time-Series analysis knot
The inaccuracy of fruit, therefore will limit the working performance that superconducting digital circuits are applied in high frequency.In consideration of it, it is necessary to design one
The new superconducting digital circuits design method of kind is with to solve the above technical problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of superconducting digital circuits design sides
Method, when for solving the existing progress superconducting digital circuits design using cell library design method, because of same superconduction digital units electricity
Road is followed by the problem that superconducting digital circuits Time-Series analysis accuracy is lower caused by different loads.
In order to achieve the above objects and other related objects, the present invention provides a kind of superconducting digital circuits design method, described
Design method includes:
The design requirement of based superconductive digital circuit carries out generative circuit design grid after the design of system architecture Design and Features
Table；
Magnetic flux is carried out to all of the port of all element circuits on any data access in the circuit design netlist
Storage capacity detection, and when port has magnetic flux storage capacity, a buffer cell is added at the port, is realized with this to institute
The timing optimization of circuit design netlist is stated, to obtain terminating circuit design netlist；
Superconducting digital circuits version is generated after carrying out logical function verification and timing verification to the terminating circuit design netlist
Figure, and physical verification is carried out to the superconducting digital circuits domain to complete superconducting digital circuits design.
Optionally, the design method further includes the steps that establishing cell library before carrying out system architecture design；Wherein
The step of establishing cell library include:
Establish the circuit graph model, circuit function descriptive model and temporal model of each unit circuit, while foundation and circuit
Graph model, circuit function descriptive model and the corresponding netlist of temporal model；
Magnetic flux storage capacity judgement is carried out to all of the port in each unit circuit, and in port there is magnetic flux to store energy
When power, magnetic flux mark is set, to realize the foundation of cell library in the netlist corresponding to the port.
Optionally, the method for magnetic flux storage capacity judgement is carried out to all of the port in each unit circuit includes: to be based on
Whether the working principle judgement nearest Josephson junction in parallel with its each port of each unit circuit is located in magnetic flux store loop,
And when nearest Josephson junction in parallel with port is located in magnetic flux store loop, determine that there is magnetic flux to store energy for the port
Power.
Optionally, to all of the port of all element circuits on any data access in the circuit design netlist into
The method of row magnetic flux storage capacity detection includes: to identify in netlist corresponding to each port of each unit circuit whether there is magnetic flux
When indicating, and there is magnetic flux mark in the netlist corresponding to port, the port is detected with magnetic flux storage capacity.
Optionally, to all of the port of all element circuits on any data access in the circuit design netlist into
The method of row magnetic flux storage capacity detection includes: that the working principle judgement based on each unit circuit is in parallel with its each port nearest
Whether Josephson junction is located in magnetic flux store loop, and is located at magnetic flux storage ring in nearest Josephson junction in parallel with port
When in road, the port is detected with magnetic flux storage capacity.
Optionally, the buffer cell includes josephson transmission line.
Optionally, the josephson transmission line includes: the first inductance, the second inductance, bias current sources and Josephson
Knot, wherein input terminal or output end of the one end of first inductance as the port, the other end of first inductance connects
It is connected to one end of second inductance, the other end of second inductance is connected to the port, one end of second inductance
The bias current sources are connected to, while being connected to one end of the Josephson junction, another termination of the Josephson junction
Ground.
Optionally, the method for carrying out logical function verification to the terminating circuit design netlist includes: to the terminal electricity
Road design netlist carries out logical function verification, whether to judge the terminating circuit design netlist according to logical function verification result
Meet logic function design requirement；When the logical function verification result does not meet logic function design requirement, readjust
The Functional Design is until the logical function verification result meets logic function design requirement；In the logical function verification knot
When fruit meets logic function design requirement, timing verification is carried out to the terminating circuit design netlist.
Optionally, the method for carrying out timing verification to the terminating circuit design netlist includes: to set to the terminating circuit
It counts netlist and carries out timing verification, to judge whether the terminating circuit design netlist meets timing Design according to timing verification result
It is required that；When the timing verification result does not meet timing Design requirement, the Functional Design is readjusted until the timing
Verification result meets timing Design requirement；When the timing verification result meets timing Design requirement, superconduction number electricity is generated
Road domain.
Optionally, the method for carrying out physical verification to the superconducting digital circuits domain includes: to the superconduction number electricity
Road domain carries out physical verification, to judge whether the superconducting digital circuits domain meets physical Design according to physical verification result
It is required that；The physical verification result do not meet physical Design require when, readjust the superconducting digital circuits domain until
The physical verification result meets physical Design requirement.
Optionally, the physical verification includes design rule check.
Optionally, the physical verification further include: the comparison of superconducting digital circuits domain and superconducting digital circuits schematic diagram
Verifying.
As described above, a kind of superconducting digital circuits design method of the invention, by each unit in superconducting digital circuits
The all of the port of circuit carries out magnetic flux storage capacity judgement, and buffering list is added at the port with magnetic flux storage capacity
Member is stablized with carrying out timing to the port with magnetic flux storage capacity, prevents its influence to previous stage element circuit timing, from
And it realizes and timing optimization is carried out to global circuit design netlist.As it can be seen that the superconducting digital circuits design provided through the invention
Method not only realizes the timing optimization of superconducting digital circuits, but also by increasing at the port with magnetic flux storage capacity
If buffer cell, remain unchanged simultaneously for the port for not having magnetic flux storage capacity, so as to avoid the institute to element circuit
Have and all add unnecessary resource consumption brought by buffer cell at port, improves the integrated level of chip, reduce chip
Area.
Detailed description of the invention
Fig. 1 is shown as the design flow diagram of superconducting digital circuits of the present invention.
Fig. 2 is shown as the structural schematic diagram of a data access in the superconducting digital circuits.
Fig. 3 to Fig. 7 is shown as the structural schematic diagram of different loads circuit, and wherein Fig. 3 is the structural representation of trigger D22
Figure, Fig. 4 is or the structural schematic diagram of door, Fig. 5 are the structural schematic diagram of RS latch, and Fig. 6 is the structural schematic diagram of XOR gate, figure
7 be the structural schematic diagram of trigger D12.
Fig. 8 is shown as the Delay Variation schematic diagram for the driving circuit that each load circuit particular port connects with Fig. 9.
Figure 10 to Figure 14 is shown as structural schematic diagram when adding buffer cell at each load circuit particular port.
Figure 15 is shown as the Delay Variation schematic diagram for the driving circuit that each load circuit particular port connects with Figure 16, at this time
Buffer cell is had additional at each load circuit particular port.
Component label instructions
100 driving sources
200 transmission lines
300 driving circuits
400 load circuits
500 buffer cells
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 16.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
Embodiment one
As shown in Figure 1, the present embodiment provides a kind of superconducting digital circuits design method, the design method includes:
Step 1: the design requirement of based superconductive digital circuit carries out generative circuit after the design of system architecture Design and Features
Design netlist.
As an example, the system architecture design is that superconducting digital circuits designer sets according to the structure that design requirement carries out
Meter, i.e., be described as several typical logical devices interconnected for superconducting digital circuits, wherein typical logical device packet
Include arithmetic operation unit (adder, multiplier etc.), register, counter etc..It should be noted that superconducting digital circuits design
The system architecture design that person completes according to different design requirement is different, at the same different superconducting digital circuits designers according to
The system architecture design that same design requirement is completed may also be different.
As an example, the Functional Design is that superconducting digital circuits designer sets according to the circuit function that design requirement carries out
Meter, is the relationship defined between input/output port and input/output port by writing scripting language, to realize super
The corresponding function of conducts digital circuit.
As an example, after completing system architecture design and Functional Design, it is raw according to system architecture design and Functional Design
It is known in those skilled in the art at circuit design netlist, therefore details are not described herein.
As an example, the design method further includes the steps that establishing cell library before carrying out system architecture design；Its
In the step of establishing cell library include:
Establish the circuit graph model, circuit function descriptive model and temporal model of each unit circuit, while foundation and circuit
Graph model, circuit function descriptive model and the corresponding netlist of temporal model；
Magnetic flux storage capacity judgement is carried out to all of the port in each unit circuit, and in port there is magnetic flux to store energy
When power, magnetic flux mark is set, to realize the foundation of cell library in the netlist corresponding to the port.
Specifically, establishing the circuit graph model, circuit function descriptive model and timing of each unit circuit based on element circuit
Model, while establishing netlist corresponding with circuit graph model, circuit function descriptive model and temporal model is those skilled in the art
Well known to member, therefore details are not described herein.It should be noted that element circuit described in the present embodiment, which refers to, constitutes superconduction number electricity
Most basic circuit unit when road, such as trigger or door, XOR gate.
Specifically, carrying out the method for magnetic flux storage capacity judgement to all of the port in each unit circuit includes: to be based on
Whether the working principle judgement nearest Josephson junction in parallel with its each port of each unit circuit is located in magnetic flux store loop,
And when nearest Josephson junction in parallel with port is located in magnetic flux store loop, determine that there is magnetic flux to store energy for the port
Power.Such as: for trigger D22 shown in Fig. 3, when the port AI input pulse signal, Josephson junction JA1, inductance LA2
A flux quantum can be stored with the magnetic flux store loop of Josephson junction JO1 composition；When the port TI input clock signal, magnetic
The flux quantum stored in logical store loop can be released, i.e. the port TO output pulse signal；It is in parallel with the port AI at this time most
The close Josephson junction JA1 and nearest Josephson junction JO1 in parallel with the port TO is form magnetic flux store loop one
Part, therefore think that the port AI and the port TO have magnetic flux storage capacity；And the nearest Josephson junction JT1 in parallel with the port TI
It is not to form a part of magnetic flux store loop, therefore think that the port TI does not have magnetic flux storage capacity.Similarly, for Fig. 4 institute
Show or Men Eryan, when the port AI or the port BI input pulse signal, Josephson junction JO2, inductance LO2, Josephson junction
The magnetic flux store loop of JO1 composition can store a flux quantum；When the port TI input clock signal, in magnetic flux store loop
The flux quantum of storage can be released, i.e. the port ABO output pulse signal；Nearest Josephson in parallel with the port AI at this time
Tie JA1, the nearest Josephson junction JB1 in parallel with the port BI and the nearest Josephson junction JT1 in parallel with the port TI simultaneously
Non- is a part for forming magnetic flux store loop, therefore thinks that the port AI, the port BI and the port TI do not have magnetic flux storage capacity；And
The nearest Josephson junction JO1 in parallel with the port ABO is a part for forming magnetic flux store loop, therefore thinks that the port ABO has
There is magnetic flux storage capacity.Similarly, for RS latch shown in fig. 5, when the port SI input pulse signal, Josephson
A flux quantum can be stored in the magnetic flux store loop that knot JL2, inductance LLR1, inductance LR3, Josephson junction JR3 are formed；When
When the input clock signal of the port RI, the flux quantum stored in magnetic flux store loop can be released, i.e. the port CO1 output pulse letter
Number.The nearest end Josephson junction JT1, CO1 of the nearest port Josephson junction JL0, RI parallel connection of the port SI parallel connection at this time
The nearest port the Josephson junction JT0 and TNRO parallel connection in parallel of the mouth nearest port Josephson junction JR5, TNRI in parallel
Nearest Josephson junction JT4 is not to form a part of magnetic flux store loop, therefore think the port SI, the port RI, the end CO1
Mouth, the port TNRI and the port TNRO do not have magnetic flux storage capacity.Similarly, for XOR gate shown in fig. 6, when the port AI
When input pulse signal, Josephson junction JA2, Josephson junction JA3, inductance LA2, inductance LAB1, Josephson junction JT3, about
A flux quantum can be stored in the magnetic flux store loop of Se Fusen knot JT2 composition；When the port TI input clock signal, magnetic flux
The flux quantum stored in store loop can be released, i.e. the port TO output pulse signal；And work as the port BI input pulse signal
When, Josephson junction JB2, Josephson junction JB3, inductance LB2, inductance LAB1, Josephson junction JT3, Josephson junction JT2 group
At magnetic flux store loop in can store a flux quantum；When the port TI input clock signal, deposited in magnetic flux store loop
The flux quantum of storage can be released, i.e. the port TO output pulse signal；Nearest Josephson junction in parallel with the port AI at this time
JA2, the nearest Josephson junction JB2 in parallel with the port BI, the nearest Josephson junction JT3 and and TO in parallel with the port TI
The nearest Josephson junction JT2 of port parallel connection is to form a part of magnetic flux store loop, therefore think the port AI, the end BI
Mouth, the port TI and the port TO have magnetic flux storage capacity.Similarly, for trigger D12 shown in Fig. 7, when the port AI is defeated
When entering pulse signal, the magnetic flux store loop of Josephson junction JA1, inductance LA2 and Josephson junction JO1 composition can store one
Flux quantum；When the port TI input clock signal, the flux quantum stored in magnetic flux store loop can be released, i.e. the port TO
Output pulse signal；Nearest Josephson junction JA1 in parallel with the port AI at this time, the nearest Joseph in parallel with the port TI
The gloomy knot JO1 and nearest Josephson junction JO1 in parallel with the port TO is to form a part of magnetic flux store loop, therefore think
The port AI, the port TI and the port TO have magnetic flux storage capacity.
Specifically, the method for setting magnetic flux mark includes: when port has magnetic flux storage capacity, corresponding to the port
Netlist in flag=1 is set, otherwise flag=0 is set, with this realize to magnetic flux storage capacity port carry out magnetic flux
Mark.Certainly, in other embodiments, magnetic flux mark can also be achieved by other means (such as to deposit in port with magnetic flux
When energy storage power, flag=0 is set in the netlist corresponding to the port, otherwise flag=1 is set), the present embodiment is not to magnetic
The specific implementation of logical mark is limited.
Step 2: to all of the port of all element circuits on any data access in the circuit design netlist into
The detection of row magnetic flux storage capacity, and when port has magnetic flux storage capacity, a buffer cell is added, at the port with this reality
Now to the timing optimization of the circuit design netlist, to obtain terminating circuit design netlist.
As an example, equal to all of the port of all element circuits on any data access in the circuit design netlist
The method for carrying out the detection of magnetic flux storage capacity includes: to identify in netlist corresponding to each port of each unit circuit whether there is magnetic
When leading to mark, and there is magnetic flux mark in the netlist corresponding to port, the port is detected with magnetic flux storage capacity.Such as at this
In embodiment, the value of flag in netlist corresponding to port is detected, if flag=1, then it is assumed that there is magnetic flux to store energy for the port
Power, otherwise it is assumed that the port does not have magnetic flux storage capacity.
As an example, the buffer cell includes josephson transmission line, wherein the josephson transmission line be with
The josephson transmission line of one Josephson junction.The present embodiment at the port with magnetic flux storage capacity by adding one
Buffer cell allows the buffer cell to effectively reduce the load circuit (port that the load circuit is connect with prime element circuit
With magnetic flux storage capacity) bias current reallocate influence to prime element circuit (i.e. driving circuit), to reduce negative
Carry influence of the circuit to the delay stability of time of driving circuit.
Specifically, the josephson transmission line includes: the first inductance, the second inductance, bias current sources and Josephson
Knot, wherein input terminal or output end of the one end of first inductance as the port, the other end of first inductance connects
It is connected to one end of second inductance, the other end of second inductance is connected to the port, one end of second inductance
The bias current sources are connected to, while being connected to one end of the Josephson junction, another termination of the Josephson junction
Ground.
Step 3: superconduction number is generated after carrying out logical function verification and timing verification to the terminating circuit design netlist
Circuit layout, and physical verification is carried out to the superconducting digital circuits domain to complete superconducting digital circuits design.
As an example, the method for carrying out logical function verification to the terminating circuit design netlist includes: to the terminal
Circuit design netlist carries out logical function verification, to judge that the terminating circuit design netlist is according to logical function verification result
It is no to meet logic function design requirement；When the logical function verification result does not meet logic function design requirement, adjust again
The whole Functional Design is until the logical function verification result meets logic function design requirement；In the logical function verification
When as a result meeting logic function design requirement, timing verification is carried out to the terminating circuit design netlist.
As an example, the method for carrying out timing verification to the terminating circuit design netlist includes: to the terminating circuit
Design netlist carries out timing verification, to judge whether the terminating circuit design netlist meets timing and set according to timing verification result
Meter requires；When the timing verification result does not meet timing Design requirement, the Functional Design is readjusted until when described
Sequence verification result meets timing Design requirement；When the timing verification result meets timing Design requirement, superconduction number is generated
Circuit layout.
Specifically, in the present embodiment, the script file of test signal is write to the terminating circuit design netlist first,
And the form of write pulse signal input in the script file of test signal；Pass through the emulation tools such as VCS, verdi later
Wave simulation is carried out, to judge whether the terminating circuit design netlist meets logic function by the waveform signal for observing output
It can design requirement；When it meets logic function design requirement, then judge whether it meets timing Design requirement.
As an example, after completing logical function verification and timing verification, according to the terminating circuit design netlist after verifying
It is known in those skilled in the art for generating superconducting digital circuits domain, therefore details are not described herein.
As an example, the method for carrying out physical verification to the superconducting digital circuits domain includes: to the superconduction number
Circuit layout carries out physical verification, to judge whether the superconducting digital circuits domain meets physics and set according to physical verification result
Meter requires；When the physical verification result does not meet physical Design requirement, it is straight to readjust the superconducting digital circuits domain
Meet physical Design requirement to the physical verification result.
Specifically, the physical verification includes design rule check；Design rule check described in the present embodiment refers to super
The design objective requirement of conducts digital circuit layout, such as the minimum range between conductor width, conducting wire, the most narrow spacing between different layers
From etc..Certainly, in other embodiments, the physical verification further includes superconducting digital circuits domain and superconducting digital circuits principle
The contrast verification of figure.
Embodiment two
The present embodiment and the distinctive points of embodiment one are: embodiment is first is that when establishing cell library first to each unit circuit
Port carry out magnetic flux storage capacity judgement, to be identified by magnetic flux mark to the port with magnetic flux storage capacity,
Then identify whether the port of each unit circuit in data path there is magnetic flux to store energy by magnetic flux mark in step 2
Power.And the present embodiment is then directly using existing cell library, then directly to each unit circuit in data path in step 2
Port carry out magnetic flux storage capacity judgement come realize detection, specific method includes: the working principle based on each unit circuit
Whether judgement nearest Josephson junction in parallel with its each port be located in magnetic flux store loop, and it is in parallel with port recently
When Josephson junction is located in magnetic flux store loop, the port is detected with magnetic flux storage capacity.
Below as shown in Fig. 2 to Figure 16, by taking different loads circuit as an example, by whether in the particular port of each load circuit
(including the port with magnetic flux storage capacity and the port without magnetic flux storage capacity) is added buffer cell and is come to embodiment
One and embodiment two described in design method feasibility carry out analytic explanation.
Five superconducting digital circuits as shown in Figure 2 are obtained by existing design method, wherein different superconducting digital circuits
Corresponding 400 structure of load circuit is different；As shown in Fig. 3 to Fig. 7, load circuit 400 is triggering in the first superconducting digital circuits
The port TI of device D22 and trigger D22 are connected to driving circuit 300, in the second superconducting digital circuits load circuit 400 be or
Door and or the port TI of door be connected to driving circuit 300, in third superconducting digital circuits load circuit 400 be RS latch and
The port RI of RS latch is connected to driving circuit 300, and load circuit 400 is XOR gate and different in the 4th superconducting digital circuits
Or the port TI of door is connected to driving circuit 300, load circuit 400 is trigger D12 and triggers in the 5th superconducting digital circuits
The port TI of device D12 is connected to driving circuit 300.
By carrying out experiment simulation to above-mentioned five kinds of superconducting digital circuits, the particular port of different loads circuit 400 is obtained
(the i.e. port TI of trigger D22 or the port TI of door, the port RI of RS latch, the port TI of XOR gate and trigger D12
The port TI) to the Delay Variation of same one drive circuit 300, wherein in the port TI or door that particular port is trigger D22
When the port TI or the port RI of RS latch, the time delay of driving circuit 300 is about 0.25ps, is XOR gate in particular port
When the port TI or the port TI of trigger D12, the time delay of driving circuit 300 is about 0.65ps, specific as shown in FIG. 8 and 9.It needs
It should be noted that the port TI of trigger D22 or the port TI of door and the port RI of RS latch do not have magnetic flux and store energy
Power, the port TI of XOR gate and the port TI of trigger D12 have magnetic flux storage capacity.
It can be seen that with one drive circuit 300 when connecing different port, driving circuit 300 because caused by each port when
Prolong variation it is different: when the port that driving circuit 300 is connect do not have magnetic flux storage capacity when, the driving circuit 300 when
Prolong and vary less, i.e., the driving circuit 300 will not be influenced (as shown in Figure 8) by the port；And connect when driving circuit 300
Port have magnetic flux storage capacity when, the driving circuit 300 work when timing can with port magnetic flux store state change and
Fluctuating change (as shown in Figure 9)；That is, state (0, the 1) variation just because of port magnetic flux store loop results in drive
The time delay of dynamic circuit 300 significantlys change.
By being redesigned to above-mentioned five superconducting digital circuits, and the particular port of each load circuit 400 (i.e.
The port TI or the port TI of door of trigger D22, the port RI of RS latch, the port TI of XOR gate and the TI of trigger D12
Port) buffer cell is added, it is specific as shown in FIG. 10 to 14.
By carrying out experiment simulation to above-mentioned five kinds of superconducting digital circuits, different particular ports are obtained to same one drive circuit
300 Delay Variation, wherein at the port TI of the port TI or door that particular port is trigger D22 or the end RI of RS latch
When mouth, the time delay of driving circuit 300 is about 0.20ps, the TI in the port TI or trigger D12 that particular port is XOR gate
When port, the time delay of driving circuit 300 is about 0.30ps, specific as shown in FIG. 11 and 12.
It can be seen that when the port that driving circuit 300 connects does not have magnetic flux storage capacity, even if adding one at port
Buffer cell 500, buffer cell 500 are also not obvious (as shown in figure 11) to the influence of the Delay Variation of driving circuit 300；And work as
When the port that driving circuit 300 connects has magnetic flux storage capacity, a buffer cell 500 is added at port may make driving circuit
300 Delay Variation more tends to stablize, and Delay Variation drops to 0.3ps (specific as shown in figure 12) from 0.65ps, stabilizes significantly
The timing of superconducting digital circuits, while it is feasible for also demonstrating design method of the present invention.
In conclusion a kind of superconducting digital circuits design method of the invention, by each unit in superconducting digital circuits
The all of the port of circuit carries out magnetic flux storage capacity judgement, and buffering list is added at the port with magnetic flux storage capacity
Member is stablized with carrying out timing to the port with magnetic flux storage capacity, prevents its influence to previous stage element circuit timing, from
And it realizes and timing optimization is carried out to global circuit design netlist.As it can be seen that the superconducting digital circuits design provided through the invention
Method not only realizes the timing optimization of superconducting digital circuits, but also by increasing at the port with magnetic flux storage capacity
If buffer cell, remain unchanged simultaneously for the port for not having magnetic flux storage capacity, so as to avoid the institute to element circuit
Have and all add unnecessary resource consumption brought by buffer cell at port, improves the integrated level of chip, reduce chip
Area.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of superconducting digital circuits design method, which is characterized in that the design method includes:
The design requirement of based superconductive digital circuit carries out generative circuit design netlist after the design of system architecture Design and Features；
Magnetic flux storage is carried out to all of the port of all element circuits on any data access in the circuit design netlist
Ability detection, and when port has magnetic flux storage capacity, a buffer cell is added at the port, is realized with this to the electricity
The timing optimization of road design netlist, to obtain terminating circuit design netlist；
Superconducting digital circuits domain is generated after carrying out logical function verification and timing verification to the terminating circuit design netlist, and
Physical verification is carried out to the superconducting digital circuits domain to complete superconducting digital circuits design.
2. superconducting digital circuits design method according to claim 1, which is characterized in that the design method is being
Further include the steps that establishing cell library before system architecture design；The step of wherein establishing cell library include:
The circuit graph model, circuit function descriptive model and temporal model of each unit circuit are established, while being established and circuit artwork
Type, circuit function descriptive model and the corresponding netlist of temporal model；
Magnetic flux storage capacity judgement is carried out to all of the port in each unit circuit, and there is magnetic flux storage capacity in port
When, magnetic flux mark is set in the netlist corresponding to the port, to realize the foundation of cell library.
3. superconducting digital circuits design method according to claim 2, which is characterized in that all in each unit circuit
The method that port carries out magnetic flux storage capacity judgement includes: that the working principle based on each unit circuit judges with its each port simultaneously
Join whether nearest Josephson junction is located in magnetic flux store loop, and is located at magnetic in nearest Josephson junction in parallel with port
When in logical store loop, determine that the port has magnetic flux storage capacity.
4. superconducting digital circuits design method according to claim 2, which is characterized in that in the circuit design netlist
The method that all of the port of all element circuits on any data access carries out magnetic flux storage capacity detection includes: that identification is each
Whether there is magnetic flux mark in netlist corresponding to each port of element circuit, and there is magnetic flux in the netlist corresponding to port
When mark, the port is detected with magnetic flux storage capacity.
5. superconducting digital circuits design method according to claim 1, which is characterized in that in the circuit design netlist
The method that all of the port of all element circuits on any data access carries out magnetic flux storage capacity detection includes: based on each
Whether the working principle judgement nearest Josephson junction in parallel with its each port of element circuit is located in magnetic flux store loop, and
When nearest Josephson junction in parallel with port is located in magnetic flux store loop, the port is detected with magnetic flux storage capacity.
6. superconducting digital circuits design method according to any one of claims 1 to 5, which is characterized in that the buffering is single
Member includes josephson transmission line.
7. superconducting digital circuits design method according to claim 6, which is characterized in that the josephson transmission line packet
It includes: the first inductance, the second inductance, bias current sources and Josephson junction, wherein one end of first inductance is as the end
The input terminal or output end of mouth, the other end of first inductance are connected to one end of second inductance, second inductance
The other end be connected to the port, one end of second inductance is connected to the bias current sources, while being connected to described
One end of Josephson junction, the other end ground connection of the Josephson junction.
8. superconducting digital circuits design method according to claim 1, which is characterized in that the terminating circuit design grid
The method that table carries out logical function verification includes: to carry out logical function verification to the terminating circuit design netlist, is patrolled with basis
It collects functional verification result and judges whether the terminating circuit design netlist meets logic function design requirement；In the logic function
When verification result does not meet logic function design requirement, the Functional Design is readjusted until the logical function verification result
Meet logic function design requirement；When the logical function verification result meets logic function design requirement, to the terminal
Circuit design netlist carries out timing verification.
9. superconducting digital circuits design method according to claim 1, which is characterized in that the terminating circuit design grid
The method that table carries out timing verification includes: to carry out timing verification to the terminating circuit design netlist, according to timing verification knot
Fruit judges whether the terminating circuit design netlist meets timing Design requirement；Timing is not met in the timing verification result to set
When meter requires, the Functional Design is readjusted until the timing verification result meets timing Design requirement；In the timing
When verification result meets timing Design requirement, superconducting digital circuits domain is generated.
10. superconducting digital circuits design method according to claim 1, which is characterized in that the superconducting digital circuits
The method that domain carries out physical verification includes: to carry out physical verification to the superconducting digital circuits domain, according to physical verification
As a result judge whether the superconducting digital circuits domain meets physical Design requirement；Physics is not met in the physical verification result
When design requirement, the superconducting digital circuits domain is readjusted until the physical verification result meets physical Design requirement.
11. superconducting digital circuits design method according to claim 10, which is characterized in that the physical verification includes setting
Meter rule checks.
12. superconducting digital circuits design method according to claim 11, which is characterized in that the physical verification also wraps
It includes: the contrast verification of superconducting digital circuits domain and superconducting digital circuits schematic diagram.
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