CN111460749B - Method and circuit for fine optimization of superconducting digital unit - Google Patents
Method and circuit for fine optimization of superconducting digital unit Download PDFInfo
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Abstract
The invention provides a fine optimization method and a circuit of a superconducting digital unit, which comprise the following steps: 1) Carrying out global optimization on the superconducting digital unit to be optimized to obtain a corresponding netlist and excitation information; 2) Sequentially performing grouping optimization on each index in the superconducting digital unit, if the optimization result is acceptable, updating the optimized parameter to a netlist, and then performing optimization on the next index, otherwise, directly performing optimization on the next index; 3) And updating the final optimization result to the circuit where the superconducting digital unit is located, and finishing curing. The invention takes the finely optimized process parameters into consideration in groups, saves time, can better converge and can more quickly obtain the optimal parameter collocation; after a certain acceptable parameter is obtained, the parameters of the components on the circuit diagram do not need to be changed, the optimization is carried out after the netlist is derived, the parameter is directly modified in the netlist, and then the next optimization link is entered, so that the time consumed by an optimization unit is further shortened, and errors possibly brought in multi-step operation are reduced.
Description
Technical Field
The invention relates to the field of design of superconducting digital units, in particular to a fine optimization method and a circuit of a superconducting digital unit.
Background
Compared with the current semiconductor integrated circuit, the superconducting circuit based on the rapid single magnetic flux quantum (RSFQ) has great advantages, achieves very rapid calculation speed with extremely low power consumption, designs and verifies some RSFQ microprocessors, and is concerned with application in the field of high-speed operation. The basis for the large-scale application of the RSFQ circuit is that a stable and reliable cell library is necessary, and it is critical that each cell in the library has stable and high performance.
The unit design of Single Flux Quanta (SFQ) is mainly based on three types of components: a resistor, a josephson junction and an inductor. The SFQ cell is powered by applying a bias voltage to the resistor and then supplying the bias voltage to the cell, so the actual appearance of the resistor in manufacture in the circuit diagram is the bias current of the circuit. Therefore, the optimization of the SFQ unit at present mainly involves the optimization of three parameters: a global bias current margin xi, a global josephson junction current margin xj, and a global inductance margin xl.
The existing optimization method for the circuit design of the SFQ unit is not disclosed in the literature, and general steps are relatively complicated and unit stability is poor, so how to further develop and perfect the optimization method for the circuit design of the SFQ unit becomes one of the problems to be solved by the technical staff in the field.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for fine optimization of a superconducting digital unit, which is used to solve the problems of complicated steps, poor unit stability, etc. existing in the optimization method of SFQ unit circuit design in the prior art.
To achieve the above and other related objects, the present invention provides a method for fine optimization of a superconducting digital unit, the method at least comprising:
1) Carrying out global optimization on the superconducting digital unit to be optimized to obtain a corresponding netlist and excitation information;
2) Sequentially performing grouping optimization on each index in the superconducting digital unit, if the optimization result is acceptable, updating the optimized parameter to the netlist, and then performing optimization on the next index, otherwise, directly performing optimization on the next index;
3) And updating the final optimization result to the circuit where the superconducting digital unit is located, and finishing curing.
Optionally, each indicator comprises a global bias current margin, a global josephson junction current margin, and a global inductance margin.
More optionally, the optimization order of each index is a global bias current margin, a global inductance margin, and a global josephson junction current margin in sequence.
Optionally, the indicators are grouped according to a bypass function.
More optionally, each index is divided into two groups, namely a clock branch and a signal branch.
Optionally, the criterion that the optimization result is acceptable is that the index to be optimized currently is optimized, and other indexes are not lower than a preset lower limit.
Optionally, the larger the parameter range of each index is and the better the balance is, the better the optimization result is considered.
More optionally, the global josephson junction current margin is optimized to a target of 20% above and below a first reference value, the global bias current margin is optimized to a target of 30% above and below a second reference value, and the global inductance margin is optimized to a target of 40% above and below a third reference value.
Optionally, step 3) is preceded by repeating step 2) until no better optimization result is obtained.
To achieve the above and other related objects, the present invention provides a fine optimization circuit of a superconducting digital unit, comprising at least:
a phase source, a superconducting digital unit to be optimized and a load;
the phase source is connected with the input end of the superconducting digital unit through a superconducting transmission line, the output end of the superconducting digital unit is connected with one end of the load through the superconducting transmission line, and the other end of the load is grounded through the superconducting transmission line.
Optionally, the superconducting digital unit comprises a non-destructive readout unit.
More optionally, the components of the fine optimization circuit of the superconducting digital unit include a resistor, a josephson junction, and an inductor.
As described above, the fine optimization method and circuit of the superconducting digital unit according to the present invention have the following advantages:
1. the fine optimization method and the circuit of the superconducting digital unit, provided by the invention, have the advantages that the fine optimization process parameters are considered in groups, the time is saved compared with the process parameters which are optimized together by tools, the convergence can be better realized, and the optimal parameter collocation can be obtained more quickly.
2. According to the fine optimization method and the circuit of the superconducting digital unit, after a certain acceptable parameter is obtained, the parameter of a component on a circuit diagram does not need to be changed, the netlist is exported, and then the process is optimized again, but the parameter is directly modified in the netlist and then enters the next optimization link, so that the time consumed by optimizing the unit, particularly a complex unit, can be further shortened, and errors possibly brought in multi-step operation can be reduced.
Drawings
Fig. 1 is a flow chart illustrating a method for fine optimization of a superconducting digital unit according to the present invention.
Fig. 2 is a schematic diagram of a circuit in which the superconducting digital unit of the present invention is located.
FIG. 3 is a schematic diagram showing a comparison between modified netlist and unmodified netlist under a simulation directory of the invention.
Fig. 4 is a schematic diagram showing the structure of a fine optimization circuit of the superconducting digital unit of the present invention.
Description of the element reference
1-step; 2-step; 21. 22, 23-step; 3-step; 4-a phase source; 5-superconducting digital unit; 6-load.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides a fine optimization method of a superconducting digital unit, including:
1) And carrying out global optimization on the superconducting digital unit to be optimized to obtain a corresponding netlist and excitation information.
Specifically, the superconducting digital unit to be optimized is globally optimized based on existing dedicated superconducting tools, including but not limited to PSCAN and PSCAN2.
By way of example, in the present embodiment, through global optimization of the tool, the indices of the superconducting digital unit at the highest frequency are as follows:
Margins for xi [31.32%，27.35%]
Margins for xj [25.99%，32.51%]
Margins for xl [39.84%，43.39%]
wherein xi is a global bias current margin, xj is a global Josephson junction current margin, and xl is a global inductance margin; the value before the bracket is the lower limit space which can be scanned by the index, the value after the bracket is the upper limit space which can be scanned by the index, and taking the global bias current margin xi as an example, the value is the critical lower working point when xi is changed to (1-0.3132) of the reference value; when xi is changed to (1 + 0.2735) of the reference value, it is the critical upper operating point. The principle that the global josephson junction current margin xj of the cell in this embodiment exceeds the first reference value by 20% or more, the global bias current margin xi exceeds the second reference value by 30% or more, and the global inductance margin xl exceeds the third reference value by 40% or more is not yet satisfied, and therefore, further optimization is required.
It should be noted that, in this embodiment, each index is a global bias current margin xi, a global josephson junction current margin xj, and a global inductance margin xl, and in actual use, the number of the indexes, specifically which index and the specific optimization target value may be set according to actual needs, which is not limited to this embodiment.
2) And sequentially performing grouping optimization on each index in the superconducting digital unit, if the optimization result is acceptable, updating the optimized parameter to the netlist and then performing optimization on the next index, otherwise, directly performing optimization on the next index.
Specifically, in this embodiment, the global bias current margin xi, the global inductance margin xl, and the global josephson junction current margin xj are sequentially optimized, and the order of optimizing each index may be set as needed in practical application.
More specifically, firstly, the bias currents in the superconducting digital units are grouped, the influence of the bias currents on three indexes is examined in groups, if the optimization result is acceptable, the optimized parameters are updated into the netlist, and if not, the next step is directly executed. Then, grouping the inductances in the superconducting digital units, examining the influence of the inductances on the three indexes in groups, updating the optimized parameters into the netlist if the optimization results are acceptable, and otherwise, directly executing the next step. And finally, grouping the Josephson junctions in the superconducting digital unit, inspecting the influence of the current of the Josephson junctions on three indexes in groups, updating the optimized parameters into the netlist if the optimization result is acceptable, and otherwise, directly executing the next step. The sequence of each group of investigation can be set based on actual needs, which is not described in detail herein.
It should be noted that, each index is grouped according to the branch function, in this embodiment, each index is divided into two groups, namely, a clock branch and a signal branch, as shown in fig. 2, where a clock branch is inside a virtual frame, and the other branches are signal branches. In actual use, grouping may be performed according to different functions.
It should be noted that, the criterion that the optimization result is acceptable is that the index to be optimized currently is optimized, and other indexes are changed within an allowable range (not lower than a preset lower limit).
The larger the parameter range of each index and the better the balance, the better the optimization result. The parameter range refers to the upper and lower limit swing space corresponding to each index, and the balance refers to the symmetry of the upper and lower limits based on the reference value.
As an example, in this embodiment, 21) first consider the bias current portion, there are a total of five biases in the circuit, the five biases are grouped, and the influence of the bias current on three indexes is examined in the first step of optimization: it was found that when the parameter ndro _ a.ir0 is adjusted from 1.20 to 1.00, the three indexes are:
Margins for xi [30.58%，28.13%]
Margins for xj [25.36%，32.17%]
Margins for xl [39.34%，40.00%]
it can be seen that although the global bias current margin xi is better balanced, the optimization in this step sacrifices the range of the global inductance margin xl (which is lower than the preset lower limit, and the specific value of the preset lower limit can be set as required), so the optimization result is considered to be unacceptable and is not considered temporarily.
22 And) after the optimization of the bias current is finished, considering the requirement of global inductance margin xl, dividing the inductance into the inductance of a clock branch circuit and the inductance of a signal branch circuit according to the function of a circuit branch circuit, and respectively inspecting the two groups of components. It was found that when the parameter ndro _ a.lt0 is optimized from 0.74 to 0.67, the parameter ndro _ a.lt1 is optimized from 0.54 to 0.38, and the parameter ndro _ a.lt3 is optimized from 0.56 to 0.50, the three criteria are:
Margins for xi [31.32%，31.32%]
Margins for xj [25.99%，34.79%]
Margins for xl [39.84%，45.68%]
it can be seen that the parameter ranges of the three indexes are increased simultaneously, the optimization result is acceptable, new values of the three components (the parameter ndro _ a.lt0, the parameter ndro _ a.lt1 and the parameter ndro _ a.lt3) are updated into the netlist, and all inductances of the signal branches are investigated on the basis of the parameters. It was found that when 0.16 of the parameter ndro _ a.ll2 is optimized to 0.24, the three indices are:
Margins for xi [31.32%，31.32%]
Margins for xj [27.35%，34.79%]
Margins for xl [39.84%，49.18%]
it can be seen that the parameter range of the global inductance margin xl is increased, the optimization result is acceptable, and the new value (parameter ndro _ a.ll2) of the component is updated into the netlist.
23 The influence caused by the change of the Josephson junctions is further considered on the basis of the updating of the four parameters, and the Josephson junctions are also classified and processed into the Josephson junctions of the clock branch and the Josephson junctions of the signal branch. In the observation of the josephson junction of the clock branch, it was found that optimizing the parameter ndro _ a.jt3 from 1.40 to 1.33, the three indices are:
Margins for xi [32.51%，30.14%]
Margins for xj [27.35%，34.79%]
Margins for xl [42.20%，49.18%]
it can be seen that the parameter range of the global inductance margin xl is increased, and a slight imbalance of the global bias current margin xi is also caused, but the imbalance is within an allowable range (set based on actual needs, not limited by this embodiment), and meets the index requirement, and such a change is acceptable, and a new value (parameter ndro _ a.jt3) of this component is updated into the netlist.
In the process of optimizing the Josephson junction current parameters of the signal branch, the fact that the overall optimization reaches the limit is found, and the tool cannot give any better collocation parameters (the larger the parameter range is, the better the optimization result is, the better the balance is, and the comprehensive consideration of the two is good).
FIG. 3 is a comparison diagram of the modified netlist and the unmodified netlist of the circuit under the simulation catalog, wherein the dark covered area is the modified parameter, and the parameter values before and after modification are different.
3) And updating the final optimization result to a circuit where the superconducting digital unit is located, and finishing curing.
Specifically, the five parameters are updated to the circuit where the superconducting digital unit is located, and a complete set of simulation flow is followed to perform final confirmation and solidification.
In the embodiment, on the basis of the step 1), five parameters of the circuit are finely optimized, so that three indexes of the circuit are slightly lower than the index requirements from two indexes at the beginning to meet the index requirements, and the circuit has more stable performance.
As another implementation manner of the present invention, step 3) is preceded by repeating step 2) until a better optimization result cannot be obtained, that is, step 2) improves the optimization effect through loop iteration.
As another implementation manner of the present invention, in step 2), a certain relatively poor index may be optimized, which is not limited to the embodiment.
The fine optimization method of the superconducting digital unit adopts fine optimization to rapidly mine the performance potential of the unit library, and at the moment, the method cannot completely depend on the automatic simulation of a tool, but needs to make practical consideration according to the actual situation. If the circuit scale is small and the number of components is small, the actual influence of each component on the parameters can be drawn, and the optimal collocation of each component can be found by analyzing; however, when the circuit scale is large and the number of components is large, grouping may be performed in the fine optimization process. In this embodiment, each of the parameters (junction current and inductance) is divided into a clock branch and a data branch according to the function of the branch. And (3) analyzing the result of each optimization, then determining that the optimization result is not accepted, and whether the next optimization link can be carried out based on the current optimization basis. Because the final result is obtained in no one step, the modification mode of the acceptable parameters is changed from the traditional mode of modifying the schema (circuit diagram) and then outputting the netlist to the mode of directly modifying and re-simulating the netlist in the simulation catalog until the parameters are finally matched, updated to the circuit diagram and the unit design is solidified. The invention further excavates the potential of the unit on the basis of automatic optimization of the tool, and further improves the stability of the overall performance of the unit library by further improving the margin of the unit in the unit library, thereby laying a solid foundation for the future superconducting digital circuit.
Example two
As shown in fig. 4, the present embodiment provides a fine optimization circuit of a superconducting digital unit, including:
a phase source 4, a superconducting digital unit 5 to be optimized and a load 6.
As shown in fig. 4, the phase source 4 is connected to the input of the superconducting digital unit 5 through a superconducting transmission line. One end of the load 6 is connected with the output end of the superconducting digital unit 5 through a superconducting transmission line, and the other end of the load 6 is grounded through the superconducting transmission line.
Specifically, the superconducting digital unit includes, but is not limited to, a non-destructive readout unit (NDRO), an exclusive or unit (XOR), an AND unit (AND), AND a latch unit (DFF, RDFF, DFFC), which are not listed herein.
More specifically, the superconducting digital unit includes various components, each including but not limited to a resistor, a josephson junction, and an inductor.
Specifically, in this embodiment, the fine optimization circuit of the superconducting digital unit may be used to implement the fine optimization method of the superconducting digital unit of the first embodiment.
In this embodiment, the phase source 4 and the load 6 both include two sets of paths, and thus, in practical use, the phase source may include only one set of paths or include more than two sets of paths, which is not limited to this embodiment.
In summary, the present invention provides a method and a circuit for fine optimization of a superconducting digital unit, comprising: 1) Carrying out global optimization on the superconducting digital unit to be optimized to obtain a corresponding netlist and excitation information; 2) Sequentially performing grouping optimization on each index in the superconducting digital unit, if the optimization result is acceptable, updating the optimized parameter to the netlist, and then performing optimization on the next index, otherwise, directly performing optimization on the next index; 3) And updating the final optimization result to a circuit where the superconducting digital unit is located, and finishing curing. The fine optimization method and the circuit of the superconducting digital unit, provided by the invention, have the advantages that the fine optimization process parameters are considered in groups, and compared with the optimization of all parameters of a tool, the time is saved, the convergence can be better realized, and the optimal parameter collocation can be obtained more quickly; after a certain acceptable parameter is obtained, the parameter of the component on the circuit diagram does not need to be changed, the netlist is exported again, the optimization process is carried out again, the parameter is directly modified in the netlist and then enters the next optimization link, the time consumed by an optimization unit, particularly a complex unit, can be further shortened, and errors possibly brought in multi-step operation are reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A method for fine optimization of a superconducting digital unit, the method comprising at least:
1) Carrying out global optimization on the superconducting digital unit to be optimized to obtain a corresponding netlist and excitation information;
2) Sequentially performing grouping optimization on each index in the superconducting digital unit, if the optimization result is acceptable, updating the optimized parameter to the netlist, and then performing optimization on the next index, otherwise, directly performing optimization on the next index; the acceptable standard of the optimization result is that the index to be optimized is optimized currently, and other indexes are not lower than a preset lower limit;
3) And updating the final optimization result to the circuit where the superconducting digital unit is located, and finishing curing.
2. The method for fine optimization of a superconducting digital unit according to claim 1, characterized in that: each index includes a global bias current margin, a global josephson junction current margin, and a global inductance margin.
3. Method for fine optimization of a superconducting digital unit according to claim 1 or 2, characterized in that: the optimization sequence of each index is a global bias current margin, a global inductance margin and a global Josephson junction current margin in sequence.
4. The method for fine optimization of a superconducting digital unit according to claim 1, characterized in that: the indexes are grouped according to the branch function.
5. The method for fine optimization of a superconducting digital unit according to claim 4, characterized in that: each index is divided into two groups, namely a clock branch and a signal branch.
6. Method for fine optimization of a superconducting digital unit according to claim 2, characterized in that: the larger the parameter range of each index is and the better the balance is, the better the optimization result is considered.
7. The method for fine optimization of a superconducting digital unit according to claim 6, characterized in that: the optimization target of the global Josephson junction current margin is 20% above and below a first reference value, the optimization target of the global bias current margin is 30% above and below a second reference value, and the optimization target of the global inductance margin is 40% above and below a third reference value.
8. The method for fine optimization of a superconducting digital unit according to claim 1, characterized in that: step 3) is preceded by repeating step 2) until no better optimization result can be obtained.
9. A fine optimization circuit of a superconducting digital unit, implementing the fine optimization method of a superconducting digital unit according to any one of claims 1 to 8, characterized in that it comprises at least:
a phase source, a superconducting digital unit to be optimized and a load;
the phase source is connected with the input end of the superconducting digital unit through a superconducting transmission line, the output end of the superconducting digital unit is connected with one end of the load through the superconducting transmission line, and the other end of the load is grounded through the superconducting transmission line.
10. The fine optimization circuit of a superconducting digital unit according to claim 9, wherein: the superconducting digital cell includes a non-destructive readout unit.
11. Fine optimization circuit of a superconducting digital unit according to claim 9 or 10, characterized in that: the components of the fine optimization circuit of the superconducting digital unit comprise a resistor, a Josephson junction and an inductor.
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