CN110031700B - PXI bus-based satellite load universal ground detection board card - Google Patents
PXI bus-based satellite load universal ground detection board card Download PDFInfo
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- CN110031700B CN110031700B CN201910226984.8A CN201910226984A CN110031700B CN 110031700 B CN110031700 B CN 110031700B CN 201910226984 A CN201910226984 A CN 201910226984A CN 110031700 B CN110031700 B CN 110031700B
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- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
- G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
- G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a PXI bus-based satellite load universal ground detection board card which comprises a PXI mother card integrated with an FPGA, an OC instruction module, an LVDS communication module, an RS422 differential communication module, an AD acquisition module and a temperature telemetry module. The invention can realize the generalization of the satellite load ground inspection board card, saves the ground inspection development cost required by different loads, integrates the functions of OC instruction, LVDS communication, RS4221, AD acquisition and temperature telemetering, simplifies cable connection, improves the integration level and reduces PXI case resources occupied by the ground inspection board card.
Description
Technical Field
The invention relates to the field of satellite load ground detection systems, in particular to a PXI bus-based satellite load universal ground detection board card.
Background
The traditional satellite load ground inspection board card has relatively single function and low integration level, the whole ground inspection function is realized, a plurality of ground inspection board cards are often required to be matched for use, the board card functions and the specific settings required by different loads are different, and the research and development cost and the difficulty are invisibly increased. Therefore, the realization of the multifunction and high integration of the ground inspection board card and the improvement of the universality thereof are important challenges in the field of on-satellite load ground inspection.
Disclosure of Invention
The invention aims to provide a PXI bus-based satellite load universal ground detection board card, so that the multifunction and high integration of the ground detection board card are realized, the universality is improved, and the development cost of the satellite load universal ground detection board card is reduced.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the utility model provides a general ground of satellite load detects integrated circuit board based on PXI bus which characterized in that: including the 3UPXI integrated board card that has FPGA to the 3UPXI integrated board card that has FPGA is as mother's card, and the extension is installed OC instruction module, LVDS communication module, RS422 differential communication module, AD acquisition module and temperature telemetry module on the mother's card, by OC instruction module, LVDS communication module, RS422 differential communication module, AD acquisition module and temperature telemetry module as daughter card respectively and FPGA are connected, FPGA passes through 3UPXI board card PXI bus from the area and upper computer communication connection, wherein:
the OC instruction module comprises a DC/DC circuit, a level conversion circuit and a plurality of drivers, wherein the input end of the DC/DC circuit is connected with a power supply, the output end of the DC/DC circuit is connected with a relay of a satellite load, the DC/DC circuit converts the voltage 1 of the power supply into the working voltage required by the relay on the satellite load, an I/O signal pin of the FPGA is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is respectively connected to the signal input end of each driver, the I/O signal of the FPGA outputs a logic level to the level conversion circuit, and the logic level is converted into the working voltage of each driver through the level conversion circuit;
the LVDS communication module comprises a multi-path LVDS receiving circuit and a multi-path LVDS transmitting circuit, wherein the input end of the multi-path LVDS transmitting circuit is respectively connected with an I/O signal pin of the FPGA, the output end of the multi-path LVDS transmitting circuit is respectively connected to the satellite load, the input end of the multi-path LVDS receiving circuit is respectively connected to the satellite load, and the output end of the multi-path LVDS receiving circuit is respectively connected to the I/O signal pin of the FPGA; LVDS signals sent by the FPGA are converted into differential signals through an LVDS sending circuit and then are transmitted to the satellite load, and the differential signals sent by the satellite load are synthesized into single-ended signals through an LVDS receiving circuit and then are transmitted to the FPGA;
the RS422 differential communication module comprises a plurality of paths of 422 receiving circuits, a plurality of paths of 422 sending circuits and a level conversion circuit comprising at least two conversion channels, wherein the input ends of the plurality of paths of 422 sending circuits are respectively connected with an I/O signal pin of the FPGA, the output ends of the plurality of paths of 422 sending circuits are respectively connected with the input end of a first conversion channel of the level conversion circuit, the output end of the first conversion channel of the level conversion circuit is connected with a satellite load, the input ends of the plurality of paths of 422 receiving circuits are respectively connected with the satellite load, the output ends of the plurality of paths of 422 receiving circuits are respectively connected with the input end of a second conversion channel of the level conversion circuit, and the output end of the second conversion channel of the level conversion circuit is; the single-ended signal sent by the FPGA is converted into a differential signal through a 422 sending circuit and a level conversion circuit and is transmitted to the satellite load, and the differential signal sent by the satellite load is synthesized into a 3.3V single-ended signal through a 422 receiving circuit and the level conversion circuit and is transmitted to the FPGA;
the AD acquisition module comprises a multi-channel analog switch and an AD converter, wherein the analog signal input end of the AD converter is connected with the output end of a multi-channel analog switch channel, and different AD telemetering signals of the satellite load are switched through all switch channels in the multi-channel analog switch. The I/O signal pin of the FPGA is also connected with the control end of the multi-channel analog switch, the chip selection signal pin and the clock signal pin of the FPGA are also respectively connected with the corresponding pins of the AD converter, the FPGA sends a channel switching signal to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch so as to switch on different conversion channels of the AD converter, the conversion result of each conversion channel of the AD converter is returned to the FPGA as serial data, and the FPGA also sends a driving clock signal and a chip selection signal required by the AD converter to the AD converter;
the temperature telemetering module comprises a temperature sensing circuit, a multi-channel analog switch and an AD converter, wherein the output end of the temperature sensing circuit is respectively connected with the analog signal input end of the AD converter, and different temperature telemetering signals of the satellite load are switched through each switch channel in the multi-channel analog switch. The FPGA sends channel switching signals to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch to switch on different conversion channels of the AD converter, conversion results of all the conversion channels of the AD converter are returned to the FPGA as serial data, and the FPGA also sends driving clock signals and chip selection signals required by the AD converter to the AD converter.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: the FPGA uses an Altera Cyclone III FPGA.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: in the OC instruction module, the DC/DC circuit is composed of a DC/DC conversion chip with a model number of TEN20WI, the level conversion circuit is composed of a level conversion chip with a model number of SN74LVC8T245, and the multi-channel driver is composed of a multi-channel driving chip with a model number of SHD51303 produced by Shandong space electronic technology research institute.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: in the LVDS communication module, the LVDS receiving circuit is composed of an LVDS receiving chip with the model number of SN65LVDS32NSR, and the LVDS sending circuit is composed of an LVDS sending chip with the model number of SN65LVDS31 NSR.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: in the RS422 differential communication module, the 422 receiving circuit is composed of a 422 receiving chip with a model of AM26C32INSR, the 422 transmitting circuit is composed of a 422 transmitting chip with a model of AM26C31INSR, and the level conversion circuit is composed of a level conversion chip with a model of SN74LVC8T 245.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: in the AD acquisition module, a multi-channel analog switch is composed of a multi-channel analog switch chip with the model of ADG708, and an AD converter is composed of an AD conversion chip with the model of TLC549 MD.
The universal ground detection board card for satellite loads based on the PXI bus is characterized in that: in the temperature telemetering module, a temperature sensing circuit adopts a thermistor temperature measuring circuit, wherein a thermistor converts object temperature information into a thermistor resistance value and converts the thermistor resistance value into an analog voltage through a voltage dividing circuit; the multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG 708; the AD converter is composed of an AD conversion chip of model TLC549 MD.
Compared with the prior art, the invention has the beneficial effects that:
1. the existing floor inspection board cards in the market are relatively single in function and low in integration level, a plurality of floor inspection board cards are often required to be matched for use when the whole floor inspection function is realized, the board card functions and the specific settings required by different loads are different, and the research and development cost and difficulty are invisibly increased. The FPGA 3U PXI board card is used as a mother card, an OC instruction module, an LVDS communication module, an RS422 differential communication module, an AD acquisition module and a temperature telemetry module are integrated, all common functions required by satellite load ground inspection are basically covered, the ground inspection function which can be finished by a plurality of board cards in the past can be realized by only one board card, and the expensive board card cost and the development difficulty are greatly saved.
2. The board card is convenient to use, and a user can flexibly configure the FPGA and an upper computer program to meet the requirements of different loads on the signal path number, the synchronous pulse frequency, the telemetering sampling interval and the like, so that the universality and the openness of the board card are greatly improved.
Drawings
FIG. 1 is a schematic diagram of an application of the FPGA 3U PXI mother card of the present invention.
FIG. 2 is a schematic diagram of the connection between the FPGA 3U PXI mother card and daughter cards of the present invention.
FIG. 3 is a schematic diagram of the OC instruction module of the present invention.
Fig. 4 is a schematic diagram of an LVDS communication module of the invention.
Fig. 5 is a schematic diagram of the RS422 differential communication module of the present invention.
Fig. 6 is a schematic diagram of an AD acquisition module of the present invention.
FIG. 7 is a schematic diagram of the temperature telemetry module of the present invention.
Fig. 8 is a functional block diagram of the architecture of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 1 to 8, a PXI bus-based satellite load universal ground detection board card includes a 3UPXI board card integrated with an FPGA, the 3UPXI board card integrated with the FPGA is used as a mother card, the mother card is provided with an OC instruction module, an LVDS communication module, an RS422 differential communication module, an AD acquisition module and a temperature telemetry module in an extended manner, the OC instruction module, the LVDS communication module, the RS422 differential communication module, the AD acquisition module and the temperature telemetry module are respectively used as daughter cards to be connected with the FPGA, the FPGA is in communication connection with an upper computer through a PXI bus of the 3UPXI board card, wherein:
the OC instruction module comprises a DC/DC circuit, a level conversion circuit and a plurality of drivers, wherein the input end of the DC/DC circuit is connected with a power supply, the output end of the DC/DC circuit is connected with a relay of a satellite load, the DC/DC circuit converts the PXI case power supply voltage into the working voltage required by the relay on the satellite load, an I/O signal pin of the FPGA is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is respectively connected to the signal input end of each driver, the I/O signal of the FPGA outputs a logic level to the level conversion circuit, and the logic level is converted into the working voltage of each driver through the level conversion circuit;
the LVDS communication module comprises a multi-path LVDS receiving circuit and a multi-path LVDS transmitting circuit, wherein the input end of the multi-path LVDS transmitting circuit is respectively connected with an I/O signal pin of the FPGA, the output end of the multi-path LVDS transmitting circuit is respectively connected to the satellite load, the input end of the multi-path LVDS receiving circuit is respectively connected to the satellite load, and the output end of the multi-path LVDS receiving circuit is respectively connected to the I/O signal pin of the FPGA; LVDS signals sent by the FPGA are converted into differential signals through an LVDS sending circuit and then are transmitted to the satellite load, and the differential signals sent by the satellite load are synthesized into single-ended signals through an LVDS receiving circuit and then are transmitted to the FPGA;
the RS422 differential communication module comprises a plurality of paths of 422 receiving circuits, a plurality of paths of 422 sending circuits and a level conversion circuit comprising at least two conversion channels, wherein the input ends of the plurality of paths of 422 sending circuits are respectively connected with an I/O signal pin of the FPGA, the output ends of the plurality of paths of 422 sending circuits are respectively connected with the input end of a first conversion channel of the level conversion circuit, the output end of the first conversion channel of the level conversion circuit is connected with a satellite load, the input ends of the plurality of paths of 422 receiving circuits are respectively connected with the satellite load, the output ends of the plurality of paths of 422 receiving circuits are respectively connected with the input end of a second conversion channel of the level conversion circuit, and the output end of the second conversion channel of the level conversion circuit is; the single-ended signal sent by the FPGA is converted into a differential signal through a 422 sending circuit and a level conversion circuit and is transmitted to the satellite load, and the differential signal sent by the satellite load is synthesized into a 3.3V single-ended signal through a 422 receiving circuit and the level conversion circuit and is transmitted to the FPGA;
the AD acquisition module comprises a multi-channel analog switch and an AD converter, wherein the input end of a conversion channel of the AD converter is connected with different AD telemetering signals of a satellite load through each switch channel switched by the multi-channel analog switch, an I/O signal pin of the FPGA is connected with the control end of the multi-channel analog switch, a chip selection signal pin and a clock signal pin of the FPGA are also respectively connected with corresponding pins of the AD converter, the FPGA sends a channel switching signal to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch to connect different conversion channels of the AD converter, the conversion result of each conversion channel of the AD converter is returned to the FPGA as serial data, and the FPGA also sends a driving clock signal and a chip selection signal required by the AD converter to the AD converter;
the temperature telemetering module comprises a temperature sensing circuit, a multi-channel analog switch and an AD converter, wherein the output end of the temperature sensing circuit is connected with the analog signal input end of the AD converter and is connected with different temperature telemetering signals of the satellite load through each switch channel switched in the multi-channel analog switch, an I/O signal pin of the FPGA is respectively connected with the control end of the multi-channel analog switch, a chip selection signal pin and a clock signal pin of the FPGA are also respectively connected with corresponding pins of the AD converter, the temperature value acquired by the temperature sensing circuit is converted into analog voltage and then is transmitted into the FPGA after being converted by the AD converter, the FPGA transmits a channel switching signal to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch so as to connect different conversion channels of the AD converter, and the conversion result of each conversion channel of the AD converter is returned to the FPGA as serial data, the FPGA also sends a driving clock signal and a chip selection signal required by the AD converter to the AD converter.
In the LVDS communication module, the LVDS receiving circuit is constituted by an LVDS receiving chip whose model is SN65LVDS32NSR, and the LVDS transmitting circuit is constituted by an LVDS transmitting chip whose model is SN65LVDS31 NSR.
In the RS422 differential communication module, a 422 receiving circuit is composed of a 422 receiving chip with the model number of AM26C32INSR, a 422 transmitting circuit is composed of a 422 transmitting chip with the model number of AM26C31INSR, and a level conversion circuit is composed of a level conversion chip with the model number of SN74LVC8T 245.
In the AD acquisition module, a multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG708, and an AD converter is composed of an AD conversion chip with the model number of TLC549 MD.
In the temperature telemetering module, a temperature sensing circuit adopts a thermistor temperature measuring circuit, wherein a thermistor converts object temperature information into a thermistor resistance value and converts the thermistor resistance value into an analog voltage through a voltage dividing circuit; the multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG 708; the AD converter is composed of an AD conversion chip of model TLC549 MD.
As shown in FIG. 1, the FPGA of the present invention has 160 digital I/O signal pins to meet the special application requirements. The FPGA uses an Altera cycle III FPGA, and the series of FPGAs support a 150MHz clock rate, have 55000 logic units and 2.34Mb memory. An 'expansion board card' can be installed on the mother card, and the characteristic is beneficial to a user to customize an interface according to different UUT applications. The mother card and the daughter card are arranged in a face-to-face mode, dependence on an additional external daughter card arranged longitudinally is avoided, the daughter card arranged longitudinally can increase the size and the weight of the system, and difficulty of system integration can be increased. FPGA programming can be done using Altera's Quartus II, which can be loaded from the FPGA through a PXI bus interface or "onboard EEROM" once the user has finished compiling the FPGA program.
The Altera Cyclone III FPGA can be configured indirectly through an EEPROM or directly through a PXI interface. The FPGA may access PXI memory 1 resources such as a local bus, a trigger bus, a PXI 10MHz clock source. Therefore, the communication between the FPGA and the upper computer operating system can be realized.
As shown in fig. 2, P8-P11 are high speed connectors produced by Samtec that have a center bar for connecting either "ground" or power. The product number of the P8 connector is QTE-060-02-L-D-A, and the number of the P9-P11 connector is QTE-040-02-L-D-A. The P8 and P9 connectors are used for connecting FPGA Flex I/O signals with a daughter card. The P10 and P11 connectors are used for connecting the mother card front panel VHDCI connector with the daughter card, wherein P10 connects the mother card front panel J3 (Flex I/O B group) with J4 (Flex I/O C group) connector, and P11 connects the GX3500 front panel J1 (Flex I/O A group) with J2 (Flex I/O D group) connector. The bidirectional switch is used for controlling the connection of Flex I/O signals of the FPGA to the mother card front panel connector or the daughter card.
As shown in FIG. 3, the OC instruction module of the invention comprises a DC/DC circuit, a level conversion circuit and an 8-way negative direction instruction driving circuit. And taking 12V power supply from the PXI case, and converting the power supply into 28V power required by a relay on a satellite load through a DC/DC circuit. The FPGA outputs 3.3V logic level, and the logic level is converted into 5V through a level conversion circuit and then is used as the working voltage of the negative direction instruction driving circuit.
The DC/DC circuit is composed of a DC/DC conversion chip with a model number of TEN20WI, the level conversion circuit is composed of a level conversion chip with a model number of SN74LVC8T245, and the multi-path driver is composed of a multi-path driving chip with a model number of SHD51303 produced by Shandong space electronic technology research institute. The DIR pin and the OE pin of the level shift chip SN74LVC8T245 are grounded and represent signal output enable, and the direction is from B to A, i.e. from VCCB level to VCCA level. And a 0.1u capacitor is connected between the chip power pin and the GND in series for filtering. The OC _3.3V command from the FPGA is converted into OC _5V by the level converting chip SN74LVC8T245 to drive the multi-channel driving chip SHD 51303. The multi-channel driving chip SHD51303 is an NPN type current driver. The circuit consists of four identical command driving units, and the input pulse signal is amplified in two stages to output maximum current of 400 mA. The instruction adopts double-input control, two input signals are relatively independent, and when two control ends input high level at the same time, the output is low level; when the control end inputs low level, the output is in a high impedance state. When the FPGA pulls down OC _3.3V, a high-resistance state is formed between an OC output signal of the negative direction instruction driving chip SHD51303 and a 28V power supply, the relay cannot be driven, when the FPGA pulls up OC _3.3V, OC output of the multi-path driving chip SHD51303 is in a low level, and the relay is normally driven.
As shown in fig. 4, the LVDS communication module of the present invention includes 4 paths of LVDS receiving and transmitting circuits. The signals sent by the FPGA are converted into differential signals through an LVDS sending circuit and are transmitted to a load; the differential signals sent by the load are synthesized into single-ended signals through the LVDS receiving circuit and are transmitted to the FPGA.
In the LVDS communication module, the LVDS receiving circuit is constituted by an LVDS receiving chip whose model is SN65LVDS32NSR, and the LVDS transmitting circuit is constituted by an LVDS transmitting chip whose model is SN65LVDS31 NSR. The FPGA sends LVDS 1-4 signals, and the LVDS signals are converted into 4 paths of differential pairs through an LVDS sending chip SN65LVDS31NSR, so that the anti-interference performance is improved. And LVDS 5-6 positive and negative differential signals sent by the load are converted by an LVDS receiving chip SN65LVDS32NSR and then transmitted to the FPGA. In addition, a 100 ohm resistor is added to each differential receiving end for impedance matching, so that the signal integrity problems such as reflection ringing and the like are reduced.
As shown in fig. 5, the RS422 differential communication module of the present invention includes 8 paths of 422 receiving and transmitting circuits, and a level shift circuit. The 3.3V single-ended signal transmitted by the FPGA is converted into a differential signal through a 422 transmitting circuit and a level conversion circuit and is transmitted to a load; and differential signals sent by the load are synthesized into 3.3V single-ended signals through a 422 receiving circuit and a level conversion circuit and are transmitted to the FPGA.
In the RS422 differential communication module, a 422 receiving circuit is composed of a 422 receiving chip with the model number of AM26C32INSR, a 422 transmitting circuit is composed of a 422 transmitting chip with the model number of AM26C31INSR, and a level conversion circuit is composed of a level conversion chip with the model number of SN74LVC8T 245. The FPGA sends 8 paths of DF-3.3V signals, the signals are converted into 5V levels DF 1-8 through a level conversion chip SN74LVC8T245, and then the signals are converted into 8 paths of differential pairs through a 422 sending chip AM26C31INSR to be transmitted to loads, so that the anti-interference performance is improved. And DF9~16 positive and negative differential signals sent by the load are converted into 3.3V level by a level conversion chip SN74LVC8T245, and then are transmitted to the FPGA by a 422 receiving chip AM26C32INSR receiver. In addition, the differential transceiver interface needs to add a matching resistor to reduce the signal integrity problems such as reflection ringing.
As shown in fig. 6, the AD acquisition module of the present invention includes a multi-channel analog switch having 8 switching channels and an AD converter having 8 conversion channels. The FPGA sends a channel switching signal CH _ A [2..0] of the multi-channel analog switch, and is used for switching different conversion channels of the AD converter. The FPGA also transmits a driving clock ADCLK1 and a chip select signal ADCS1 required for the AD converter, and the conversion result is returned to the FPGA as serial data.
In the AD acquisition module, a multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG708, and an AD converter is composed of an 8-bit AD conversion chip with the model number of TLC549MD, which is low in price and high in performance and is manufactured by TI company. The AD converter realizes A/D conversion by using an 8-bit switched capacitor successive approximation method, the conversion speed is less than 17us, the maximum conversion rate is 40000HZ, a 4MHZ typical internal system clock and the power supply is 3V to 6V. It can be conveniently connected with various microprocessors by adopting a three-wire serial interface mode to form various cheap measurement and control application systems. As can be seen from the figure, the positive reference voltage input terminal REF + of the AD conversion chip TLC549 and the system power supply VCC are both connected with 3.3V voltage, the negative reference voltage input terminal REF-GND are both connected with ground, and the external clock signal ADCLK1, the conversion result data serial output ADDO and the chip select signal ADCS1 are all connected with the FPGA pin. The analog input signal AIN is connected to the multi-channel analog switch chip ADG 708. The multiple analog switch chip ADG708 is a low-voltage CMOS analog multiplexer with 8 single channels built therein. According to the address determined by a channel switching signal CH _ A [2..0] of a multi-channel analog switch sent by the FPGA, one of 8-channel input (S1-S8) is switched to a common output D, namely an analog input end AIN of an AD conversion chip TLC549 MD.
As shown in fig. 7, the temperature telemetry module of the present invention includes a temperature sensing circuit, a multi-way analog switch having 8 switching channels, and an AD converter having 8 switching channels. In the temperature telemetering module, a temperature sensing circuit adopts a thermistor temperature measuring circuit, wherein the thermistor converts object temperature information into a thermistor resistance value, and the thermistor resistance value is converted into analog voltage through a voltage dividing circuit. The FPGA sends a channel switching signal CH _ B [2..0] of the multi-channel analog switch, and is used for switching different conversion channels of the AD converter. The FPGA also transmits a driving clock ADCLK2 and a chip select signal ADCS2 required for the AD converter, and the conversion result is returned to the FPGA as serial data.
In the temperature telemetering module, a multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG 708; the AD converter is composed of an AD conversion chip of model TLC549 MD. The positive reference voltage input end REF + of the AD converter TLC549 and the system power supply VCC are connected with 3.3V voltage, the negative reference voltage input end REF-and GND are connected with the ground, and an external clock signal ADCLK2, a temperature conversion data serial output Tem and a chip selection signal ADCS2 are connected with the FPGA pin. The analog input signal Tem + is connected to the multi-way analog switch chip ADG708, which switches one of the 8 inputs (S1-S8) to the common output D, i.e., the analog input Tem + of the AD converter TLC549, according to the address determined by the channel switching signal CH _ B [2..0] of the multi-way analog switch sent by the FPGA. And a Tem + position collects the voltage value of the thermistor after the thermistor is subjected to voltage division by a 5k resistor, and the telemetering temperature of the thermistor can be obtained according to a thermistor temperature and resistance value relation table.
Claims (7)
1. The utility model provides a general ground of satellite load detects integrated circuit board based on PXI bus which characterized in that: including the 3UPXI integrated board card that has FPGA to the 3UPXI integrated board card that has FPGA is as mother's card, and the extension is installed OC instruction module, LVDS communication module, RS422 differential communication module, AD acquisition module and temperature telemetry module on the mother's card, by OC instruction module, LVDS communication module, RS422 differential communication module, AD acquisition module and temperature telemetry module as daughter card respectively and FPGA are connected, FPGA passes through 3UPXI board card PXI bus from the area and upper computer communication connection, wherein:
the OC instruction module comprises a DC/DC circuit, a level conversion circuit and a plurality of drivers, wherein the input end of the DC/DC circuit is connected with a PXI case power supply, the output end of the DC/DC circuit is connected with a relay of a satellite load, the DC/DC circuit converts the PXI case power supply voltage into the working voltage required by the relay on the satellite load, an I/O signal pin of the FPGA is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is respectively connected to the signal input end of each driver, the I/O signal of the FPGA outputs a logic level to the level conversion circuit, and the logic level is converted into the working voltage of each driver through the level conversion circuit;
the LVDS communication module comprises a multi-path LVDS receiving circuit and a multi-path LVDS transmitting circuit, wherein the input end of the multi-path LVDS transmitting circuit is respectively connected with an I/O signal pin of the FPGA, the output end of the multi-path LVDS transmitting circuit is respectively connected to the satellite load, the input end of the multi-path LVDS receiving circuit is respectively connected to the satellite load, and the output end of the multi-path LVDS receiving circuit is respectively connected to the I/O signal pin of the FPGA; LVDS signals sent by the FPGA are converted into differential signals through an LVDS sending circuit and then are transmitted to the satellite load, and the differential signals sent by the satellite load are synthesized into single-ended signals through an LVDS receiving circuit and then are transmitted to the FPGA;
the RS422 differential communication module comprises a plurality of paths of 422 receiving circuits, a plurality of paths of 422 sending circuits and a level conversion circuit comprising at least two conversion channels, wherein the input ends of the plurality of paths of 422 sending circuits are respectively connected with an I/O signal pin of the FPGA, the output ends of the plurality of paths of 422 sending circuits are respectively connected with the input end of a first conversion channel of the level conversion circuit, the output end of the first conversion channel of the level conversion circuit is connected with a satellite load, the input ends of the plurality of paths of 422 receiving circuits are respectively connected with the satellite load, the output ends of the plurality of paths of 422 receiving circuits are respectively connected with the input end of a second conversion channel of the level conversion circuit, and the output end of the second conversion channel of the level conversion circuit is; the single-ended signal sent by the FPGA is converted into a differential signal through a 422 sending circuit and a level conversion circuit and is transmitted to the satellite load, and the differential signal sent by the satellite load is synthesized into a 3.3V single-ended signal through a 422 receiving circuit and the level conversion circuit and is transmitted to the FPGA;
the AD acquisition module comprises a multi-channel analog switch and an AD converter, wherein an analog input end of the AD converter is connected with an output end of a multi-channel analog switch channel, different AD telemetering signals of a satellite load are switched through each switch channel in the multi-channel analog switch, an I/O signal pin of the FPGA is connected with a control end of the multi-channel analog switch, a chip selection signal pin and a clock signal pin of the FPGA are also respectively connected with corresponding pins of the AD converter, the FPGA sends channel switching signals to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch to connect different conversion channels of the AD converter, conversion results of each conversion channel of the AD converter are returned to the FPGA as serial data, and the FPGA also sends driving clock signals and chip selection signals required by the AD converter to the AD converter;
the temperature telemetering module comprises a temperature sensing circuit, a multi-channel analog switch and an AD converter, wherein the output end of the temperature sensing circuit is connected with the input end of the AD converter, and different temperature telemetering signals of the satellite load are switched through each switch channel in the multi-channel analog switch; the FPGA sends channel switching signals to the multi-channel analog switch for switching different switch channels of the multi-channel analog switch to switch on different conversion channels of the AD converter, conversion results of all the conversion channels of the AD converter are returned to the FPGA as serial data, and the FPGA also sends driving clock signals and chip selection signals required by the AD converter to the AD converter.
2. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: the FPGA uses an Altera Cyclone III FPGA.
3. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: in the OC instruction module, the DC/DC circuit is composed of a DC/DC conversion chip with a model number of TEN20WI, the level conversion circuit is composed of a level conversion chip with a model number of SN74LVC8T245, and the multi-path driver is composed of a multi-path driving chip with a model number of SHD 51303.
4. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: in the LVDS communication module, the LVDS receiving circuit is composed of an LVDS receiving chip with the model number of SN65LVDS32NSR, and the LVDS sending circuit is composed of an LVDS sending chip with the model number of SN65LVDS31 NSR.
5. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: in the RS422 differential communication module, the 422 receiving circuit is composed of a 422 receiving chip with a model of AM26C32INSR, the 422 transmitting circuit is composed of a 422 transmitting chip with a model of AM26C31INSR, and the level conversion circuit is composed of a level conversion chip with a model of SN74LVC8T 245.
6. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: in the AD acquisition module, a multi-channel analog switch is composed of a multi-channel analog switch chip with the model of ADG708, and an AD converter is composed of an AD conversion chip with the model of TLC549 MD.
7. The PXI bus-based satellite load universal ground detection board card of claim 1, wherein: in the temperature telemetering module, a temperature sensing circuit adopts a thermistor temperature measuring circuit, wherein a thermistor converts object temperature information into a thermistor resistance value and converts the thermistor resistance value into an analog voltage through a voltage dividing circuit; the multi-path analog switch is composed of a multi-path analog switch chip with the model number of ADG 708; the AD converter is composed of an AD conversion chip of model TLC549 MD.
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| CN111404591B (en) * | 2020-02-20 | 2022-04-12 | 浙江时空道宇科技有限公司 | Satellite load ground test equipment and method |
| CN112732343B (en) * | 2020-12-31 | 2022-04-22 | 中国电子科技网络信息安全有限公司 | Method for loading service primary and secondary board cards in stacking equipment |
| CN113485087B (en) * | 2021-06-16 | 2023-11-10 | 航天东方红卫星有限公司 | Small satellite DC-DC module active-standby switching device based on PXI bus technology |
| CN113489393B (en) * | 2021-06-29 | 2023-03-24 | 中国科学院合肥物质科学研究院 | Subdivision driving method of permanent magnet stepping motor |
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