CN110010079A - Gate drive apparatus - Google Patents
Gate drive apparatus Download PDFInfo
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- CN110010079A CN110010079A CN201910435942.5A CN201910435942A CN110010079A CN 110010079 A CN110010079 A CN 110010079A CN 201910435942 A CN201910435942 A CN 201910435942A CN 110010079 A CN110010079 A CN 110010079A
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- 230000005611 electricity Effects 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000007704 transition Effects 0.000 description 13
- 230000001360 synchronised effect Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 238000006073 displacement reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
Gate drive apparatus, including multiple shift register circuits.In N grades of shift register circuit, output-stage circuit is according to first control signal, second control signal and first mode selection signal to generate N grades of gate drive signals.First voltage adjuster is according to second control signal to adjust first control signal.Second voltage adjuster is according to second mode selection signal, prime gate drive signal or initial pulse signal to adjust first control signal.Tertiary voltage adjuster is according to rear class gate drive signal to adjust first control signal.4th voltage adjuster is according to first mode selection signal to adjust second control signal.5th voltage adjuster is according to reversed clock pulse signal, second mode selection signal and first control signal to adjust second control signal.
Description
Technical field
The invention relates to a kind of gate drive apparatus, and in particular to a kind of grid to drive display panel
Electrode driving device.
Background technique
It is opened in the active light-emitting diode pixel circuit of synchronous light-emitting, when need to be more in compensated stage all
Pixel, so as to can variation to the conducting voltage of thin film transistor (TFT) in picture element while the movement that compensates.In next number
According to write phase, then unlatching pixel circuit by column is needed, with the movement for carrying out data write-in for pixel circuit by column.
In existing technical field, the pixel circuit of synchronous light-emitting often faces various problems.First, synchronous light-emitting
Pixel circuit in need to be arranged special signal to indicate the progress of compensated stage and data write phase；Second, it is answering
When for high-resolution display panel, sufficiently long Data writing time is needed；Third is low when applying in gate driving circuit
When thin film transistor (TFT) manufactured by temperature polysilicon processing procedure, when thin film transistor (TFT) is disconnected, can still have relatively high electronics
Mobility, and the phenomenon that generating electric leakage, is be easy to cause on circuit node.
Summary of the invention
The present invention provides a kind of gate drive apparatus, can be applied on high-resolution display panel.
Gate drive apparatus of the invention includes multiple shift register circuits.Multiple shift register circuits are serially connected coupling
It connects, and generates multiple gate drive signals respectively, wherein N grades of shift register circuit includes output-stage circuit, first voltage
Adjuster, second voltage adjuster, tertiary voltage adjuster, the 4th voltage adjuster and the 5th voltage adjuster.Output stage
Circuit has the first control terminal and the second control terminal to receive first control signal and second control signal respectively.Output stage electricity
It is high that road provides clock pulse signal, grid according to first control signal, second control signal and first mode selection signal
Voltage or grid low-voltage charge to generate N grades of gate drive signals to output end.First voltage adjuster is coupled in first
Between control terminal and the second control terminal, according to second control signal to provide gate high-voltage to adjust first control signal.The
Two voltage adjusters are coupled to the first control terminal, according to second mode selection signal, prime gate drive signal or initial pulse
Signal is to adjust first control signal.Tertiary voltage adjuster is coupled to the first control terminal, according to rear class gate drive signal with
Gate high-voltage is provided to adjust first control signal.4th voltage adjuster is coupled to the second control terminal, according to first mode
Selection signal is to provide gate high-voltage to adjust second control signal.5th voltage adjuster is coupled to the second control terminal, according to
According to reversed clock pulse signal, second mode selection signal and first control signal to provide reversed clock pulse signal or grid
Very high voltage is to adjust second control signal.
The letter of the control in control terminal is adjusted by multiple voltage adjusters based on above-mentioned, of the invention gate drive apparatus
Number, and by control signal control output-stage circuit to generate gate drive signal.In this way, gate drivers can be in compensated stage
Multiple gate drive signals with consistent waveform are generated, and generate multiple grid of sequentially enable respectively in write phase later
Pole driving signal.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Detailed description of the invention
Fig. 1 shows the schematic diagram of the gate drive apparatus of the embodiment of the present invention.
Fig. 2 shows the movement oscillograms of the gate drive apparatus of the embodiment of the present invention.
Fig. 3 A to Fig. 3 H shows the equivalent circuit diagram of the shift register circuit of the embodiment of the present invention.
Wherein, appended drawing reference are as follows:
100: shift register circuit
110: output-stage circuit
120~160: voltage adjuster
C1: capacitor
CE1, CE2: control terminal
CK: clock pulse signal
XCK: reversed clock pulse signal
G[N]: N grades of gate drive signals
G[N-1]: prime gate drive signal
G[N+1]: rear class gate drive signal
OE: output end
Q[N]、P[N]: control signal
SS, SR: mode select signal
ST: initial pulse signal
T1~T13: transistor
TA0~TA7: time interval
VGH: gate high-voltage
VGL: grid low-voltage
Δ V1, Δ V2: deviant
Specific embodiment
Structural principle and working principle of the invention are described in detail with reference to the accompanying drawing:
Fig. 1 is please referred to, Fig. 1 shows the schematic diagram of the gate drive apparatus of the embodiment of the present invention.Gate drive apparatus includes
Multiple shift register circuits of coupling are serially connected, and generate multiple gate drive signals respectively.With N grades of shift LD electricity
For road 100, shift register circuit 100 includes output-stage circuit 110 and voltage adjuster 120~160.Output-stage circuit
110 have the first control terminal CE1 and the second control terminal CE2.First control terminal CE1 and the second control terminal CE2 receives respectively
One control signal Q [N] and second control signal P [N].Output-stage circuit 110 can be according to first control signal Q [N], the second control
Signal P [N] and mode select signal SS is to provide clock pulse signal CK, gate high-voltage VGH or VGL pairs of grid low-voltage
Output end OE charging, and use and generate N grades of gate drive signal G [N].Wherein, when mode select signal SS is low-voltage electricity
When position, output-stage circuit 110 can provide grid low-voltage VGL and charge output end OE to drag down N grades of gate drive signal G
The voltage value of [N].In the present embodiment, mode select signal SS, SR is to indicate that shift register circuit 100 operates in compensation rank
Section or write phase.
In the present embodiment, output-stage circuit 110 includes transistor T3, T4, T11 and capacitor C1.The of transistor T3
One end receives clock pulse signal CK, and the second end of transistor T3 is coupled to output end OE, and the control terminal of transistor T3 receives the
One control signal Q [N].The first end of transistor T11 is coupled to output end OE, the high electricity of second end receiving grid of transistor T11
VGH is pressed, the control terminal of transistor T11 receives second control signal P [N].The first end of transistor T4 receives grid low-voltage
VGL, the second end of transistor T4 are coupled to output end OE, the control terminal reception pattern selection signal SS of transistor T4.In addition, electric
Hold C1 to be serially connected between the control terminal of transistor T3 and output end OE.
Voltage adjuster 120 is coupled between the first control terminal CE1 and the second control terminal CE2.120 foundation of voltage adjuster
Second control signal P [N] adjusts first control signal Q [N] to provide gate high-voltage VGH, wherein works as second control signal
When P [N] is low voltage potential, voltage adjuster 120 can provide gate high-voltage VGH to draw high the electricity of first control signal Q [N]
Pressure value.
In the present embodiment, voltage adjuster 120 includes transistor T10 and T12, and transistor T10 and T12 can be sequentially
The first control terminal CE1 is series between gate high-voltage VGH.The control terminal of transistor T10 and T12 receive the second control jointly
Signal P [N] processed.
In other embodiments of the present invention, voltage adjuster 120 can only include single a transistor.In fact, voltage tune
The transistor that settable one or more is serially connected in whole device 120, the limitation that quantity is not fixed.And pass through multiple concatenations
Transistor circuit framework, the leaky between node can be reduced.
Voltage adjuster 130 is coupled to the first control terminal CE1.Voltage adjuster 130 is according to mode select signal SR, prime
Gate drive signal G [N-1] or initial pulse signal ST is to adjust first control signal Q [N], wherein when prime gate driving
Signal G [N-1] or initial pulse signal ST is low voltage potential, and when mode select signal SR is also low voltage potential, electricity
Pressure adjuster 130 can drag down first control signal Q [N] according to prime gate drive signal G [N-1] or initial pulse signal ST
Voltage value.
Specifically bright, the voltage adjuster 130 of the present embodiment includes transistor T1 and T2, the control terminal of transistor T1
It is coupled to the first end of transistor T1, and forms the coupling form of diode configuration.In the present embodiment, transistor T1 institute construction
The cathode of diode receive prime gate drive signal G [N-1] or initial pulse signal ST, anode and be then coupled to transistor
The first end of T2.The first end of transistor T2 is coupled to the second end of transistor T1, and the second end of transistor T2 is then coupled to
The control terminal reception pattern selection signal SR of one control terminal CE1, transistor T2.
Voltage adjuster 140 is coupled to the first control terminal CE1.Voltage adjuster 140 is according to rear class gate drive signal G [N
+ 1] first control signal Q [N] is adjusted to provide gate high-voltage VGH, wherein when rear class gate drive signal G [N+1] is
When low voltage potential, voltage adjuster 140 can provide gate high-voltage VGH to draw high the voltage value of first control signal Q [N].
In the present embodiment, voltage adjuster 140 includes transistor T7 and T13, and transistor T7 and T13 sequentially connect
In the first control terminal CE1 between gate high-voltage VGH.The control terminal of transistor T7 and T13 receive rear class grid jointly
Driving signal G [N+1].
In other embodiments of the present invention, voltage adjuster 140 can only include single a transistor.In fact, voltage tune
The transistor that same settable one or more is serially connected in whole device 140, the limitation that quantity is not fixed, by multiple
The circuit framework of the transistor of concatenation reduces the leaky between node.
Voltage adjuster 150 is coupled to the second control terminal CE2.Voltage adjuster 150 is according to mode select signal SS to mention
For gate high-voltage VGH to adjust second control signal P [N], wherein when mode select signal SS is low voltage potential, electricity
Pressure adjuster 150 provides gate high-voltage VGH to draw high the voltage value of second control signal P [N].
In the present embodiment, voltage adjuster 150 includes transistor T9.Transistor T9 be serially connected in the second control terminal CE2 with
Between gate high-voltage VGH, the control terminal reception pattern selection signal SS of transistor T9.It is noted that voltage adjuster
The quantity for the transistor for including in 150 can be one or multiple.Fig. 1 is only used as the example of explanation, not to limit this
The scope of invention.
Voltage adjuster 160 is coupled to the second control terminal CE2.Voltage adjuster 160 is according to reversed clock pulse signal
XCK, mode select signal SR and first control signal Q [N] are to provide reversed clock pulse signal XCK or gate high-voltage
VGH is to adjust second control signal P [N].Voltage adjuster 160 includes transistor T5, T6 and T8, the control terminal of transistor T5
It is coupled to the first end of transistor T5, and forms the coupling form of diode configuration.In the present embodiment, transistor T5 institute construction
The cathode of diode receive reversed clock pulse signal XCK, anode is then coupled to the first end of transistor T6.Transistor T6
First end be coupled to the construction of transistor T5 institute diode anode, the second end of transistor T6 is coupled to the second control terminal
The control terminal reception pattern selection signal SR of CE2, transistor T6.The first end of transistor T8 is coupled to the second of transistor T6
End, the second end of transistor T8 receive gate high-voltage VGH, and the control terminal of transistor T8 receives first control signal Q [N].
About the movement details of shift register circuit 100, referring to Fig. 2 and Fig. 3 A to Fig. 3 H, wherein Fig. 2 shows
The movement oscillogram of the gate drive apparatus of the embodiment of the present invention, Fig. 3 A to Fig. 3 H show the shift LD electricity of the embodiment of the present invention
The equivalent circuit diagram on road.
Referring to figure 2. and Fig. 3 A, at the beginning between in the TA0 of section, gate drive apparatus is in normal operation phase, this
When mode select signal SS be high voltage potential (be equal to gate high-voltage VGH), mode select signal SR is low voltage potential (etc.
In grid low-voltage VGL).When clock signal XCK is low voltage potential (being equal to grid low-voltage VGL) when inverted, voltage
Transistor T5 reverse-conducting in adjuster 150, and transistor T6 can according to low voltage potential mode select signal SR and
It is switched on, whereby so that the voltage value of second control signal P [N] is equal to VGL+ | VTH_T5 |, wherein VTH_T5 is transistor T5
Conducting voltage.
And transistor T10 and T12 in voltage adjuster 120 can be according to being voltage value VGL+ | VTH_T5 | the second control
Signal P [N] processed and be switched on, draw high the voltage value of first control signal Q [N] to provide gate high-voltage VGH.At this point, defeated
The transistor T11 in grade circuit 110 is switched on according to second control signal P [N] out, and the transistor in output-stage circuit 110
T3 is disconnected according to first control signal Q [N], the corresponding N grades of gate drivings for being produced as high voltage potential of output-stage circuit 110
Signal G [N].And at the same time, rear class gate drive signal G [N+1] caused by rear class shift register is similarly high voltage
Current potential (is equal to gate high-voltage VGH).In addition, when the non-shift register circuit for belonging to the first order of output-stage circuit 110, prime
Prime gate drive signal G [N-1] caused by shift register is similarly high voltage potential.
Subsidiary one mentions, at the beginning between in the TA0 of section, transistor T1 in voltage adjuster 130 is according to being equal to high voltage
The prime gate drive signal G [N-1] or starting clock pulse signal ST of current potential (be equal to gate high-voltage VGH) and be disconnected.
Transistor T7, T13 in voltage adjuster 140 are broken according to the rear class gate drive signal G [N+1] for being equal to high voltage potential
It opens.Transistor T4 in transistor T9 and output-stage circuit 110 in voltage adjuster 150 is according to equal to high voltage potential
Mode select signal SS and be disconnected.Transistor T8 in voltage adjuster 160 (it is high to be equal to grid according to high voltage potential is equal to
Voltage VGH) first control signal Q [N] and be disconnected.
It is worth mentioning, voltage adjuster 130 can receive initial pulse signal ST, or also can receive the drive of prime grid
Dynamic signal G [N-1].Voltage adjuster 130 can determine to receive starting clock according to the position of affiliated shift register circuit
Pulse signal ST or prime gate drive signal G [N-1].It is bright in simple terms, when voltage adjuster 130 belongs to the displacement of the first order
When register circuit, voltage adjuster 130 can receive initial pulse signal ST, and belong to the first order when voltage adjuster 130 is non-
Shift register circuit when, voltage adjuster 130 then can receive prime gate drive signal G [N-1].
Then referring to figure 2. and Fig. 3 B.In time interval TA1 between at the beginning after the TA0 of section, gate driving dress
It sets and enters compensated stage.At the same time, mode select signal SR transition is high voltage potential (being equal to gate high-voltage VGH), mould
Formula selection signal SS is then equal to voltage value VGL_L by gate high-voltage VGH transition, wherein voltage value VGL_L is low lower than grid
Voltage VGL.It and is transistor T4 meeting equal to voltage value VGL_L, in output-stage circuit 110 based on mode select signal SS transition
It is switched on according to mode select signal SS, to provide grid low-voltage VGL to charge to output end OE, and makes N grades of grids
The voltage value of driving signal G [N] is pulled low, to generate N grades of gate drive signal G [N] for being equal to grid low-voltage VGL.
It is worth noting that, based on the received mode select signal SS of all shift register circuits institute be it is identical, therefore,
In time interval TA1, the voltage value of N-1 grades of gate drive signal G [N-1] can be drawn according to mode select signal SS synchronization
Down to grid low-voltage VGL, and the voltage value of N+1 grades of gate drive signal G [N+1] equally can be according to mode select signal
SS is synchronized to be pulled low to grid low-voltage VGL.In this way, which gate drive apparatus can make all gate drive signals quilt simultaneously
Enable (drags down), and the compensating movement of the thin film transistor (TFT) of executable all pixels circuit.
On the other hand, voltage adjuster 140 can be switched on according to the rear class gate drive signal G [N+1] being pulled low at this time,
And gate high-voltage VGH is provided to continue to draw high first control signal Q [N].And the transistor T9 in voltage adjuster 150 can be according to
It is switched on according to for the mode select signal SS of voltage potential VGL_L, and provides gate high-voltage VGH to draw high second control signal
P[N].At this point, voltage adjuster 120 is cut off according to the second control signal P [N] being raised.Crystalline substance in output-stage circuit 110
Body pipe T11 is disconnected also according to second control signal P [N], and the transistor T3 in output-stage circuit 110 is controlled according to first
Signal Q [N] continues to be disconnected.
Subsidiary one mentions, transistor T5 in voltage adjuster 160 can be switched on according to reversed clock pulse signal XCK or
It is disconnected, and transistor T6 is then cut off according to the mode select signal SR for being high voltage potential, and transistor T8 foundation
The first control signal Q [N] being raised continues to be disconnected.Transistor T9 meeting foundation in voltage adjuster 150 is voltage potential
The mode select signal SS of VGL_L is cut off.Transistor T2 in voltage adjuster 130 can be according to the mode for being high voltage potential
Selection signal SR is cut off.
Then referring to figure 2. and Fig. 3 C.Time interval TA2 after time interval TA1, gate drive apparatus can be into
Row resetting, to terminate the compensated stage of gate drive apparatus.In time interval TA2, mode select signal SR is by the high electricity of grid
Pressure VGH transition is low voltage potential (being equal to grid low-voltage VGL), and mode select signal SS is turned by grid low-voltage VGL
State is high voltage potential (being equal to gate high-voltage VGH).The transistor T5 meeting foundation in voltage adjuster 150 is low-voltage at this time
The reversed clock pulse signal XCK of current potential (be equal to grid low-voltage VGL) and be switched on, and transistor T6 can be according to for low-voltage
The mode select signal SR of current potential and be switched on so that the voltage value of second control signal P [N] is pulled low to equal to VGL+ |
VTH_T5|.At the same time, transistor T10 and T12 the meeting foundation in voltage adjuster 120 are voltage value VGL+ | VTH_T5 |
Second control signal P [N] and be switched on, drawn high to equal than gate high-voltage with drawing high the voltage value of first control signal Q [N]
VGH。
At this point, the transistor T11 in output-stage circuit 110 is switched on according to second control signal P [N], and output stage is electric
Transistor T3 in road 110 is disconnected according to first control signal Q [N], and output-stage circuit 110 is produced as high voltage potential (etc.
In the N grades of gate drive signal G [N] of gate high-voltage VGH).And at the same time, rear class caused by rear class shift register
Gate drive signal G [N+1], which is synchronized, to be raised as high voltage potential.In addition, working as the non-shifting for belonging to the first order of output-stage circuit 110
When the register circuit of position, prime gate drive signal G [N-1] caused by preceding shift register, which can also be synchronized, to be raised as high electricity
Piezoelectric position.
It should be noted that this time section TA2 in remaining gate drive apparatus action waveforms and operation mode with
It is aforementioned at the beginning between action waveforms in section TA0 (being similarly in normal operation phase) and operation mode it is similar, therefore
This does not repeat to repeat.
Then referring to figure 2. and Fig. 3 D.In time interval TA3, gate drive apparatus enters the first son of write phase
Stage.In time interval TA3, mode select signal SS is maintained high voltage potential (being equal to gate high-voltage VGH), and mode
Selection signal SR is maintained low voltage potential (being equal to grid low-voltage VGL).At this point, the transistor T2 in voltage adjuster 130
It is switched on according to the mode select signal SR for being low voltage potential, and the transistor T1 in voltage adjuster 130 can foundation
Transition is the starting clock pulse signal ST or prime gate drive signal G [N- of low voltage potential (being equal to grid low-voltage VGL)
1] it is switched on, to transmit initial pulse signal ST or prime gate drive signal G [N- by transistor T1, T2 switched on
1] voltage value of first control signal Q [N] is dragged down, at this moment, the voltage value of first control signal Q [N] is equal to VGL+ | VTH_
T1 |, wherein VTH_T1 is the conducting voltage of transistor T1.
As the voltage value of first control signal Q [N] is pulled low, the transistor T8 in voltage adjuster 160 is switched on, and
Transistor T5 is then led according to by gate high-voltage VGH transition for the reversed clock pulse signal XCK of grid low-voltage VGL
It is logical, and transistor T6 is switched on according to mode select signal SR, accordingly with provide reversed clock pulse signal XCK with grid
High voltage VGH draws high second control signal P [N].In this way, which in the present embodiment, second control signal P [N] is in the time
Section TA3 can be raised as equal to the slightly below voltage potential VGH-V2 of gate high-voltage VGH.Wherein, V2 is a deviant, and
And VGH > VGH-V2 > VGL+ | VTH_T5 |.At the same time, voltage adjuster 120 is according to the second control signal P being raised
[N] and be cut off.Subsidiary one mentions, and voltage adjuster 140 is according to the rear class gate drive signal G [N+1] for high voltage potential
It maintains to be cut off.Voltage adjuster 150 then maintains to be cut off according to the mode select signal SS for being high voltage potential.
And at the same time, the transistor T3 in output-stage circuit 110 is led according to the first control signal Q [N] being pulled low
Logical, so that the clock pulse signal CK equal to gate high-voltage VGH charges to output end OE, and then foundation is equal to transistor T11
The second control signal P [N] of voltage potential VGH-V2 is disconnected, and transistor T4 is disconnected according to mode select signal SS maintenance.
Therefore, the voltage value of N grades of gate drive signal G [N] is maintained equal to gate high-voltage VGH.
Then referring to figure 2. and Fig. 3 E.In time interval TA4, gate drive apparatus enters the second son of write phase
Stage.In time interval TA4, the voltage value of initial pulse signal ST or prime gate drive signal G [N-1] are pulled to
In gate high-voltage VGH.Transistor T1 in voltage adjuster 130 is according to the initial pulse signal ST or prime grid being raised
Driving signal G [N-1] and be cut off.On the other hand, clock pulse signal CK is the low electricity of grid by gate high-voltage VGH transition
Press VGL.By maintaining transistor T3 switched on, output-stage circuit 110 provides clock pulse signal CK to fill to output end OE
Electricity is pulled low the voltage value of N grades of gate drive signal G [N] for grid low-voltage VGL.
It should also be noted that the voltage value based on N grades of gate drive signal G [N] is pulled low movement, first control signal
Q [N] can be pulled low a deviant V1 according to the clock pulse signal CK being pulled low.Specifically bright, by produced by capacitor C1
Coupling effect, the voltage value of first control signal Q [N] can further be pulled low to VGL+ | VTH_T1 |-V1, wherein deviating
The size of value V1 is determined according to the ratio of capacitance and the equivalent capacitance value on the first control terminal CE1 of capacitor C1.
And under conditions of the voltage value of first control signal Q [N] can be further pulled low, in voltage adjuster 160
Transistor T8 can continue to be switched on, with continue provide gate high-voltage VGH.At the same time, transistor T5 can be according to by grid
Low-voltage VGL transition be gate high-voltage VGH reversed clock pulse signal XCK and be disconnected.Therefore, second control signal P
The voltage value of [N] can be raised a deviant V2 according to gate high-voltage VGH, so that the voltage value etc. of second control signal P [N]
In gate high-voltage VGH.And the transistor in transistor T10, T12 and output-stage circuit 110 in voltage adjuster 120
T11 can continue to be cut off according to second control signal P [N].Subsidiary one mentions, and voltage adjuster 140 then drives according to rear class grid
Dynamic signal G [N+1] continues to be cut off, the crystal in transistor T9 and output-stage circuit 110 in voltage adjuster 150
Pipe T4 maintains to be cut off according to mode select signal SS.
Then referring to figure 2. and Fig. 3 F.In time interval TA5, gate drive apparatus enters third of write phase
Stage.In time interval TA5, clock pulse signal CK is gate high-voltage VGH by grid low-voltage VGL transition, and anti-
To clock pulse signal XCK by gate high-voltage VGH transition be grid low-voltage VGL.By maintaining transistor T3 switched on,
Output-stage circuit 110 provides clock pulse signal CK to charge to output end OE, makes the voltage of N grades of gate drive signal G [N]
Value is raised as gate high-voltage VGH.
It is worth noting that, the voltage value based on N grades of gate drive signal G [N] is raised movement, the first control letter
Number Q [N] can be pulled to according to the clock pulse signal CK being raised equal to voltage value VGL+ | VTH_T1 |.In the present embodiment
In, first control signal Q [N] can be raised in time interval TA5 as equal to voltage value VGL+ | VTH_T1 |, wherein VGH >
VGL+ | VTH_T1 | > VGL+ | VTH_T1 |-V1.
On the other hand, the voltage value of rear class gate drive signal G [N+1] is pulled low to equal to grid low-voltage VGL.Electricity
Transistor T7 and T13 in pressure adjuster 140 are switched on according to the rear class gate drive signal G [N+1] being pulled low, to mention
It charges for gate high-voltage VGH to first control signal Q [N].And at the same time, the transistor in voltage adjuster 160
T5 is switched on according to reversed clock pulse signal XCK, and transistor T6 is switched on according to mode select signal SR, and it is low to provide grid
Voltage VGL, with transistor T8 provided by charged together with gate high-voltage VGH to second control signal P [N], with continue by
Second control signal P [N] maintains gate high-voltage VGH.Voltage adjuster 120 is according to the second control for gate high-voltage VGH
Signal P [N] processed continues to be cut off.Subsidiary one mentions, and voltage adjuster 130 and voltage adjuster 150 continue to be cut off.
Then referring to figure 2. and Fig. 3 G.In time interval TA6, gate drive apparatus enters the 4th son of write phase
Stage.In time interval TA6, clock pulse signal CK maintains gate high-voltage VGH, and reversed clock pulse signal
XCK maintains grid low-voltage VGL.The voltage value of rear class gate drive signal G [N+1] is maintained equal to grid low-voltage VGL.
Transistor T7 and T13 in voltage adjuster 140 continues to be switched on according to rear class gate drive signal G [N+1], to the
One control signal Q [N] continues to charge, and is pulled to the voltage value of first control signal Q [N] equal to gate high-voltage VGH.
At the same time, in voltage adjuster 160 transistor T8 can according to equal to gate high-voltage VGH first control signal Q [N] and by
Cutting, and transistor T5 then remains switched on according to the reversed clock pulse signal XCK equal to grid low-voltage VGL, and mentions
For reversed clock pulse signal XCK to drag down second control signal P [N] to equal than voltage value VGL+ | VTH_T5 |.
At the same time, voltage adjuster 120 is switched on according to the second control signal P [N] being pulled low, and provides grid
High voltage VGH makes the voltage value of first control signal Q [N] maintain gate high-voltage to charge to first control signal Q [N]
VGH.Subsidiary one is mentioned that voltage adjuster 130 and voltage adjuster 150 continue to be cut off.
And at the same time, the transistor T3 in output-stage circuit 110 is cut according to the first control signal Q [N] being raised
Disconnected, transistor T4 is disconnected according to mode select signal SS maintenance, and transistor T11 is then according to equal to voltage potential VGL+ |
VTH_T5 | second control signal P [N] be switched on, charged with providing gate high-voltage VGH to output end OE, make N grades
The voltage value of gate drive signal G [N] is maintained equal to gate high-voltage VGH.
Then referring to figure 2. and Fig. 3 H.In time interval TA7, gate drive apparatus enter voltage keep the stage, when
Between in the TA7 of section, voltage adjuster 140 is according to the rear class gate drive signal G [N+1] that transition is equal to gate high-voltage VGH
It is cut off.Transistor T5 in voltage adjuster 160 is periodic according to the reversed clock pulse signal XCK of periodical transition
Conducting (when clock signal XCK transition is equal to grid low-voltage VGL when inverted), and to second control signal P [N] period
The charging of property, drives the voltage value of second control signal P [N] to decline and maintain VGL+ | VTH_T5 |, voltage adjuster 120 is then
Continue to be switched on according to second control signal P [N], to charge to first control signal Q [N], drives first control signal Q [N]
Voltage value be raised and maintain gate high-voltage VGH.
Subsidiary one mentions, and the transistor T8 in voltage adjuster 160 can be according to first control signal Q [N] quilt being raised
It disconnects.Voltage adjuster 130 continues to be cut off according to prime gate drive signal G [N-1] or initial pulse signal ST.Voltage tune
Transistor T4 in transistor T9 and output-stage circuit 110 in whole device 150 continues to be cut off according to mode select signal SS.
It is worth noting that, the transistor T3 in output-stage circuit 110 is disconnected according to the first control signal Q [N] being raised, and
Transistor T11 in output-stage circuit 110 then maintains to be switched on according to the second control signal P [N] being pulled low.Such one
Coming, output-stage circuit 110 will charge to output end OE with gate high-voltage VGH via transistor T11 switched on, so that
N grades of gate drive signal G [N] maintain gate high-voltage VGH.
It is not difficult to learn by above description, the gate drive signal being pulled low by transmission step by step, in write phase, grid
Electrode driving device can produce the gate drive signal for being sequentially enabled and (dragging down), and sequentially execute data write-in to multiple pixel columns
Movement.
In conclusion the present invention provides shift register circuit, and grid are formed by the shift register circuit of multi-stage serial connection
Pole driving signal.Gate drive signal proposed by the present invention can provide multiple gate drivings letter of common enable in compensated stage
Number, and the gate drive signal of sequentially enable is generated in write phase, it is dynamic to execute data write-in to provide the sufficiently long time
Make.Can effectively be arranged in pairs or groups the display panel of synchronous mode active Organic Light Emitting Diode, with the compensation time come compensate threshold voltage it
Variation is applied on high-resolution display panel without being limited by panel resolution.In addition, in embodiments of the present invention,
And the leaky of internal node can be reduced come construction voltage adjuster by multiple concatenated transistors, save disappearing for electric power
Consumption.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention, ripe
It knows those skilled in the art and makes various corresponding changes and modifications, but these corresponding changes and change in accordance with the present invention
Shape.
Claims (20)
1. a kind of gate drive apparatus characterized by comprising
Multiple shift register circuits, those shift register circuits are serially connected, and generate multiple gate drive signals respectively, wherein the
N grades of shift register circuit includes:
One output-stage circuit has one first control terminal and one second control terminal to receive a first control signal and one respectively
Second control signal, according to the first control signal, the second control signal and a first mode selection signal to mention
It is charged to an output end for a frequency signal, a gate high-voltage or a grid low-voltage to generate a N grades of gate driving letters
Number；
One first voltage adjuster is coupled between first control terminal and second control terminal, according to second control
Signal processed is to provide the gate high-voltage to adjust the first control signal；
One second voltage adjuster is coupled to first control terminal, drives according to a second mode selection signal, a prime grid
Dynamic signal or an initial pulse signal are to adjust the first control signal；
One tertiary voltage adjuster is coupled to first control terminal, according to a rear class gate drive signal to provide the grid
Very high voltage is to adjust the first control signal；
One the 4th voltage adjuster is coupled to second control terminal, provides according to the first mode selection signal described
Gate high-voltage is to adjust the second control signal；And
One the 5th voltage adjuster is coupled to second control terminal, selects according to a reverse frequency signal, the second mode
Signal and the first control signal are to provide the reverse frequency signal or the gate high-voltage to adjust described second
Control signal.
2. gate drive apparatus according to claim 1, which is characterized in that in a compensated stage, the second voltage tune
Whole device is cut off according to the second mode selection signal, and the first voltage adjuster is cut according to the second control signal
Disconnected, the tertiary voltage adjuster is switched on according to the rear class gate drive signal being pulled low, and it is high to provide the grid
Voltage is to draw high the first control signal.
3. gate drive apparatus according to claim 2, which is characterized in that in the compensated stage, the 4th voltage
Adjuster is switched on according to the first mode selection signal, and provides the gate high-voltage to draw high the second control letter
Number, the 5th voltage adjuster is cut off according to the first control signal and the second mode selection signal.
4. gate drive apparatus according to claim 3, which is characterized in that in the compensated stage, the output stage electricity
Road provides the grid low-voltage according to the first mode selection signal to charge to the output end, and generates described the
N grades of gate drive signals.
5. gate drive apparatus according to claim 2, which is characterized in that in one first sub-stage of a write phase,
The second voltage adjuster according to the second mode selection signal and the prime gate drive signal being pulled low or
The initial pulse signal is switched on, and transmits the prime gate drive signal or the initial pulse signal to drag down described the
One control signal, the first voltage adjuster according to the second control signal be cut off, the tertiary voltage adjuster according to
It is cut off according to the rear class gate drive signal.
6. gate drive apparatus according to claim 5, which is characterized in that in the described first sub- rank in said write stage
Section, the 4th voltage adjuster are cut off according to the first mode selection signal, and the 5th voltage adjuster is according to institute
It states first control signal, the second mode selection signal and the reverse frequency signal being pulled low to be switched on, and provides
The reverse frequency signal and the gate high-voltage are to draw high the second control signal.
7. gate drive apparatus according to claim 5, which is characterized in that in the one second sub- rank in said write stage
Section, the second voltage adjuster are cut according to the prime gate drive signal or the initial pulse signal being raised
Disconnected, the first voltage adjuster is cut off according to the second control signal, and the tertiary voltage adjuster is according to after described
Grade gate drive signal is cut off, and the first control signal is pulled low one first offset according to the frequency signal being pulled low
Value.
8. gate drive apparatus according to claim 7, which is characterized in that in the described second sub- rank in said write stage
Section, the 4th voltage adjuster maintain to be cut off, and the 5th voltage adjuster is according to the first control signal to continue
It is switched on, and provides the gate high-voltage so that the second control signal is drawn high one second deviant.
9. gate drive apparatus according to claim 8, which is characterized in that the output-stage circuit is according to first control
Signal processed generates the N grades of gate drive signals to provide the frequency signal to charge to the output end.
10. gate drive apparatus according to claim 9, which is characterized in that in the sub- rank of a third in said write stage
Section, the second voltage adjuster are cut off according to the prime gate drive signal or the initial pulse signal, and described the
One voltage adjuster is cut off according to the second control signal, and the tertiary voltage adjuster is according to the rear class being pulled low
The pole driving signal is switched on, and provides the gate high-voltage to first control signal charging, the 4th voltage
Adjuster according to the first mode selection signal be cut off, the 5th voltage adjuster according to the first control signal,
The second mode selection signal and the reverse frequency signal being pulled low are switched on, and provide the gate high-voltage with
And the reverse frequency signal is to charge to the second control signal.
11. gate drive apparatus according to claim 10, which is characterized in that in one the 4th sub- rank in said write stage
Section, the second voltage adjuster continue to be cut off, and the first voltage adjuster is according to the second control signal quilt being pulled low
Conducting, and the gate high voltage is provided to charge to the first control signal, tertiary voltage adjuster is according to the rear class
Gate drive signal continues to be switched on to charge to the first control signal, and the 4th voltage adjuster continues to be cut off,
5th voltage adjuster according to the reverse frequency signal and the second mode selection signal to continue to be switched on, and
The reverse frequency signal is provided to drag down the second control signal.
12. gate drive apparatus according to claim 2, which is characterized in that kept for the stage in a voltage, second electricity
Press adjuster to be cut off according to the prime gate drive signal or the initial pulse signal, the first voltage adjuster according to
It is switched on according to second control signal to charge to the first control signal, tertiary voltage adjuster drives according to the rear class grid
Dynamic signal is cut off, and the 4th voltage adjuster is cut off according to the first mode selection signal, the 5th voltage tune
Whole device is periodically switched on according to the reverse frequency signal and the second mode selection signal, and periodically to institute
State second control signal charging.
13. gate drive apparatus according to claim 12, which is characterized in that it is kept for the stage in the voltage, it is described defeated
Grade circuit provides the gate high voltage according to the second control signal to generate the described N grades pole driving letters out
Number.
14. gate drive apparatus according to claim 1, which is characterized in that the output-stage circuit includes:
One the first transistor, first end receive the frequency signal, and the second end of the first transistor is coupled to the output
The control terminal at end, the first transistor receives the first control signal；
One first capacitor is coupled between the control terminal of the first transistor and the output end；
One second transistor, first end are coupled to the output end, and it is high that the second end of the second transistor receives the grid
The control terminal of voltage, the second transistor receives the second control signal；And
One third transistor, first end receive the grid low-voltage, and the second end of the third transistor is coupled to described defeated
The control terminal of outlet, the third transistor receives the first mode selection signal.
15. gate drive apparatus according to claim 1, which is characterized in that the first voltage adjuster includes:
An at least transistor, is coupled in first control terminal and to receive the gate high-voltage, an at least transistor
Control terminal receive the second control signal.
16. gate drive apparatus according to claim 1, which is characterized in that the second voltage adjuster includes:
One diode, cathode receive the prime gate drive signal or the initial pulse signal；And
One the first transistor, first end are coupled to the anode of the diode, and the second end of the first transistor is coupled to institute
The first control terminal is stated, the control terminal of the first transistor receives the second mode selection signal.
17. gate drive apparatus according to claim 1, which is characterized in that the tertiary voltage adjuster includes:
An at least transistor, is coupled in first control terminal and to receive the gate high-voltage, an at least transistor
Control terminal receive the rear class gate drive signal.
18. gate drive apparatus according to claim 1, which is characterized in that the 4th voltage adjuster includes:
An at least transistor, is coupled in second control terminal and to receive the gate high-voltage, an at least transistor
Control terminal receive the first mode selection signal.
19. gate drive apparatus according to claim 1, which is characterized in that the 5th voltage adjuster includes:
One diode, cathode receive the reverse frequency signal；
One the first transistor, first end are coupled to the anode of the diode, and the second end of the first transistor is coupled to institute
The second control terminal is stated, the control terminal of the first transistor receives the second mode selection signal；And
One second transistor, first end are coupled to the second end of the first transistor, the second termination of the second transistor
The gate high-voltage is received, the control terminal of the second transistor receives the first control signal.
20. gate drive apparatus according to claim 1, which is characterized in that in a compensated stage, those gate drivings letter
It number is enabled simultaneously, in a write phase, those gate drive signals are sequentially enabled, and keep stage, those grid in a voltage
Pole driving signal is maintained at the voltage value being disabled；
Wherein, the compensated stage, said write stage and the voltage are kept for the stage sequentially occur.
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| US201862684913P | 2018-06-14 | 2018-06-14 | |
| US62/684,913 | 2018-06-14 | ||
| TW107141083A TWI675359B (en) | 2018-06-14 | 2018-11-19 | Gate driving apparatus |
| TW107141083 | 2018-11-19 |
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