CN110007962A - A kind of instruction-set simulation method based on Code automatic build - Google Patents
A kind of instruction-set simulation method based on Code automatic build Download PDFInfo
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- CN110007962A CN110007962A CN201910175584.9A CN201910175584A CN110007962A CN 110007962 A CN110007962 A CN 110007962A CN 201910175584 A CN201910175584 A CN 201910175584A CN 110007962 A CN110007962 A CN 110007962A
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- instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
Abstract
The instruction-set simulation method based on Code automatic build that the invention discloses a kind of.This method manually develops time-consuming and laborious problem for current instruction set simulator, first saves instruction set information by specific coding rule, then parsed by coded program and extract above-metioned instruction information.By the operation code instructed and each feature segment information, coded program can automatically generate the decoding module code of instruction set simulator;By instruction execution information, coded program can automatically generate instruction set simulator execution module code.This method is suitable for a plurality of types of instruction set, and the programing work amount of developer can be effectively reduced, improve the development efficiency of instruction set simulator, with good application prospect.
Description
Technical field
The present invention relates to instruction-set simulation more particularly to a kind of instruction-set simulation methods based on Code automatic build.
Background technique
The limitation of hardware number is got rid of since instruction set simulator has, operational process adjustable obtains equipment state at any time
The advantages that, it is all widely used in fields such as simulation hardware, chip designs.However, designing and customizing a specific
Instruction set simulator is an extremely complex job.
The technological difficulties of simulator are correctly dummy instruction execution.The implementation procedure of instruction can be divided into: fetching is translated
Code executes three steps.Decoding procedure is mapped to decoding module by simulator, executes step and is then mapped to execution module.It translates
Code module is by matching instruction operation code, determine instruction type, and according to command encoding formats, and each characteristic segments letter is extracted in segmentation
Breath.Under actual conditions, since an instruction set usually contains up to a hundred instructions, and decoding module needs support all instructions class
The identification of type, if therefore instruction set operation code irregular distribution, the workload of manual compiling correlation module code are very big.
Execution module is made of the instruction functions of a whole set of instruction set.Since instruction functions and instruction type correspond, therefore
If instruction set huge number, instruction functions write work and will become very heavy.There are 20 row generations by averagely each instruction functions
Code calculates, and for the instruction set that up to a hundred instruct, then only instruction functions one development just contains thousands of row generations
Code, it is artificial to realize not only time-consuming and laborious but also easy error.
Summary of the invention
It is an object of the invention to for manually realization instruction set simulator decoding module and execution module workload
The problem of big and fallibility, provide a kind of instruction-set simulation method based on Code automatic build.
The purpose of the present invention is achieved through the following technical solutions: a kind of instruction set mould based on Code automatic build
Quasi- method, specifically comprises the following steps:
(1) all instructions is concentrated to encode target instruction target word, call instruction coding, and all instructions coding is summarized into preservation
Into instruction set encoding file;
(2) the instruction set encoding file of read step 1 summarizes the characteristic segments distribution situation of all instructions, generates instruction knot
Structure body;
(3) the instruction set encoding file of read step 1 extracts the operation code distribution of all instructions, and by operation code length
Descending sort is made to distribution.It is followed successively by and is distributed the corresponding decoding code of generation, be finally aggregated into complete instruction-set simulation
Device decoding module;
(4) the instruction set encoding file of read step 1 extracts the execution information of every instruction, is generated according to execution information
Instruction functions, all instructions function collectively constitute the execution module of instruction simulation device;
(5) instruction set simulator decoding module is by matching instruction operation code determine instruction type, and extracts each spy of instruction
Levy segment information.Instruction set simulator execution module executes instruction respective operations according to instruction type.Two modules collectively constitute instruction
Set simulator.
Further, in the step 1, instruction encoding has recorded the format information and execution information of instruction.Any one
The coded representation of instruction are as follows:
NA: instruction name
Characteristic segments coding
DT: data type operands
EX: instruction execution expression formula
(DE: delay period number)
Characteristic segments encode the distribution situation of each characteristic segments of recording instruction, and coded format is " characteristic segments name [position] ".It will refer to
All characteristic segments all press above-mentioned said shank in enabling, and connect combination, and the characteristic segments coding of whole instruction can be obtained.
Further, the step 2 specifically: order structure body is to save single in instruction set simulator operational process to refer to
The data structure of information is enabled, saves and instructs each feature segment information and instruction functions pointer.Instruction functions are generated in structural body to refer to
Needle attribute.Characteristic segments attribute is generated by following methods: traversal instruction set encoding file concludes the feature that entire instruction set includes
Section type, and count each feature segment length.Characteristic segments of the same name if it exists, length are remembered by maximum value.According to feature segment length,
Each characteristic segments attribute of the same name is defined in order structure body.
Further, the step 3 specifically: extract all instructions operation code distribution, and by operation code length to point
Cloth makees descending sort.It is followed successively by each operation code distribution and generates identification sentence, and wrap up extracting under the distribution with identification sentence and instruct
The code of feature segment information.Instruct each characteristic segments information preservation in the order structure body attribute of the same name that step 2 defines.At every
The decoding code end of instruction carries out assignment to the function pointer of order structure body, and function name Uniform Name is op_NA,
Middle NA is the instruction name in coding rule.
Further, the step 4 specifically: generate an instruction functions, instruction functions Uniform Name for every instruction
For op_NA.All instructions function can modular division be statement variable, assigned variable, execute operation and result to write back four big
Module.Wherein, the DT coding in instruction encoding is mapped as statement variable and assigned variable module, and EX coding is mapped as executing
Operation module, DT and DE coding are mapped as result and write back module.
The invention has the advantages that developer only need to be by the command information in specific format typing instruction manual, i.e.,
Decoding function and instruction functions can be automatically generated, the workload for developing novel instruction set simulator is effectively reduced.
Detailed description of the invention
Fig. 1 is this method flow chart.
Specific embodiment
A kind of instruction-set simulation method based on Code automatic build of the present invention, specifically comprises the following steps:
1, all instructions is concentrated to encode target instruction target word, call instruction coding, and all instructions coding is summarized into preservation
Into instruction set encoding file.The coded representation of any one instruction are as follows:
NA: instruction name
Characteristic segments coding
DT: data type operands
EX: instruction execution expression formula
(DE: delay period number)
Characteristic segments encode the distribution situation of each characteristic segments of recording instruction, and coded format is " characteristic segments name [position] ".It will refer to
All characteristic segments all press above-mentioned said shank in enabling, and connect combination, and the characteristic segments coding of whole instruction can be obtained.Wherein,
Since not all instruction all includes delay period, therefore DE coding is marked with bracket.
2, the instruction set encoding file of read step 1 summarizes the characteristic segments distribution situation of all instructions, generates order structure
Body;
Order structure body is the data structure that individual instructions information is saved in instruction set simulator operational process, saves instruction
Each feature segment information and instruction functions pointer.Instruction functions pointer attribute is generated in structural body.Characteristic segments attribute passes through following
Method generates: traversal instruction set encoding file concludes the characteristic segments type that entire instruction set is included, and count each feature segment length
Degree.Characteristic segments of the same name if it exists, length are remembered by maximum value.According to feature segment length, definition and each spy in order structure body
Levy section attribute of the same name.If characteristic segments src length is the i.e. recordable characteristic segments information of 5,1 byte, therefore characteristic segments attribute can define
For char src.
3, the instruction set encoding file of read step 1 extracts the operation code distribution of all instructions, and by operation code length pair
Descending sort is made in distribution.It is followed successively by and is distributed the corresponding decoding code of generation, be finally aggregated into complete instruction set simulator
Decoding module;
The operation code distribution of all instructions is extracted, and descending sort is made to distribution by operation code length.It is followed successively by each operation
Code distribution generates identification sentence, and the code that instruction features segment information is extracted under the distribution is wrapped up with identification sentence.Instruct each spy
Sign segment information is stored in the order structure body attribute of the same name of step 2 definition.At the decoding code end that every instructs, to instruction
The function pointer of structural body carries out assignment, and function name Uniform Name is op_NA, and wherein NA is the instruction name in coding rule.
For individual instructions, instruction set simulator determines its instruction functions pointer by decoding module, and is transferred and held by the pointer
The corresponding instruction functions of row module.
4, the instruction set encoding file of read step 1 extracts the execution information of every instruction, is referred to according to execution information generation
Function is enabled, all instructions function collectively constitutes the execution module of instruction simulation device;
An instruction functions are generated for every instruction, instruction functions Uniform Name is op_NA.All instructions function can mould
Block is divided into statement variable, assigned variable, execution operation and result and writes back four module.Wherein, the DT coding of instruction is reflected
It penetrates to state variable and assigned variable module, EX coding is mapped as executing operation module, and DT and DE coding are mapped as result
Write back module.
Claims (5)
1. a kind of instruction-set simulation method based on Code automatic build, which is characterized in that specifically comprise the following steps:
(1) all instructions is concentrated to encode target instruction target word, call instruction coding, and all instructions coding is summarized into preservation and is extremely referred to
It enables in collection coding file.
(2) the instruction set encoding file of read step 1 summarizes the characteristic segments distribution situation of all instructions, generates order structure body.
(3) the instruction set encoding file of read step 1, extract all instructions operation code distribution, and by operation code length to point
Cloth makees descending sort.It is followed successively by and is distributed the corresponding decoding code of generation, be finally aggregated into complete instruction set simulator and translate
Code module.
(4) the instruction set encoding file of read step 1 extracts the execution information of every instruction, is generated and is instructed according to execution information
Function, all instructions function collectively constitute the execution module of instruction simulation device.
(5) instruction set simulator decoding module is by matching instruction operation code determine instruction type, and extracts each characteristic segments of instruction
Information.Instruction set simulator execution module executes instruction respective operations according to instruction type.Two modules collectively constitute instruction set mould
Quasi- device.
2. the instruction-set simulation method according to claim 1 based on Code automatic build, characterized in that the step 1
In, instruction encoding has recorded the format information and execution information of instruction.The coded representation of any one instruction are as follows:
NA: instruction name
Characteristic segments coding
DT: data type operands
EX: instruction execution expression formula
(DE: delay period number)
Characteristic segments encode the distribution situation of each characteristic segments of recording instruction, and coded format is " characteristic segments name [position] ".In instructing
All characteristic segments all press above-mentioned said shank, and connect combination, and the characteristic segments coding of whole instruction can be obtained.
3. the instruction-set simulation method according to claim 1 based on Code automatic build, characterized in that the step 2
Specifically: order structure body is the data structure that individual instructions information is saved in instruction set simulator operational process, saves instruction
Each feature segment information and instruction functions pointer.Instruction functions pointer attribute is generated in structural body.Characteristic segments attribute passes through following
Method generates: traversal instruction set encoding file concludes the characteristic segments type that entire instruction set includes, and count each feature segment length
Degree.Characteristic segments of the same name if it exists, length are remembered by maximum value.According to feature segment length, each feature is defined in order structure body
Duan Tongming attribute.
4. the instruction-set simulation method according to claim 1 based on Code automatic build, characterized in that the step 3
Specifically: the operation code distribution of all instructions is extracted, and descending sort is made to distribution by operation code length.It is followed successively by each operation code
Distribution generates identification sentence, and the code that instruction features segment information is extracted under the distribution is wrapped up with identification sentence.Instruct each feature
Segment information is stored in the order structure body attribute of the same name of step 2 definition.At the decoding code end that every instructs, instruction is tied
The function pointer of structure body carries out assignment, and function name Uniform Name is op_NA, and wherein NA is the instruction name in coding rule.
5. the instruction-set simulation method according to claim 1 based on Code automatic build, characterized in that the step 4
Specifically: an instruction functions are generated for every instruction, instruction functions Uniform Name is op_NA.All instructions function can mould
Block is divided into statement variable, assigned variable, execution operation and result and writes back four module.Wherein, the DT in instruction encoding is compiled
Code is mapped as statement variable and assigned variable module, and EX coding is mapped as executing operation module, and DT and DE coding are mapped
Module is write back for result.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110572160A (en) * | 2019-08-01 | 2019-12-13 | 浙江大学 | Compression method for decoding module code of instruction set simulator |
CN110597554A (en) * | 2019-08-01 | 2019-12-20 | 浙江大学 | Automatic generation optimization method for instruction function of instruction set simulator |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1653446A (en) * | 2002-04-10 | 2005-08-10 | 坦斯利卡公司 | High-performance hybrid processor with configurable execution units |
CN101034351A (en) * | 2007-01-05 | 2007-09-12 | 浙江大学 | Emulator generating method based on component |
CN101542434A (en) * | 2006-11-21 | 2009-09-23 | 日本电气株式会社 | Command operation code generation system |
CN101751373A (en) * | 2008-11-28 | 2010-06-23 | 上海芯豪微电子有限公司 | Configurable multi-core/many core system based on single instruction set microprocessor computing unit |
CN102339252A (en) * | 2011-07-25 | 2012-02-01 | 大连理工大学 | Static state detecting system based on XML (Extensive Makeup Language) middle model and defect mode matching |
US20120101791A1 (en) * | 2010-10-20 | 2012-04-26 | International Business Machines Corporation | Controlling simulation systems |
CN102567164A (en) * | 2011-12-23 | 2012-07-11 | 中国科学院自动化研究所 | Instruction set batch testing device and method for processor |
CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
CN104317715A (en) * | 2014-10-30 | 2015-01-28 | 南京富士通南大软件技术有限公司 | Simulator based automatic functional test implementation method for central processing unit instruction sets |
CN106776281A (en) * | 2016-11-22 | 2017-05-31 | 浙江大学 | A kind of instruction set simulator verification method based on source code pitching pile |
CN106844195A (en) * | 2016-12-22 | 2017-06-13 | 福建瑞之付微电子有限公司 | A kind of method of testing based on the test of unified instruction collection |
CN109189479A (en) * | 2018-10-12 | 2019-01-11 | 西安微电子技术研究所 | A kind of parallel automatic verification method for processor instruction set |
-
2019
- 2019-03-08 CN CN201910175584.9A patent/CN110007962A/en active Pending
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1653446A (en) * | 2002-04-10 | 2005-08-10 | 坦斯利卡公司 | High-performance hybrid processor with configurable execution units |
CN101542434A (en) * | 2006-11-21 | 2009-09-23 | 日本电气株式会社 | Command operation code generation system |
CN101034351A (en) * | 2007-01-05 | 2007-09-12 | 浙江大学 | Emulator generating method based on component |
CN101751373A (en) * | 2008-11-28 | 2010-06-23 | 上海芯豪微电子有限公司 | Configurable multi-core/many core system based on single instruction set microprocessor computing unit |
US20120101791A1 (en) * | 2010-10-20 | 2012-04-26 | International Business Machines Corporation | Controlling simulation systems |
CN102339252A (en) * | 2011-07-25 | 2012-02-01 | 大连理工大学 | Static state detecting system based on XML (Extensive Makeup Language) middle model and defect mode matching |
CN102567164A (en) * | 2011-12-23 | 2012-07-11 | 中国科学院自动化研究所 | Instruction set batch testing device and method for processor |
CN102902906A (en) * | 2012-09-26 | 2013-01-30 | 中国航天科技集团公司第九研究院第七七一研究所 | Microprocessor instruction set validation method |
CN104317715A (en) * | 2014-10-30 | 2015-01-28 | 南京富士通南大软件技术有限公司 | Simulator based automatic functional test implementation method for central processing unit instruction sets |
CN106776281A (en) * | 2016-11-22 | 2017-05-31 | 浙江大学 | A kind of instruction set simulator verification method based on source code pitching pile |
CN106844195A (en) * | 2016-12-22 | 2017-06-13 | 福建瑞之付微电子有限公司 | A kind of method of testing based on the test of unified instruction collection |
CN109189479A (en) * | 2018-10-12 | 2019-01-11 | 西安微电子技术研究所 | A kind of parallel automatic verification method for processor instruction set |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110572160A (en) * | 2019-08-01 | 2019-12-13 | 浙江大学 | Compression method for decoding module code of instruction set simulator |
CN110597554A (en) * | 2019-08-01 | 2019-12-20 | 浙江大学 | Automatic generation optimization method for instruction function of instruction set simulator |
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Application publication date: 20190712 |