CN109189479A - A kind of parallel automatic verification method for processor instruction set - Google Patents
A kind of parallel automatic verification method for processor instruction set Download PDFInfo
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- CN109189479A CN109189479A CN201811190340.XA CN201811190340A CN109189479A CN 109189479 A CN109189479 A CN 109189479A CN 201811190340 A CN201811190340 A CN 201811190340A CN 109189479 A CN109189479 A CN 109189479A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
Abstract
The invention discloses a kind of parallel automatic verification methods for processor instruction set, automatically generate command verification use-case first；Then checking case is emulated on RTL circuit, monitors simulation result；The checking case that step 1 obtains is handled through processor reference model simultaneously, calculates expected result；Format consistency treatment finally is carried out to simulation result and expected result, is then compared, when the two result is consistent, then simulation result is correct；When the two result is inconsistent, then simulation result mistake, and generation error log.The method of the present invention can carry out efficient, comprehensively and accurately command simulation verifying within the limited time, to guarantee the correctness of chip functions.
Description
Technical field
The invention belongs to the verifying fields of digital integrated electronic circuit processor, and in particular to a kind of for processor instruction set
Parallel automatic verification method.
Background technique
With the continuous expansion of digital integrated electronic circuit scale, the function of integrated chip becomes increasingly complex, the instruction number of support
Mesh is more and more, and one for having become a development for restricting chip checking for the verifying of digital integrated electronic circuit instruction is important
Factor, and command verification is because clarifying space is very huge, verification result inspection lacks automatic method, controls class, floating-point class
Expected result is instructed to calculate more difficult, therefore the verifying about instruction also becomes one of Contemporary Digital integrated circuit verification
Problem.In order to guarantee the correctness of processor function, it must just write high-volume checking case and carry out authentication to it, rely on
Manpower manual writes checking case and checks that verification result will be one within the project life cycle and be difficult the thing completed.Therefore,
Need to find a kind of method to improve the efficiency of command verification and comprehensive, it is imperative.
Currently, less about the verifying documents and materials of digital integrated electronic circuit processor both at home and abroad, it is known that verification technique and
Practical operable method is also relatively fewer, does not form a kind of command verification method of automation still.
Summary of the invention
The present invention verifies the huge challenge of clarifying space faced for digital integrated electronic circuit processor, and proposing one kind can
Command verification method that is efficient, comprehensively and accurately automating is carried out in finite time, ensure that the spreadability of processor instruction
And correctness.
In order to achieve the above objectives, the present invention adopts the following technical scheme:
A kind of parallel automatic verification method for processor instruction set, comprising the following steps:
Step 1: command verification use-case automatically generates；
Step 2: the checking case batch that step 1 obtains being submitted on supercomputer server, is carried out on practical RTL circuit
The parallel artificial of multiple tasks monitors simulation result；The checking case that step 1 obtains is carried out through processor reference model simultaneously
Processing calculates expected result；
Step 3: format consistency treatment being carried out to simulation result and expected result, is then compared, when the two result
When consistent, then simulation result is correct；When the two result is inconsistent, then simulation result mistake；And generate result log file.
Further, step 1 specifically includes the generation of individual instructions checking case and dependent instruction checking case generates.
Further, individual instructions checking case generating process is as follows:
A) analysis instruction collection feature extracts the parameter of input；
B) all random and boundary operand, address and the condition field that instruction needs are generated according to the parameter of step a) input
Etc. data；
C) auxiliary and instruction sequence to be verified are generated according to the data that step b) is obtained；The ginseng inputted simultaneously according to step a)
Number generates result output order sequence, for checking register value, mode bit and address date etc.；The auxiliary and finger to be verified
Sequence and result output order sequence is enabled to collectively constitute individual instructions checking case, the checking case of generation has traversed in step b)
All data.
Further, dependent instruction checking case generating process is as follows:
A) 2 three instruction 1, the instruction strip number of insertion and instruction input parameters are introduced；
B) classified according to processor pipeline structure, instruction operands type and register type to instruction；
C) according to the classification in step b) provide the read-write cycle of every class command register and memory in a pipeline and
Relevance parameter between instruction class；
D) according to the correlation of the classification results of step b) and step c) the parameter decision instruction 1 and instruction 2 generated, if
Correlation then enumerates all pipelining conflict types, generates corresponding command verification sequence, and adds auxiliary instruction for preparing
Operand and output are as a result, be finally printed as text formatting output；If uncorrelated, ignore, does not export any instruction sequence；
E) text that step d) is generated is split into etc. to several checking cases of sizes according to custom size.
Further, processor reference method for establishing model is as follows in step 2:
A) the checking case binary file after reading checking case file or compiling；
B) text-processing is carried out according to the type of step a) (i.e. compiling or uncompiled) respectively, to every instruction distribution one
The parameters such as instruction, register type, register ID, address, condition field and immediate are extracted in a address PC；
C) register model function is constructed；
D) memory model function is constructed；
E) the computation model function of every instruction is established according to instruction set handbook, the computation model function is supported a certain
All instructions of processor；And the floating point instruction in instruction includes floating point instruction model and floating-point binary model, calculated result
It can be defined with spec completely the same；
F) by step b) extract parameter be input in the computation model function of step e), obtain calculated result and in real time more
Newly into corresponding register and memory；
G) print result is into text file.
Compared with prior art, the invention has the following beneficial technical effects:
A kind of method that the present invention realizes object oriented processor instruction set simulation verifying, may be implemented by this method to not
The automatic Verification of same type processor instruction set instruction, and the automated analysis for realizing result compares, it can be with minimum
Man power and material most adequately and reliably verified within the limited time；The automatic Verification constructed by this method is flat
Each level division of labor of platform is clear, and all parts are relatively independent, have very high reusability；The reference mould constructed simultaneously by this method
The not excessive constraint of type can according to need be replaced using the master pattern for meeting relevant criterion completely, therefore for
The design to be measured of various criterion has universality.
Detailed description of the invention
Fig. 1 is present invention automation command verification method flow and composed structure；
Fig. 2 is processor instruction reference model of the present invention；
Fig. 3 is that checking case automatically generates environment.
Specific embodiment
Present invention is further described in detail with reference to the accompanying drawing:
The present invention problem huge for processor clarifying space, the processor instruction verification method proposed can be realized certainly
It is dynamic to generate a large amount of single and intersect instruction checking case；Can real simulation processor operating condition, can automatic identification refer to
It enables, automatically generates expected result, solve that jump instruction destination address is difficult to control, difficult inquiry, expected result can not calculate automatically
Etc. problems；It can also realize batch parallel artificial and automaticly inspect simulation result, while generate result log file, convenient for quickly fixed
Position, problem analysis improve the spreadability and efficiency of verifying emulation.
This method ideally, i.e., is not influenced by time, manpower etc., can traverse every instruction, each deposit
Operand in device, each allowed band can carry out N grades of instruction cross validations.Its feature is specifically included that be developed by C language
A set of processor instruction reference model, realizes processor instruction operational model, and which includes jump class instructions, floating-point class
Instruction and the instruction of various vector classes etc.；Checking case is write by C language and Perl language and automatically generates part, to instruction and number
According to various constraints are carried out, corresponding checking case file is exported, including individual instructions two parts related to instruction, to protect
The comprehensive of command verification is demonstrate,proved；By practical Perl language development a set of integrated compiling, emulation, result than peering from
Dynamicization simulated environment.Inventive solution is as follows thus:
The automation command verification method is in instruction references model, verifying excitation build environment, automation simulation verifying
On the basis of three basic platforms of environment, corresponding script is write using Perl language and is combined, processor instruction is realized
That verifies is increasingly automated.Its main working process and component part are as shown in Figure 1.
Firstly, according to processor instruction set feature using C language reference model of the exploitation based on DUV as shown in Fig. 2, realizing
The function of all instructions that processor is supported.Reference model read first native assembler file (such as: inst_test.asm),
For the instruction of access control class, LABEL joined in instruction, jump to carry out instruction, the command verifications such as instruction cycles.But
LABEL can not be but compiled into corresponding address data by compiler, therefore be joined in reference model and converted correspondence for LABEL
Address date program, then by the assembler after conversion be output to text file (such as: pre_inst_test.asm)
In, it is compiled for compiler.Reference model reads pretreated file again, is that every instruction distributes an address PC,
The executive condition of analog processor pointer.After every instruction execution, the address of PC pointer is calculated, according to the ground of PC pointer
Location executes next instruction, then with the operating condition of real simulation processor, can realize normal sequence execution, the program of program
Jump, program circulation, into trap service routine, into interrupt service routine situations such as, more solve jump instruction, interruption,
Trap etc. instructs the problems such as destination address is difficult to control, difficult inquiry, and expected result can not calculate automatically.Simultaneously by checking case
The middle specific instruction of insertion can control DUV and whether reference model exports simulation result and expected result (expect_
Result.txt), so that the control whether checked for result realized.
Secondly, automatically generate checking case automatically generate part be according to verifying demand using C language and Perl language into
Row exploitation, by being constrained accordingly instruction and data, so that corresponding checking case is exported, the verifying which generates
Use-case mainly includes the individual instructions (register transfer class, memory read/write class calculate class and control class etc.) and phase of instruction set
Checking case two parts of instruction (data are related, control correlation, resource correlation etc.) are closed, structure is as shown in Figure 3.Individual instructions
Part is automatically generated, the personnel that verify only need to select instruction to be tested, configuration verification mode is traversal, certain specific condition (shape
State position, degree of parallelism and addressing system etc.) corresponding single checking case can be automatically generated；According to processor pipeline design
Feature, be broadly divided into three kinds of associative modes under normal circumstances: data are related, and instruction is written and read register in different flowing water sections
Operation is divided into RAW (Read After Write) read-after-write, related two types of WAW (Write After Write) write after write
Type；Control is related, pipeline stall caused by transfer instruction；Resource is related, and when the assembly line of instruction executes, generation is same
The identical pipeline resource of clock cycle contention causes resource related, and also referred to as structure is related；Assembly line punching in correlation
Prominent problem, the present invention carry out the thinking of checking case generation are as follows: firstly, the generation mechanism of clear pipelining conflict, instruction is pressed
Specific principle is classified；Then, enumerating the type of all possible pipeline hazard, (including data collision, control are related, knot
Structure correlation etc.), determine whether to generate correlation；Finally, according to whether generation correlation, automatically generates corresponding proving program.In structure
Instruction is classified when building build environment, merger improves the efficiency of verifying its object is to reduce the quantity of verifying excitation.
In general, unique principle that instruction divides is to instruct the influence of convection current water conflict, deficiency is that automatically generating verifying excitation compares
Difficulty, because verifying excitation, therefore this can not be directly obtained from instruction type if same class instruction has different instruction syntaxes
Instruction is divided into several points by the rule such as flowing structure, instruction operands register type that invention is designed according to par-ticular processor
Class.Then it according to each instruction classification, provides between every class command register read-write cycle in a pipeline and instruction class
With the presence or absence of correlation, and if it exists, then call and automatically generate incentive programme, generate verifying excitation.Simultaneously as processor program is deposited
The limitation of storage area space size needs to carry out certainly the command verification use-case that part generates to checking case size in the presence of limiting
It adapts to split to adapt to the requirement of processor program memory block space size.Processor instruction verifying is realized by above method
The classification of use-case automatically generates part.
Finally, if it is also very huge for carrying out simulation work amount to above-mentioned checking case using traditional simulated environment
's.For this purpose, construct a kind of command simulation environment of automation based on Perl in the present invention, by the environment realize compiling,
The full-automation of emulation, result than peering is run.Verifying personnel only need that all verifyings to be tested are initially motivated title
It arranges into a text, simulation run order is then executed, without checking simulation scenarios, meeting after emulation in real time
It can quickly be positioned according to emulation comparison result, problem analysis, while the expected result verifying different from simulation result being motivated
Title be input in specified file (such as: wrong_case.txt), after emulation, the personnel that verify only need to check
Whether there is new verifying excitation title to increase in wrong_case.txt, so that it may which all verifyings of judgement this time batch emulation swash
There is which verifying excitation mistake occur in encouraging.In addition, simulation time will if emulated using conventional authentication use-case sequence
Can be very huge, for this purpose, increasing the parallel artificial mechanism of checking case in verification environment of the invention, i.e., provided according to server
Source can configure in verification environment while run the maximum number of use-case, that is, configurable multi-purpose example parallel artificial be realized, thus pole
Big shortens checking case runing time.
Device command verification environment through this process only need to be according to particular, instruction set the characteristics of, configures relevant parameter and mentions
For relevant verifying demand, the command verification of associative processor can be efficiently quickly finished, improves verification efficiency significantly.
Below with reference to embodiment, the present invention will be described in detail:
The command verification for applying the present invention to certain multi-core processor chip generates hundreds of thousands of multiple test using the invention
Use-case is demonstrate,proved, up to billions of instructions complete and refer to substantially with 12 kinds of condition bits, 3 kinds of degree of parallelisms, 30 kinds of addressing systems etc.
It enables, jump instruction, structure enable the verifyings of the complicated orders such as 40 class instruction, noncanonical format floating point instructions.The set verification platform from
Verifying excitation, which is generated to result inspection, to be realized increasingly automated, and the personnel that verify only need to select individual instructions or friendship to be tested
Instruction sequence is pitched, the range that constraint manipulation number is chosen, by instruction input to the interface of verification platform, verification platform can be automatically performed
The a series of work such as verifying excitation generation, compiling, parallel artificial, result inspection, people is liberated from cumbersome, duplicate work
Out.
Claims (5)
1. a kind of parallel automatic verification method for processor instruction set, which comprises the following steps:
Step 1: automatically generating command verification use-case；
Step 2: the checking case batch that step 1 obtains being submitted on supercomputer server, is carried out on practical RTL circuit multiple
The parallel artificial of task monitors simulation result；The checking case that step 1 is obtained simultaneously through processor reference model at
Reason calculates expected result；
Step 3: format consistency treatment being carried out to simulation result and expected result, is then compared, when the two result is consistent
When, then simulation result is correct；When the two result is inconsistent, then simulation result mistake；And generate result log file.
2. a kind of parallel automatic verification method for processor instruction set according to claim 1, which is characterized in that
Step 1 specifically includes the generation of individual instructions checking case and dependent instruction checking case generates.
3. a kind of parallel automatic verification method for processor instruction set according to claim 2, which is characterized in that
Individual instructions checking case generating process is as follows:
A) analysis instruction collection feature extracts the parameter of input；
B) all random and boundary operand, address and the condition field number that instruction needs are generated according to the parameter of step a) input
According to；
C) auxiliary and instruction sequence to be verified are generated according to the data that step b) is obtained；Parameter simultaneously according to step a) input is raw
At result output order sequence, for checking register value, mode bit and address date；The auxiliary and instruction sequence to be verified
And result output order sequence collectively constitutes individual instructions checking case.
4. a kind of parallel automatic verification method for processor instruction set according to claim 2, which is characterized in that
Dependent instruction checking case generating process is as follows:
A) 2 three instruction 1, the instruction strip number of insertion and instruction input parameters are introduced；
B) classified according to processor pipeline structure, instruction operands type and register type to instruction；
C) every class command register and memory read-write cycle in a pipeline and instruction are provided according to the classification in step b)
Relevance parameter between class；
D) according to the correlation of the classification results of step b) and step c) the parameter decision instruction 1 and instruction 2 generated, if phase
Close, then enumerate all pipelining conflict types, generate corresponding command verification sequence, and add auxiliary instruction for prepare behaviour
It counts and exports as a result, being finally printed as text formatting output；If uncorrelated, ignore, does not export any instruction sequence；
E) text that step d) is generated is split into etc. to several checking cases of sizes according to custom size.
5. a kind of parallel automatic verification method for processor instruction set according to claim 1, which is characterized in that
Processor reference method for establishing model is as follows in step 2:
A) the checking case binary file after reading checking case file or compiling；
B) text-processing is carried out according to the type of step a) respectively, distributes an address PC to every instruction, extracts instruction, deposit
Device type, register ID, address, condition field and immediate parameter；
C) register model function is constructed；
D) memory model function is constructed；
E) the computation model function of every instruction is established according to instruction set handbook, the computation model function supports a certain processing
All instructions of device；And the floating point instruction in instruction includes floating point instruction model and floating-point binary model；
F) the step b) parameter extracted is input in the computation model function of step e), obtains calculated result and real-time update arrives
In corresponding register and memory；
G) print result is into text file.
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| CN112579378A (en) * | 2020-12-24 | 2021-03-30 | 西安翔腾微电子科技有限公司 | Automatic generation method of simulation picture of GPU chip virtual verification platform |
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| CN110134580A (en) * | 2019-04-01 | 2019-08-16 | 深圳云天励飞技术有限公司 | Processor verification method and Related product |
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| CN110457743A (en) * | 2019-06-27 | 2019-11-15 | 芯翼信息科技(上海)有限公司 | A kind of chip detecting method based on FPGA |
| CN110457743B (en) * | 2019-06-27 | 2023-12-05 | 芯翼信息科技(上海)有限公司 | Chip detection method based on FPGA |
| CN112463624A (en) * | 2020-12-07 | 2021-03-09 | 中国电子科技集团公司第五十八研究所 | CPU verification platform based on Systemverilog |
| CN112579378A (en) * | 2020-12-24 | 2021-03-30 | 西安翔腾微电子科技有限公司 | Automatic generation method of simulation picture of GPU chip virtual verification platform |
| CN112579378B (en) * | 2020-12-24 | 2024-04-19 | 西安翔腾微电子科技有限公司 | Automatic generation method of simulation pictures of GPU chip virtual verification platform |
| WO2023065309A1 (en) * | 2021-10-22 | 2023-04-27 | 华为技术有限公司 | Circuit design method and apparatus |
| CN115658414A (en) * | 2022-12-29 | 2023-01-31 | 中科亿海微电子科技（苏州）有限公司 | RISC-V architecture processor core-based function verification method and platform |
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