CN110007712B - Method, apparatus, computer device and storage medium for reducing digital clock frequency error - Google Patents
Method, apparatus, computer device and storage medium for reducing digital clock frequency error Download PDFInfo
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- CN110007712B CN110007712B CN201910242873.6A CN201910242873A CN110007712B CN 110007712 B CN110007712 B CN 110007712B CN 201910242873 A CN201910242873 A CN 201910242873A CN 110007712 B CN110007712 B CN 110007712B
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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Abstract
The invention discloses a method, a device, computer equipment and a storage medium for reducing digital clock frequency error, wherein the method comprises the steps of configuring controller parameters; entering a calibration mode; inquiring whether the calibration is completed; if yes, writing the saved delay value of the main delay into a parameter register; the configuration parameter register enters a clock oscillation mode to generate an internal clock according to a delay value of the main delay; and turning off the external crystal oscillator clock. The invention generates the reference clock through the internal clock gating, then carries out phase locking on the pre-delay internal clock generated by the parameter of the pre-delay according to the reference clock, generates the internal clock according to the delay value of the main delay after the phase locking is finished, and can close the external crystal oscillator clock after the internal clock is obtained, thereby achieving the purposes of reducing the power consumption and reducing the frequency error of the digital clock.
Description
Technical Field
The present invention relates to a solid state disk, and more particularly, to a method, an apparatus, a computer device, and a storage medium for reducing digital clock frequency error.
Background
The clock source of the internal chip of the solid state disk generally comes from an external crystal and provides a clock for the internal chip PLL or logic through a special clock IO. In the application of low power consumption, partial logic is powered off, the part which is not powered off still needs to provide a clock, and if the chip cannot provide an independent clock, the clock IO cannot be turned off, so that energy consumption is required at all. In addition, under different manufacturing processes, the frequency error of the clock generated by the digital clock is large, and the special scenes of the clock requiring high precision are not met.
Disclosure of Invention
It is an object of the present invention to overcome the disadvantages of the prior art and to provide a method, an apparatus, a computer device and a storage medium for reducing digital clock frequency errors.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for reducing digital clock frequency error, the method comprising:
configuring controller parameters;
entering a calibration mode;
inquiring whether the calibration is completed;
if yes, writing the saved delay value of the main delay into a parameter register;
the configuration parameter register enters a clock oscillation mode to generate an internal clock according to a delay value of the main delay;
and turning off the external crystal oscillator clock.
The further technical scheme is as follows: the step of configuring the controller parameters specifically comprises the following steps:
configuring parameters of a front delay to generate a front delay internal clock;
the reference clock is generated by internal clock gating.
The further technical scheme is as follows: the step of entering the calibration mode specifically comprises the following steps:
comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
when the delay value of the master delay is the same as the value of the reference clock frequency, the delay value corresponding to the master delay at the moment is recorded.
The device for reducing the frequency error of the digital clock comprises a first configuration unit, a calibration unit, a query unit, a storage unit, a second configuration unit and a stop unit;
the first configuration unit is used for configuring controller parameters;
the calibration unit is used for entering a calibration mode;
the query unit is used for querying whether calibration is completed;
the storage unit is used for writing the stored delay value of the main delay into the parameter register;
the second configuration unit is used for configuring the parameter register to enter a clock oscillation mode so as to generate an internal clock according to a delay value of the main delay;
and the stopping unit is used for closing the external crystal oscillator clock.
The further technical scheme is as follows: the first configuration unit comprises a configuration module and a gating module;
the configuration module is used for configuring parameters of the front delay so as to generate a front delay internal clock;
the gating module is used for generating a reference clock through internal clock gating.
The further technical scheme is as follows: the calibration unit comprises a comparison module and a recording module;
the comparison module is used for comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
and the recording module is used for recording the delay value corresponding to the master delay when the delay value of the master delay is the same as the value of the reference clock frequency.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps for reducing digital clock frequency error as claimed above when executing the computer program.
A storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method steps for reducing digital clock frequency error as described above.
Compared with the prior art, the invention has the beneficial effects that: the method for reducing the frequency error of the digital clock provided by the invention generates the reference clock through the internal clock gating, then carries out phase locking on the pre-delay internal clock generated by the parameter of the pre-delay according to the reference clock, generates the internal clock according to the delay value of the main delay after the phase locking is finished, and can close the external crystal oscillator clock after the internal clock is obtained, thereby achieving the purposes of reducing the power consumption and reducing the frequency error of the digital clock.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more apparent, the following detailed description will be given of preferred embodiments.
Drawings
FIG. 1 is a first flowchart of a method for reducing digital clock frequency error according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a second embodiment of a method for reducing digital clock frequency error according to the present invention;
FIG. 3 is a flowchart of a third embodiment of a method for reducing digital clock frequency error according to the present invention;
FIG. 4 is a first schematic diagram illustrating a first exemplary embodiment of an apparatus for reducing digital clock frequency error according to the present invention;
FIG. 5 is a second schematic diagram illustrating a second exemplary embodiment of an apparatus for reducing digital clock frequency error according to the present invention;
FIG. 6 is a third schematic structural diagram of an embodiment of an apparatus for reducing digital clock frequency error according to the present invention;
FIG. 7 is a schematic block diagram of one embodiment of a computer device of the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
It is to be understood that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects.
It should be further understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
As shown in fig. 1-3, the present invention provides a method for reducing digital clock frequency error, the method comprising:
s10, configuring controller parameters;
s20, entering a calibration mode;
s30, checking whether the calibration is finished, if so, S40, writing the saved delay value of the main delay into a parameter register, and if not, returning to the step S20;
s50, the configuration parameter register enters a clock oscillation mode to generate an internal clock according to the delay value of the main delay;
and S60, turning off the external crystal oscillator clock.
Specifically, the parameters of the controller are configured through the AHB bus, and whether the calibration is completed through the AHB bus length is determined. After the calibration is completed, the external crystal oscillator clock can be turned off, and the power supply of the external crystal oscillator clock is not needed, so that the power consumption is reduced.
Further, step S10 specifically includes the following steps:
s101, configuring parameters of front delay to generate a front delay internal clock;
and S102, generating a reference clock through internal clock gating.
Further, step S20 specifically includes the following steps:
s201, comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
and S202, when the delay value of the master delay is the same as the value of the reference clock frequency, recording the delay value corresponding to the master delay.
Specifically, when the delay value of the master delay is the same as the value of the reference clock frequency, phase locking is performed, and the delay value of the master delay is not changed.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Corresponding to the method for reducing the frequency error of the digital clock in the embodiment, the invention provides a device for reducing the frequency error of the digital clock. As shown in fig. 4-6, the apparatus includes a first configuration unit 1, a calibration unit 2, a query unit 3, a save unit 4, a second configuration unit 5, and a stop unit 6;
a first configuration unit 1 for configuring controller parameters;
a calibration unit 2 for entering a calibration mode;
the inquiring unit 3 is used for inquiring whether the calibration is completed;
a saving unit 4, configured to write the saved delay value of the master delay into the parameter register;
a second configuration unit 5, configured to configure the parameter register to enter a clock oscillation mode, so as to generate an internal clock according to a delay value of the main delay;
and the stopping unit 6 is used for turning off the external crystal oscillator clock.
Specifically, the parameters of the controller are configured through the AHB bus, and whether the calibration is completed through the AHB bus length is determined. After the calibration is completed, the external crystal oscillator clock can be turned off, and the power supply of the external crystal oscillator clock is not needed, so that the power consumption is reduced.
Further, the first configuration unit 1 includes a configuration module 11 and a gate control module 12;
a configuration module 11, configured to configure parameters of the front delay to generate a front delay internal clock;
a gating module 12 for generating the reference clock by internal clock gating.
Further, the calibration unit 2 includes a comparison module 21 and a recording module 22;
a comparison module 21, configured to compare the internal front delay clock with the reference hour hand, and generate a delay value of the main delay;
and a recording module 22, configured to record a delay value corresponding to the master delay when the delay value of the master delay is the same as the value of the reference clock frequency.
Specifically, when the delay value of the master delay is the same as the value of the reference clock frequency, phase locking is performed, and the delay value of the master delay is not changed.
As shown in fig. 7, the present invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps for reducing digital clock frequency error as described above when executing the computer program.
The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, memory, and a network interface 750, which are connected by a system bus 710, where the memory may include non-volatile storage media 730 and internal memory 740.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer programs 732, when executed, cause the processor 720 to perform any of a variety of methods for reducing digital clock frequency error.
The processor 720 is used to provide computing and control capabilities, supporting the operation of the overall computer device 700.
The internal memory 740 provides an environment for the execution of the computer program 732 in the non-volatile storage medium 730, which computer program 732, when executed by the processor 720, causes the processor 720 to perform any of the methods for reducing digital clock frequency error.
The network interface 750 is used for network communication such as sending assigned tasks and the like. Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing device 700 to which the disclosed aspects apply, as a particular computing device 700 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to perform the following steps:
configuring controller parameters;
entering a calibration mode;
inquiring whether the calibration is completed;
if yes, writing the saved delay value of the main delay into a parameter register;
the configuration parameter register enters a clock oscillation mode to generate an internal clock according to a delay value of the main delay;
and turning off the external crystal oscillator clock.
Further: the step of configuring the controller parameters specifically comprises the following steps:
configuring parameters of a front delay to generate a front delay internal clock;
the reference clock is generated by internal clock gating.
Further: the step of entering the calibration mode specifically comprises the following steps:
comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
when the delay value of the master delay is the same as the value of the reference clock frequency, the delay value corresponding to the master delay at the moment is recorded.
It should be understood that, in the embodiment of the present Application, the Processor 720 may be a Central Processing Unit (CPU), and the Processor 720 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the configuration of computer device 700 depicted in FIG. 7 is not intended to be limiting of computer device 700 and may include more or less components than those shown, or some components in combination, or a different arrangement of components.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present invention may be implemented in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical functional division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The technical contents of the present invention are further illustrated by the examples only for the convenience of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (4)
1. A method for reducing digital clock frequency error, the method comprising:
configuring controller parameters;
entering a calibration mode;
inquiring whether the calibration is completed;
if yes, writing the saved delay value of the main delay into a parameter register;
the configuration parameter register enters a clock oscillation mode to generate an internal clock according to a delay value of the main delay;
turning off an external crystal oscillator clock;
the step of configuring the controller parameters specifically comprises the following steps:
configuring parameters of a front delay to generate a front delay internal clock;
generating a reference clock by internal clock gating;
the step of entering the calibration mode specifically comprises the following steps:
comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
when the delay value of the master delay is the same as the value of the reference clock frequency, the delay value corresponding to the master delay at the moment is recorded.
2. The device for reducing the frequency error of the digital clock is characterized by comprising a first configuration unit, a calibration unit, a query unit, a storage unit, a second configuration unit and a stop unit;
the first configuration unit is used for configuring controller parameters;
the calibration unit is used for entering a calibration mode;
the query unit is used for querying whether calibration is completed;
the storage unit is used for writing the stored delay value of the main delay into the parameter register;
the second configuration unit is used for configuring the parameter register to enter a clock oscillation mode so as to generate an internal clock according to a delay value of the main delay;
the stopping unit is used for closing an external crystal oscillator clock;
the first configuration unit comprises a configuration module and a gating module;
the configuration module is used for configuring parameters of the front delay so as to generate a front delay internal clock;
the gating module is used for generating a reference clock through internal clock gating;
the calibration unit comprises a comparison module and a recording module;
the comparison module is used for comparing the internal clock of the front delay with the reference hour hand to generate a delay value of the main delay;
and the recording module is used for recording the delay value corresponding to the master delay when the delay value of the master delay is the same as the value of the reference clock frequency.
3. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method steps for reducing digital clock frequency error as claimed in claim 1 when executing the computer program.
4. A storage medium, characterized in that the storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to carry out the method steps for reducing digital clock frequency errors as claimed in claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910242873.6A CN110007712B (en) | 2019-03-28 | 2019-03-28 | Method, apparatus, computer device and storage medium for reducing digital clock frequency error |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910242873.6A CN110007712B (en) | 2019-03-28 | 2019-03-28 | Method, apparatus, computer device and storage medium for reducing digital clock frequency error |
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| CN110007712A CN110007712A (en) | 2019-07-12 |
| CN110007712B true CN110007712B (en) | 2020-12-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4071604B2 (en) * | 2002-11-18 | 2008-04-02 | 株式会社ルネサステクノロジ | Information processing apparatus provided with clock generation circuit and information processing apparatus provided with clock delay circuit |
| JP4660076B2 (en) * | 2003-06-23 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | Clock generation circuit |
| KR100558554B1 (en) * | 2004-01-07 | 2006-03-10 | 삼성전자주식회사 | Internal clock generating apparatus |
| US7961026B2 (en) * | 2007-03-31 | 2011-06-14 | Hynix Semiconductor Inc. | Delay cell and phase locked loop using the same |
| KR100905440B1 (en) * | 2008-01-08 | 2009-07-02 | 주식회사 하이닉스반도체 | Clock synchronization circuit and operation method thereof |
| CN106708167B (en) * | 2015-11-13 | 2019-11-29 | 北京兆易创新科技股份有限公司 | A kind of method and controller adjusting clock |
| CN107872221B (en) * | 2016-09-26 | 2021-04-27 | 深圳市中兴微电子技术有限公司 | Full-phase digital delay phase-locked loop device and working method |
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