CN109994066A - For driving and compensating the display device of low delay virtual reality - Google Patents

For driving and compensating the display device of low delay virtual reality Download PDF

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Publication number
CN109994066A
CN109994066A CN201811491747.6A CN201811491747A CN109994066A CN 109994066 A CN109994066 A CN 109994066A CN 201811491747 A CN201811491747 A CN 201811491747A CN 109994066 A CN109994066 A CN 109994066A
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CN
China
Prior art keywords
display device
signal
timing controller
addressing
data
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Pending
Application number
CN201811491747.6A
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Chinese (zh)
Inventor
朴东远
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LG Display Co Ltd
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LG Display Co Ltd
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Publication of CN109994066A publication Critical patent/CN109994066A/en
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)

Abstract

For driving and compensating the display device of low delay virtual reality.This disclosure relates to be used to drive virtual reality with low delay and compensate the display device of the brightness after reducing.According to the disclosure, a kind of display device is provided, and the display device includes: timing controller, which is used to receive data-signal and timing signal from host system；Data drive unit, the data drive unit are used to receive driving signal from the timing controller；Gate driving circuit unit, the gate driving circuit unit are used to receive driving signal from the timing controller；Display panel, the display panel have multiple sub-pixels and show video based on from the data drive unit and the gate driving circuit unit received signal；And power supply unit, the power supply unit are used to power to the data drive unit, the gate driving circuit unit and the display panel；And the timing controller receives addressing reset signal from the host system.

Description

For driving and compensating the display device of low delay virtual reality
Technical field
This disclosure relates to the display device for driving and compensating virtual reality, and more particularly, to for low Delay (latency) drives virtual reality and compensates the display device of the brightness of reduction.
Background technique
Market with Information Technology Development, the display device as the connection medium between user and information is increasingly expanded Greatly.Therefore, to such as Organic Light Emitting Diode (OLED) display device, quantum dot displays (ODD), liquid crystal display (LCD) Use with display device as plasma display panel (PDP) increasingly increases.
Display device is implemented as such as TV, set-top box, navigation, video player, Blu-ray player, individual calculus Small-sized, medium-sized or giant display as machine, wearable device, mobile phone and virtual reality display.
It is immersed in the environment of imitation and render real as former state in addition, virtual reality display device is able to use family.Thus The user of purpose, virtual reality display device wears equipment as such as goggles, headphone, gloves and togs To exchange information, and it is exposed to the virtual environment created by system (for example, computer etc.).
However, the problem is that, user is subjected to so-called virtual reality illness when watching virtual reality display device (VR illness).Virtual reality is in the eyeball that people is closer to than conventional display device, so that vision acceptance of the people to picture It becomes very large.When the movement of people and the inconsistent variation for the picture for corresponding to movement, there is virtual reality illness.It is existing Problem is that virtual reality illness is the main uncomfortable of virtual reality user and limits the use time of virtual reality.
Summary of the invention
The disclosure aims to solve the problem that these problems, and a purpose of the disclosure is to provide for driving low delay virtually existing Real display device.
In addition, the disclosure aims to solve the problem that these problems, and another object of the present disclosure is to provide for low in driving The display device of compensation brightness while the virtual reality that is delayed.
According to the disclosure, a kind of display device is provided, and the display device includes: timing controller, the timing control Device processed is used to receive data-signal and timing signal from host system；Data drive unit, the data drive unit are used for from institute It states timing controller and receives driving signal；Gate driving circuit unit, the gate driving circuit unit are used to receive from the timing controller Driving signal；Display panel, the display panel have multiple sub-pixels and are based on from the data drive unit and the choosing Lead to driving unit received signal to show video；And power supply unit, the power supply unit be used for the data drive unit, The gate driving circuit unit and display panel power supply；Also, the timing controller is received from the host system and is addressed Reset signal.
The timing controller receives the addressing reset signal when moving.
When receiving the addressing reset signal, the timing controller sends gating weight to the gate driving circuit unit Confidence number.
It is poor that addressing resetting bit is assigned to the low-voltage transmitted between the host system and the timing controller Divide any of multiple unrelated bits of signaling (LVDS) transformat unrelated bit.
Referring to the VSYNC ratio for the LVDS transformat that instruction transmits between the host system and the timing controller Special and HSYNC bit combined recovery table receives the addressing reset signal.
In clock built-in interface between the host system and the timing controller, transmission/reception has addressing Reset the illusory grouping and described illusory after the first level blanking grouping of initial data, first level blanking grouping The second horizontal blanking grouping that there is addressing resetting to terminate data after grouping.
The display device adjusts the pulse width of addressing reset signal by adjusting the length of illusory grouping.
The timing controller is sent to the gate driving circuit unit for luminous signal is compensated.
The compensation carried out based on the compensation luminous signal in the display device is controlled by compensation light-emitting period to shine, And the compensation light-emitting period is controlled by the pulse width of the addressing reset signal.
The compensation carried out based on the compensation luminous signal in the display device is controlled by light emission luminance to shine.
The gate driving circuit unit executes the control reduced for showing the light emission luminance for the video data for reflecting movement.
The reduced light emission luminance in display device is calculated, and according to replacement ratio with desired level and intrinsic brilliance Between ratio calculate the replacement ratio.
According to the disclosure, low delay can be realized when driving virtual reality.
In addition, the virtual reality illness (VR illness) of virtual reality user can be removed according to the disclosure.
In addition, can compensate for the reduction of brightness according to the disclosure, because transporting due to gating addressing resetting and in response to user The new frame of dynamic variation configures and the transmitting retention time of former frame is caused to become longer.
Detailed description of the invention
Fig. 1 is schematically to illustrate the block diagram of the display device according to embodiment of the present disclosure.
Fig. 2 is the configuration diagram of the sub-pixel of the display device schematically illustrated in example diagram 1.
Fig. 3 is the figure of a part of exemplary virtual reality display device.
Fig. 4 is the figure for illustrating the definition of the delay in virtual reality display device.
The exemplary figure of delay configuration when Fig. 5 A is for illustrating to move during addressing periods.
The exemplary figure of delay configuration when Fig. 5 B is for illustrating to move during addressing periods.
The exemplary figure of delay configuration when Fig. 5 C is for illustrating to move during addressing periods.
Fig. 6 is the block diagram schematically illustrated for realizing the exemplary display device illustrated referring to Fig. 5 C.
Fig. 7 is to illustrate the figure of the data structure for realizing the exemplary display device illustrated referring to Fig. 5 C.
Fig. 8 is to illustrate the figure of the packet configuration for realizing the exemplary display device illustrated referring to Fig. 5 C.
Fig. 9 A is the figure for illustrating the luminance compensation when realizing that the delay illustrated referring to Fig. 5 C configures.
Fig. 9 B is the figure for illustrating the luminance compensation when realizing that the delay illustrated referring to Fig. 5 C configures.
Fig. 9 C is the figure for illustrating the luminance compensation when realizing that the delay illustrated referring to Fig. 5 C configures.
Specific embodiment
Hereinafter, it will be described with reference to the accompanying drawings embodiment of the present disclosure.
Fig. 1 is schematically to illustrate the block diagram of the display device according to embodiment of the present disclosure.
Fig. 2 is the configuration diagram of the sub-pixel of the display device schematically illustrated in example diagram 1.
It illustrates as shown in figure 1, which includes host system 100, timing controller 170, data drive unit 130, power supply unit 140, gate driving circuit unit 150 and display panel 110.
Host system 100 includes wherein being built-in with the system on chip (SoC) of scaler (scaler), and by input video Digital video data be converted into the data-signal of format for being suitable for showing on display panel 110 and export the data letter Number.Various timing signals are supplied to timing controller 170 by host system 100 together with data-signal.
Timing controller 170 receives video data (Video Data) from host system 100.Timing controller 170 is based on Such as vertical synchronizing signal (V_Sync), the horizontal synchronizing signal (H_Sync), data enable signal inputted from host system 100 (DE) and timing signal as master clock signal (Pixel Clock) is single to control data drive unit 130 and gating driving The operation timing of member 150.
Timing controller 170 handles the data-signal inputted from host system 100 for video, and is supplied to number According to driving unit 130.For example, timing controller 170 compensates the data-signal inputted from host system 100, and supplied To data drive unit 130.
Data drive unit 130 executes operation in response to the signal supplied from timing controller 170.For example, data are driven Moving cell 130 is operated in response to the first driving signal (DDC) for providing from timing controller 170.Data drive unit 130 will The digital data signal (DATA) provided from timing controller 170 is converted into analog data signal and exports analogue data letter Number.
Specifically, data drive unit 130 in response to the gamma unit of internal or external offer gamma electric voltage and will count Digital data signal (DATA) is converted into analog data signal.Data-signal is supplied to display panel 110 by data drive unit 130 Data line (DL1 to DLn).
Gate driving circuit unit 150 executes operation in response to the signal supplied from timing controller 170.For example, gating drives Moving cell 150 is operated in response to the second driving signal (GDC) for providing from timing controller 170.Gate driving circuit unit 150 is defeated It gates high voltage out or gates the gating signal of low-voltage.Gating signal can also be referred to as scanning signal.
Gate driving circuit unit 150 can be sequentially output gating signal in the forward direction, or in backward direction successively Export gating signal.In addition, gate driving circuit unit 150 can export gating signal simultaneously.Gate driving circuit unit 150 believes gating Number it is supplied to the gating line (GL1 to GLm) of display panel 110.
Power supply unit 140 provides for the first voltage source (VCC, GND) of driving data driving unit 130 etc. and for driving The second voltage source (EVDD, EVSS) of dynamic display panel 110.It is driven in addition, power supply unit 140 generates the gating such as to be passed that is sent to Voltage needed for the gating high voltage or the such driving display device of gating low-voltage of unit 150.
Display panel 110 include multiple sub-pixels (SP), connect with sub-pixel (SP) data line (DL1 to DLn) and Gating line (the GL1 to GLm) being connect with sub-pixel (SP).Display panel 110 is in response to the choosing that exports from gate driving circuit unit 150 Messenger and from data drive unit 130 export data-signal and show video.Display panel 110 includes lower substrate and upper base Plate.Sub-pixel (SP) can be plugged between lower substrate and upper substrate.
As illustrated in Fig. 2, a sub-pixel includes connecting (or to be formed in gating line (GL1) and data line (DL1) With the infall of gating line (GL1) and data line (DL1)) switching thin-film transistor (SW) and in response to passing through switch film The data-signal of transistor (SW) supply and the pixel circuit (PC) that operates.
According to the configuration of the pixel circuit (PC) of sub-pixel (SP), display panel 110 may be implemented as LCD display Plate or organic light emitting display panel etc..For example, it is when display panel 110 is implemented as liquid crystal display panel with twisted-nematic (TN) mode, perpendicular alignmnet (VA) mode, in-plane switching (IPS) mode, fringing field switching (FFS) mode or electrically conerolled birefringence (ECB) mode is operated.
As another example, when display panel 110 is implemented as organic light emitting display panel, it is with top-emission mode Or bottom emission mode is operated.
The display panel of above-mentioned display device can be selected from liquid crystal display panel, organic light emitting display panel, electrophoresis showed Panel, plasma display panel etc..It should be appreciated, however, that the present disclosure is not limited to either of which kinds.
It is played in addition, above-mentioned display device may be implemented as such as TV, set-top box, navigation, video player, blue light It is small-sized as device, personal computer, wearable device, home theater, mobile phone and virtual reality (VR) display device, in Type or giant display.When based on the display device with organic light emitting display panel to realize virtual reality, following displays Device has the advantages that bigger, and this will be described as example.It should be appreciated, however, that the present disclosure is not limited in them It is any.
In addition, it can pass through rolling shutter mode and global shutter mode in the display panel for realizing virtual reality In any realize.When being realized under global shutter mode, following display devices have the advantages that it is bigger, and this will It is described as example.It should be appreciated, however, that the present disclosure is not limited to either of which kinds.
Fig. 3 is the figure of a part of exemplary virtual reality display device.
As illustrated in Fig. 3, virtual reality display device includes for showing that the left eye of video is shown on left eye direction Driving unit (180L, 150L, LAA) and for showing video on right eye direction right eye display driver element (180R, 150R、RAA)。
Left eye display driver element (180L, 150L, LAA) and right eye display driver element (180R, 150R, RAA) include Panel driving unit (180L, 180R), gate driving circuit unit (150L, 150R) and display unit (LAA and RAA).
Panel driving unit (180L, 180R) controls gate driving circuit unit (150L, 150R), and data-signal is supplied To display unit (LAA, RAA).Panel driving unit (180L, 180R) is 170 He of timing controller being wherein integrated in Fig. 1 The integrated circuit (IC) of data drive unit 130.Panel driving unit (180L, 180R) can also include the power supply list in Fig. 1 Member 140.
In addition, Fig. 3 instantiate for showing video on left eye display direction left eye display driver element (180L, 150L, LAA) and right eye display driver element (180R, 150R, RAA) for showing video on right eye display direction separate Example, it should be appreciated that, this is only an example and the present disclosure is not limited thereto.
Virtual reality display device as described above is able to use family and is immersed in the environment of imitation and render real as former state. For this purpose, user wear such as goggles, headphone, gloves and togs as equipment to exchange information, And it is exposed to the virtual environment created by system (for example, computer etc.).
Hereinafter, it in order to improve the virtual reality illness occurred in virtual reality display device (VR illness), will describe For the display device of virtual reality to be driven and compensated with low delay.
Fig. 4 is the figure for illustrating the definition of the delay in virtual reality display device.
Referring to Fig. 4, the delay in virtual reality display device be defined as from the time of moving to generating the first light Period at the time of sub-.Specifically, movement is directed to the change for the video that user shows.For example, working as the use of experiencing virtual reality When family rotates his/her head, this means that the visual field changes.Since display should show that omnidirectional regards in physics constrained environment Figure, therefore display device should show the visual field after changing according to the change in the visual field on panel.It shows on the display apparatus Picture means that organic illuminating element emits light in organic light-emitting display device, that is to say, that generates the first photon.Therefore, empty Delay in quasi- reality display device is defined as from being used to show the fortune after reflecting change to generating at the time of moving Period at the time of first photon of dynamic video.When delay becomes longer, user will be subjected to virtual reality illness (VR disease Disease).That is, visual field after change is delayed by and is shown on the desplay apparatus and continuously although the visual field changes When ground postpones, user feels inconvenient.As another example, even if user does not take movement, in shown video It can also happen that changing.For example, the case where being changed in video due to particular event is also included in movement.
In addition, the addressing periods (Addressing) illustrated in Fig. 4 mean host system 100 in response to occur movement and to Timing controller 170 provides signal (V_Sync, H_Sync, data enable signal, the master for showing the video corresponding to movement Clock signal etc.) and timing controller 170 to data drive unit and gate driving circuit unit provide driving signal (DATA, DDC, GDC etc.) period.In addition, illustrated in Fig. 4 shine (Emission) period mean organic illuminating element transmitting light when Section.It it should be appreciated, however, that the present disclosure is not limited to these meanings, and can also include the equivalent period.
As a result, delay in virtual reality display device be defined as from the time of moving to generating the first photon The period at moment.That is, delay most preferably addressing periods (T_addr).
The exemplary figure of delay configuration when Fig. 5 A is for illustrating to move during addressing periods.
Referring to Fig. 5 A, three frame periods (T_frame1, T_frame2, T_frame3), and each frame period are instantiated Including addressing periods and light-emitting period.That is, the frame period 1 (T_frame1) includes addressing periods 1 (T_addr1) and shines Period 1 (T_emit1), frame period 2 (T_frame2) include addressing periods 2 (T_addr2) and light-emitting period 2 (T_emit2), frame Period 3 (T_frame3) includes addressing periods 3 (T_addr3) and light-emitting period 3 (T_emit3).
For example, in the display device operated under with 20% global shutter mode of 120Hz, the frame period (T_frame) can be with It is 8.33ms, addressing periods (T_addr) can be 6.66ms, and light-emitting period (T_emit) can be 1.67ms.
It is assumed that being moved during addressing periods 2 (T_addr2).In such a case, it is possible in 3 (T_ of light-emitting period Emit3 carried out in) for show reflect movement video shine.Such as previous definition, in virtual reality display device Delay is defined as the first photon from video at the time of moving to generation for showing the movement after reflecting change At the time of period.Therefore, the delay in Fig. 5 A is T_extra+T_frame.That is, delay in this case is T_extra+T_emit2+T_addr3。
As described above, most preferably, delay is addressing periods (T_addr).In the example referring to Fig. 5 A, with addressing Period, (T_addr) was compared, and delay has further increased T_extra+T_emit.That is, user is from his/her angle Degree, which is seen, has been carried out movement, but will watch the video for reflecting movement more lately than ideal situation.Therefore, user is subjected to Virtual reality illness (VR illness) is inevitable.
The exemplary figure of delay configuration when Fig. 5 B is for illustrating to move during addressing periods.
Referring to Fig. 5 B, four frame periods (T_frame1, T_frame2, T_frame3, T_frame4) are instantiated, and every A frame period includes addressing periods and light-emitting period.That is, the frame period 1 (T_frame1) includes 1 (T_ of addressing periods Addr1) and light-emitting period 1 (T_emit1), frame period 2 (T_frame2) include addressing periods 2 (T_addr2) and light-emitting period (T_emit2), the frame period 3 (T_frame3) includes addressing periods 3 (T_addr3) and light-emitting period 3 (T_emit3), and frame Period 4 (T_frame4) includes addressing periods 4 (T_addr4) and light-emitting period 4 (T_emit4).
For example, in the display device operated under with 20% global shutter mode of 120Hz, the frame period (T_frame) can be with It is 8.33ms, addressing periods (T_addr) can be 6.66ms, and light-emitting period (T_emit) can be 1.67ms.
It is assumed that being moved during addressing periods 2 (T_addr2).In this case, SoC (is included in host system In 100) two data are handled in an addressing periods.That is, the place in an addressing periods (T_addr2,3) SoC The video data got a haircut before giving birth to movement and the video data for reflecting movement.That is, movement occurs for mixed merging treatment Preceding video data and the video data for reflecting movement.The display device of data is received in a light-emitting period (T_ from SoC Emit2,3) it is generated in for show two video datas (that is, video data before moving and the view for reflecting movement Frequency evidence) photon.Such as previous definition, the delay in virtual reality display device be defined as from the time of moving to Generate period at the time of the first photon for showing the video for reflecting movement.Therefore, the delay in Fig. 5 B than it is ideal when Section (T_addr) is short.
As described above, most preferably, delay is addressing periods (T_addr).In the example referring to Fig. 5 B, with addressing Period, (T_addr) was compared, and delay is further reduced.That is, movement has been carried out in user from the point of view of him/her, and And the video for reflecting movement can be watched immediately.Therefore, the virtual reality illness (VR illness) that user is subjected to can be by most Smallization.However, shining (T_emit2) for the video before moving due to being performed simultaneously as illustrated in Fig. 5 B With shining (T_emit3) for the video for reflecting movement, therefore finally mixed video will be shown simultaneously to user.
The exemplary figure of delay configuration when Fig. 5 C is for illustrating to move during addressing periods.
Referring to Fig. 5 C, four frame periods (T_frame1, T_frame2, T_frame3, T_frame4) are instantiated, and every A frame period includes addressing periods and light-emitting period.That is, the frame period 1 (T_frame1) includes 1 (T_ of addressing periods Addr1) and light-emitting period 1 (T_emit1), frame period 2 (T_frame2) include addressing periods 2 (T_addr2) and light-emitting period (T_emit2), the frame period 3 (T_frame3) includes addressing periods 3 (T_addr3) and light-emitting period 3 (T_emit3), and frame Period 4 (T_frame4) includes addressing periods 4 (T_addr4) and light-emitting period 4 (T_emit4).
For example, in the display device operated under with 20% global shutter mode of 120Hz, the frame period (T_frame) can be with It is 8.33ms, addressing periods (T_addr) can be 6.66ms, and light-emitting period (T_emit) can be 1.67ms.
It is moved during addressing periods 2 (T_addr2).In this case, SoC (is included in host system 100 In) generate addressing reset signal (Addressing Reset).In addition, SoC processing reflects the video data of movement.Work as display When device receives addressing reset signal (Addressing Reset), display device starts the new frame period (T_frame3). That is, display device addresses the video data for reflecting movement within the T_addr3 period, and within the T_emit3 period Generate the photon for showing the video data for reflecting movement.Delay such as previous definition, in virtual reality display device It is defined as from period at the time of being used to show the first photon of the video for reflecting movement to generation at the time of moving. Therefore, the delay in Fig. 5 C is identical as ideal period (T_addr).
As described above, most preferably, delay is addressing periods (T_addr).In the example referring to Fig. 5 C, be delayed energy Enough become identical as addressing periods (T_addr).That is, movement has been carried out in user from the point of view of him/her, and It can be watched at the optimal moment and reflect the video of movement.Therefore, the virtual reality illness (VR illness) that user is subjected to It can be minimized.
Fig. 6 is the block diagram schematically illustrated for realizing the exemplary display device referring to Fig. 5 C description.
As illustrated in Fig. 6, which includes host system 100, timing controller 170, data drive unit 130, power supply unit 140, gate driving circuit unit 150 and display panel 110.
Host system 100 includes wherein being built-in with the system on chip (SoC) of scaler, and by the digital number of input video According to the data-signal being converted into suitable for the format shown on display panel 110 and export the data-signal.Host system 100 will Various timing signals are supplied to timing controller 170 together with data-signal.
In addition, host system 100 provides addressing reset signal (Addressing Reset) to timing controller 170.Tool Body, when moving, addressing reset signal (Addressing is provided from host system 100 to timing controller 170 Reset)。
Timing controller 170 receives video data (Video Data) from host system 100.In addition, timing controller 170 It is enabled based on such as vertical synchronizing signal (V_Sync), horizontal synchronizing signal (H_Sync), data inputted from host system 100 Timing signal as signal (DE) and master clock signal (Pixel Clock) drives to control data drive unit 130 and gating The operation timing of moving cell 150.
Timing controller 170 handles the data-signal inputted from host system 100 for video, and is supplied to number According to driving unit 130.For example, timing controller 170 compensates the data-signal inputted from host system 100, and supplied To data drive unit 130.
In addition, timing controller 170 receives addressing reset signal (Addressing Reset) from host system 100.Tool Body, when moving, addressing reset signal (Addressing is provided from host system 100 to timing controller 170 Reset)。
When timing controller 170 receives addressing reset signal (Addressing Reset) from host system 100, timing Controller 170 provides gating reset signal (Gate Reset) to gate driving circuit unit 150.At this point it is possible to be driven according to gating The type of unit and operation reset to be configured differently gating.For example, can be by the way that gate-in-panel type gating will be repeatedly input The GCLK signal of driving unit is maintained at digital low or digital height to reset gate driving circuit unit.
Data drive unit 130 executes operation in response to the signal supplied from timing controller 170.For example, data are driven Moving cell 130 is operated in response to the first driving signal (DDC) for providing from timing controller 170.Data drive unit 130 will The digital data signal (DATA) provided from timing controller 170 is converted into analog data signal and exports analogue data letter Number.
Specifically, data drive unit 130 in response to the gamma unit of internal or external offer gamma electric voltage and will count Digital data signal (DATA) is converted into analog data signal.Data-signal is supplied to display panel 110 by data drive unit 130 Data line (DL1 to DLn).
Gate driving circuit unit 150 executes operation in response to the signal supplied from timing controller 170.For example, gating drives Moving cell 150 is operated in response to the second driving signal (GDC) for providing from timing controller 170.Gate driving circuit unit 150 is defeated It gates high voltage out or gates the gating signal of low-voltage.Gating signal can also be referred to as scanning signal.
Gate driving circuit unit 150 is sequentially output gating signal in the forward direction, or is sequentially output in backward direction Gating signal.In addition, gate driving circuit unit 150 can export gating signal simultaneously.Gate driving circuit unit 150 proposes gating signal Supply the gating line (GL1 to GLm) of display panel 110.
When gate driving circuit unit 150 receives gating reset signal (Gate Reset) from timing controller 170, gating The resetting gating driving processing of driving unit 150.As a result, display device addressing reflects the video data (T_ in Fig. 5 C of movement Addr3), and the photon (T_emit3 in Fig. 5 C) for being used for showing the video for reflecting movement is generated.As a result, it is possible to will prolong When (from the time of moving to for showing period at the time of the first photon for reflecting the video of movement) remain T_ Addr, this is the ideal period.Therefore, movement has been carried out in user from the point of view of him/her, and can be optimal Moment watches the video for reflecting movement.Therefore, the virtual reality illness (VR illness) that user is subjected to can be minimized.
Power supply unit 140 provides for the first voltage source (VCC, GND) of driving data driving unit 130 etc. and for driving The second voltage source (EVDD, EVSS) of dynamic display panel 110.It is driven in addition, power supply unit 140 generates the gating such as to be passed that is sent to Voltage needed for the gating high voltage or the such driving display device of gating low-voltage of unit 150.
Display panel 110 include multiple sub-pixels (SP), connect with sub-pixel (SP) data line (DL1 to DLn) and Gating line (the GL1 to GLm) being connect with sub-pixel (SP).Display panel 110 is in response to the choosing that exports from gate driving circuit unit 150 Messenger and from data drive unit 130 export data-signal and show video.Display panel 110 includes lower substrate and upper base Plate.Sub-pixel (SP) can be plugged between lower substrate and upper substrate.
Fig. 7 is to illustrate the figure of the data structure for realizing the exemplary display device referring to Fig. 5 C description.
Specifically, Fig. 7 is for illustrating host system 100 and timing controller 170 via low voltage difference signaling (LVDS) figure for the case where communicating with one another.
Referring to Fig. 7, LVDS transformat 710 and LVDS recovery table 720 are instantiated.
LVDS transformat 710 is transmitted between host system 100 and timing controller 170.
LVDS transformat 710 includes multiple bits.For example, R0 is intended to indicate that the bit of red video to R7 bit, G0 is intended to indicate that the bit of green video, B0 are intended to indicate that the bit of blue video to B7 bit to G7 bit.VSYNC ratio Spy 712 is the bit for being used to indicate vertical synchronizing signal (Vertical Sync), and HSYNC bit 713 is to be used to indicate level together Walk the bit of signal (Horizontal Sync).
According to the disclosure, any of uninterested bit (so-called unrelated bit) is assigned to be used to indicate and is sought The bit 711 of location reset signal (Addressing Reset).That is, when indicating high (H) in addressing resetting bit 711 When, the timing controller 170 for receiving corresponding LVDS transformat 710 receives the order for executing addressing resetting.It is reset when in addressing When indicating low (L) in bit 711, the reception of timing controller 170 for receiving corresponding LVDS transformat 710 does not execute addressing resetting Order.
According to the disclosure, VSYNC bit 712, HSYNC bit 713 and recovery table 720 can use.For example, when in LVDS VSYNC bit 712 is low and HSYNC bit 713 when being high in transformat 710, receives corresponding LVDS transformat 710 Timing controller 170 receives HSYNC synch command referring to table 720 721 is restored.For example, in LVDS transformat 710 When VSYNC bit 712 is height and HSYNC bit 713 is low, the timing controller 170 of corresponding LVDS transformat 710 is received HSYNC synch command is received referring to table 720 722 is restored.For example, working as the VSYNC bit 712 in LVDS transformat 710 is height And when HSYNC bit 713 is high, the timing controller 170 of corresponding LVDS transformat 710 is received referring to recovery table 720 723 receive the order for executing addressing resetting.For example, working as the VSYNC bit 712 in LVDS transformat 710 is low and HSYNC When bit 713 is low, the timing controller 170 for receiving corresponding LVDS transformat 710 is not held referring to the reception of recovery table 720 724 The order of any operation of row.
Fig. 8 is to illustrate the figure of the packet configuration for realizing the exemplary display device referring to Fig. 5 C description.
Specifically, Fig. 8 is for illustrating that host system 100 and timing controller 170 lead to each other via clock built-in interface The figure of the case where letter.
Referring to Fig. 8, the multiple groupings sent and received between host system 100 and timing controller 170 are instantiated.Example Such as, the multiple grouping includes video data packets 811 and horizontal blanking grouping 812.
Level when being moved during transmitting video data grouping 821, after corresponding video data packets 821 Blanking grouping 822 includes the data (ARESET_START) that instruction addressing resetting starts.Hereafter, illusory (Dummy) grouping is sent 823, then horizontal blanking grouping 824 includes the data (ARESET_STOP) that instruction addressing resetting terminates.At this point it is possible to adjust The length of illusory grouping 823, to control the time for executing addressing resetting.
That is, using include addressing resetting start data (ARESET_START) first level blanking grouping 822, The illusory grouping 823 and sent and received after illusory grouping 823 that first level blanking grouping 822 sends and receives later Include that addressing resetting terminates the second horizontal blanking grouping 824 of data (ARESET_STOP) to indicate addressing resetting, and can The period for executing addressing resetting is controlled to use illusory grouping 823.
Fig. 9 A is the figure for illustrating the luminance compensation when realizing the delay configuration referring to Fig. 5 C description.
For ease of description, by 120 [Hz] the 20% global shutter modes that describe.It should be appreciated, however, that the disclosure is only For ease of description, and it is without being limited thereto.In 120 [Hz] 20% global shutter modes, addressing periods (T_addr) are 6.66ms, Light-emitting period (T_emit) is 1.67ms, and the frame period (T_frame) is 8.33ms.
Description is needed into the reason of carrying out luminance compensation first.
Referring to Fig. 9 A, section 1 (ideal) is instantiated.Section 1 (ideal) is not sent out in the second addressing periods (T_addr2) The ordinary circumstance of raw movement.Since shining to the second light-emitting period (T_emit2) in the first light-emitting period (T_emit1) Period be T_emit1+T_addr2=8.33ms.That is, it is identical as frame period (T_frame).Due to shine when Section (T_emit1) is 1.67ms, therefore the brightness that user visually receives is considered as the flat of (light-emitting period)/(frame period) Equal brightness.That is, (1.67ms/8.33ms)=0.2, so that receiving 20% brightness.For example, when in light-emitting period (T_ When having transmitted the light that brightness is 100nit in emit1), the brightness that user recognizes during section 1 (ideal) is 20nit, i.e., 20%.
Referring to Fig. 9 B, section 2 (reality) is instantiated.Section 2 (reality) is occurred in the second addressing periods (T_addr2) The case where movement.Herein, it is assumed that T_extra 3.33ms.The luminous period (T_emit1) is 1.67ms, is occurred second Period before shining is T_emit1+T_extra+T_addr3=11.66ms.Therefore, because what user visually received Brightness is (1.67ms)/(11.66ms)=0.143, therefore receives 14.3% brightness.For example, when in light-emitting period (T_ When having transmitted the light that brightness is 100nit in emit1), the brightness that user recognizes during section 2 (reality) is 14.3nit, i.e., 14.3%.
That is, configuring according to the delay referring to Fig. 5 C, the reduction for the brightness that user recognizes occurs, so that proposing Luminance compensation is carried out to reduced brightness.
Fig. 9 B is the figure for illustrating the luminance compensation when realizing the delay configuration referring to Fig. 5 C description.
In the present embodiment, propose that the compensation generated for carrying out luminance compensation to reduced brightness shines (Compensation Emit)。
Specifically, it is preferred that after moving and reflect movement frame (T_frame3) before between occur It compensates and shines (Compensation Emit).In the description referring to Fig. 9 A, reduced brightness is 5.7%.It is able to carry out control System is shone with the reduction amount by brightness to execute compensation.Specifically, compensation hair can be executed by control compensation light-emitting period Light.For example, the reduction amount with brightness becomes much larger, it is able to carry out and controls so that compensation light-emitting period is longer.As a reality Mode is applied, compensation light-emitting period can be controlled by addressing the pulse width 910 of reset signal.As another embodiment party Formula can be shone by the luminous brightness of control compensation to execute compensation.For example, the reduction amount with brightness becomes much larger, energy Enough it is controlled such that the luminous brightness of compensation is bigger.
Compensation, which shines, can be referred to as short global transmitting or global compensation transmitting.
Since above-mentioned compensation shines, the virtual reality illness (VR illness) that user is subjected to can be reduced.That is, working as When application compensation does not shine, due to movement, the luminance deviation that will lead to every frame is big, and user will be subjected to visual flicker.So And it can be shone by above-mentioned compensation to reduce luminance deviation.
Fig. 9 C is the figure for illustrating the luminance compensation when realizing the delay configuration referring to Fig. 5 C description.
In the present embodiment, propose to reduce the luminous quantity for showing the video data for reflecting movement so as to reduction Brightness carry out luminance compensation.
Specifically, in the embodiment referring to Fig. 9 A, desired level (L_ideal) is 20%, but intrinsic brilliance (L_ Actual) it is 14.3%, reduces 5.7%.In this case, when in the case where not compensating execute for showing When reflecting luminous (T_emit3) of the video data of movement, due to the change of visually big brightness, user will be subjected to dizzy Light.Therefore, present embodiment proposes to reduce the luminous quantity (T_emit3) for showing the video data for reflecting movement.
Specifically, for showing that the slip for reflecting the luminous quantity (T_emit3) of the video data of movement can be as follows.
Replacement ratio=(L_actual)/(L_ideal)
That is, in the embodiment referring to Fig. 9 A, (L_actual)/(L_ideal)=(0.143)/(0.2)= 0.715.Therefore, for showing that the luminous quantity (T_emit3) for reflecting the video data of movement can reduce 71.5%.For example, When being directed at the light of T_emit3 transmitting 200nit, can be controlled to emit in the embodiment as 71.5% The light of 143nit.As another example, it when being directed at the light of T_emit3 transmitting 300nit, can be controlled according to this The light of embodiment transmitting 214.5nit.
Due to the reduction of above-mentioned luminous quantity, the virtual reality illness (VR illness) that user is subjected to can be reduced.That is, When not having to shine using compensation, due to movement, the luminance deviation that will lead to every frame is big, and user will be subjected to visual flicker. However, causing luminance deviation that can reduce since above-mentioned luminous quantity is reduced.
As described above, although having been combined embodiment illustrated in figure describes the disclosure, neck belonging to the disclosure Domain it is to be understood by the skilled artisans that other specific shapes can be formed in the case where not changing its technical spirit or essential characteristic Formula.It should therefore be understood that above embodiment be all in all respects it is illustrative, and not restrictive.
Cross reference to related applications
This application claims the preferential of the South Korea patent application No.10-2017-0183566 submitted on December 29th, 2017 Power, the disclosure of the South Korea patent application are completely incorporated herein by reference.

Claims (13)

1. a kind of display device, the display device include:
Timing controller, the timing controller are used to receive data-signal and timing signal from host system；
Data drive unit, the data drive unit are used to receive driving signal from the timing controller；
Gate driving circuit unit, the gate driving circuit unit are used to receive driving signal from the timing controller；
Display panel, the display panel have multiple sub-pixels and are based on driving from the data drive unit and the gating Unit received signal shows video；And
Power supply unit, the power supply unit are used for the data drive unit, the gate driving circuit unit and the display panel Power supply,
Wherein, the timing controller receives addressing reset signal from the host system.
2. display device according to claim 1, wherein the timing controller receives the addressing when moving Reset signal.
3. display device according to claim 1, wherein when receiving the addressing reset signal, the timing control Device processed sends gating reset signal to the gate driving circuit unit.
4. display device according to claim 1, wherein addressing resetting bit is assigned in the host system and institute It is unrelated to state any of multiple unrelated bits of low voltage difference signaling LVDS transformat transmitted between timing controller Bit.
5. display device according to claim 1, wherein referring to instruction in the host system and the timing controller Between the combined recovery table of the VSYNC bit of LVDS transformat and HSYNC bit that transmits receive the addressing resetting Signal.
6. display device according to claim 1, wherein between the host system and the timing controller when In clock built-in interface, transmission/reception has first level blanking grouping, the first level blanking of addressing resetting initial data The second horizontal blanking point that there is addressing resetting to terminate data after illusory grouping and the illusory grouping after grouping Group.
7. display device according to claim 6, wherein adjust described seek by adjusting the length of the illusory grouping The pulse width of location reset signal.
8. display device according to claim 1, wherein the timing controller will compensate luminous signal be sent to it is described Gate driving circuit unit.
9. display device according to claim 8, wherein controlled by compensation light-emitting period and shone based on the compensation The compensation that signal carries out shines, and controls the compensation light-emitting period by the pulse width of the addressing reset signal.
10. display device according to claim 8, wherein control to shine based on the compensation by light emission luminance and believe Number carry out compensation shine.
11. display device according to claim 1, wherein the gate driving circuit unit, which executes, to be reduced for showing reflection The control of the light emission luminance of the video data of movement.
12. display device according to claim 11,
Wherein, reduced light emission luminance is calculated according to replacement ratio, and
Wherein, the replacement ratio is calculated with the ratio between desired level and intrinsic brilliance.
13. display device according to claim 1, wherein the display device is driven under global shutter mode.
CN201811491747.6A 2017-12-29 2018-12-07 For driving and compensating the display device of low delay virtual reality Pending CN109994066A (en)

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