CN109979833A - A kind of quick room temperature micro convex point bonding method based on nested structure and annealing - Google Patents
A kind of quick room temperature micro convex point bonding method based on nested structure and annealing Download PDFInfo
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- CN109979833A CN109979833A CN201910177846.5A CN201910177846A CN109979833A CN 109979833 A CN109979833 A CN 109979833A CN 201910177846 A CN201910177846 A CN 201910177846A CN 109979833 A CN109979833 A CN 109979833A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/8182—Diffusion bonding
- H01L2224/81825—Solid-liquid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
Abstract
The invention belongs to technical field of semiconductors, specially a kind of quick room temperature micro convex point bonding method based on nested structure and annealing.The method of the present invention includes: to form nested structure: being respectively formed nested structure in the front and back of wafer, nested structure includes the first protrusion and recessed portion, and recessed portion includes sunk structure and the second protrusion around the sunk structure；The nested structure of two wafers: being aligned by bonding on bonder, so that the first protrusion of wherein wafer is mutually aligned and is bonded with the sunk structure of another wafer, repeatedly completes the bonding of multilayer wafer；First protrusion and sunk structure constitute solid-liquid and spread metal pair；Annealing: annealing to the multilayer wafer for completing bonding, so that the refractory metal of solid-liquid diffusion metal centering and low-melting-point metal thawing is diffuseed to form intermetallic compound and realizes electrical connection.This method is simple and effective, can save the production time, improves production efficiency；And it can effectively avoid damage to device.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to the micro convex point bonding method between a kind of chip and chip.
Background technique
As integrated circuit integrated level improves, feature sizes of semiconductor devices is up to physics limit.To further increase
Performance and integrated level, researcher start to integrate chip on three-dimensional.The wherein dimpling between chip and chip
Point bonding techniques are the key that realization is three-dimensionally integrated.It mostly uses at present based on solid-liquids diffusion principles such as solder reflux, CuSn/AuSn
Micro convex point bonding, bonding curve include cooling/heating-up time, need higher peak temperature and certain pressure, and key
Solder/Sn is excessive uncontrollable during conjunction, therefore micro convex point bonding techniques temperature is higher, bonding time is longer, salient point pitch and
Reliability is all restricted.Also, the time needed for the bonding of multilayer chiop is directly proportional to the number of chip, this makes multiple key
Peak temperature is larger to component influences on chip in conjunction, and multilayer chiop bonding time is very long, efficiency is very low.
Summary of the invention
The purpose of the present invention is to provide a kind of quick, room temperature micro convex point bonding methods.
Quick room temperature micro convex point bonding method provided by the invention is based on based on nested structure and annealing technology, tool
Body step are as follows:
(1) it forms nested structure: being respectively formed nested structure, the nested structure, both ends difference in the front and back of wafer
It is formed with the first protrusion and recessed portion, the recessed portion includes sunk structure and the second protrusion around the sunk structure, institute
The height for stating the second protrusion is greater than the height of the sunk structure, and the first protrusion and the second protrusion are using high in the nested structure
The sunk structure of melting metal material, the recessed portion uses low-melting-point metal；
(2) it is bonded: being directed at the nested structures of two wafers on bonder, make the wherein nested structure of wafer
First protrusion is mutually aligned and is bonded with the sunk structure of the nested structure of another wafer, repeatedly completes more
The bonding of layer crystal circle；Wherein, first protrusion and the sunk structure constitute solid-liquid diffusion metal pair；
(3) it anneals: the multilayer wafer for completing bonding is made annealing treatment, make the Gao Rong of the solid-liquid diffusion metal centering
Point metal and low-melting-point metal thawing diffuse to form intermetallic compound and realize electrical connection.
In the present invention, preferably annealing temperature is set between 150 DEG C -250 DEG C according to the fusing point of the low melting point metal material.
In the present invention, the preferably described annealing time is 5min ~ 25min.
In the present invention, the preferably described refractory metal is one of Cu, Au, Ni or any combination thereof.
In the present invention, the preferably described low-melting-point metal is one of Sn, In, Ga or any combination thereof.
In the present invention, the preferably described nested structure forming step specifically includes following sub-step: alignment is formed on wafer
Marker graphic；Form adhesion layer and seed layer；Using standard photolithography process, the basal layer of wiring pattern out and nested structure is exposed
Figure plates out high melting point metal materials, basis of formation layer with plating or chemical plating；Using standard photolithography process, on the basis
Layer exposes the first raised position of nested structure out and the second raised position of recessed portion, and refractory metal is electroplated, and forms first
Second protrusion of protrusion and recessed portion；Low-melting-point metal is electroplated in second protrusion and forms the sunk structure, then does
Method etches adhesion layer and seed layer；Interim bonding protection existing graphics is carried out to the front of wafer, reversion wafer is in its back side weight
Multiple above-mentioned steps, complete the production of the nested structure at the back side, then the interim bonding of removal.
In the present invention, the preferably described nested structure forming step specifically includes following sub-step: alignment is formed on wafer
Marker graphic；Form adhesion layer and seed layer；Using standard photolithography process, the basal layer of wiring pattern out and nested structure is exposed
Figure plates out high melting point metal materials, basis of formation layer with plating or chemical plating；Using standard photolithography process, on the basis
The sunk structure for exposing the recessed portion of nested structure out of layer is electroplated low-melting-point metal, forms the sunk structure of recessed portion；Using
Standard photolithography process exposes the first raised position of nested structure out and the second raised position of recessed portion on the basal layer
It sets, interim bonding protection existing graphics is carried out to the front of wafer, reversion wafer repeats the above steps at its back side, completes the back side
Nested structure production, the then interim bonding of removal.
In the present invention, the preferably described adhesive layer material is TiW, Ti or Cr.
In the present invention, the preferably described adhesion layer with a thickness of 20-50 nanometers, the seed layer is received with a thickness of 50-100
Rice, the basal layer with a thickness of 2-3 microns.
In the present invention, the height of the preferably described sunk structure is 1-3 microns, and the height of second protrusion is 4-6 microns.
The present invention is by the mechanical connection in bonding process and is electrically connected process and separates, using nested structure carry out wafer/
The mechanical connection of chip utilizes being electrically connected for the last bonded interface for realizing multilayer chiop of annealing.By repeatedly mechanical
Connection procedure realizes that chip stacks, and primary annealing, which is realized, to be electrically connected, to greatly shorten thermal diffusion time-consuming in repeatedly bonding
Time, repeatedly bonding is identical as a bonding time.This method is simple and effective, can save the production time, improves production efficiency.
In addition, since bonding temperature reduces, so as to effectively avoid device caused by being bonded because of multiple high temp from damaging.
Detailed description of the invention
Fig. 1 is the flow chart of the quick normal temperature bonding method of the invention based on nested structure and annealing.
Fig. 2 is the device architecture schematic diagram after forming seed layer.
Fig. 3 is the device architecture schematic diagram after the basic layer pattern to form nested structure.
Fig. 4 is the device architecture schematic diagram to be formed after the first protrusion and recessed portion.
Fig. 5 is the device architecture schematic diagram after forming nested structure.
Fig. 6 is the device architecture schematic diagram completed after nested structure alignment and bonding.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with drawings and examples
The invention will be further described.It should be appreciated that described herein, specific examples are only used to explain the present invention, is not used to
Limit the present invention.Described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, all other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the orientation of the instructions such as term " on ", "lower", " vertical " "horizontal"
Or positional relationship is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present invention and simplification of the description, and
It is not that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore
It is not considered as limiting the invention.In addition, term " first ", " second " are used for description purposes only, and should not be understood as referring to
Show or imply relative importance.
In addition, many specific details of the invention, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can be with
The present invention is not realized according to these specific details.Unless hereinafter particularly point out, the various pieces in device can be by
Material well known to those skilled in the art is constituted, or can be using the material with similar functions of exploitation in the future.
As shown in Figure 1, the quick normal temperature bonding method of the invention based on nested structure and annealing the following steps are included:
Firstly, being respectively formed nested structure in the front and back of wafer 100 in nested structure forming step S1.Nested structure
Both ends be respectively formed with first protrusion and recessed portion, recessed portion include sunk structure and around sunk structure second protrusion,
The height of second protrusion is greater than the height of sunk structure.The first protrusion and the second protrusion use refractory metal material in nested structure
The sunk structure of material, recessed portion uses low-melting-point metal.
For more specifically, alignment mark figure is formed on wafer 100.Select thermally grown 300nm thick silicon oxide
101 silicon wafer 100 is used as substrate material, uses normalized optical photoetching process on it, exposes marker graphic out, use physical vapor
The metallic gold of about 50 nano thickness is deposited on its surface in (PVD) method of deposit, one layer about 5 nanometers of the insertion between gold and substrate
Titanium obtains the figure 102 of alignment mark as adhesive layer material so as to the use of subsequent alignment after removing photoresist.
Next, forming adhesion layer 103 and seed layer 104.Use sputtering method deposition about 20nm thickness metal TiW as glue
As seed layer 104, resulting structures are as shown in Figure 2 by attached layer 103 and the Cu of 50nm thickness.In addition, adhesion layer can also use
In the integrated circuit technologies such as Ti, Cr frequently with adhesion layer metal.
Later, using standard photolithography process, the basic layer pattern of wiring pattern out and nested structure, plating or chemistry are exposed
High melting point metal materials, such as Cu are plated out, thickness is preferably 3 microns, and 105 resulting structures of basis of formation layer are as shown in Figure 3.
Then, using standard photolithography process, the first raised position and recessed portion of nested structure out are exposed in basal layer 105
The second raised position, 4 microns thick of refractory metal Cu of plating forms the first protrusion 106 and the second protrusion 107.It is being recessed
Low-melting-point metal such as Sn is electroplated in second protrusion in portion, forms sunk structure 108.Thickness less than the second protrusion 107 height, it is excellent
It is selected as 1 micron.Then dry etching adhesion layer and seed layer, resulting structures are as shown in Figure 4.
The front of wafer is temporarily bonded, existing graphics is protected, reversion wafer 100 repeats above-mentioned step at its back side
Suddenly, the production of the nested structure at the back side is completed, then the interim bonding of removal, resulting structures are as shown in Figure 5.
In one embodiment of the invention, the process of above-mentioned formation the first protrusion and the second protrusion, can also pass through
Following steps are realized.Firstly, exposing the recess position of the recessed portion of nested structure out in basal layer 105 using standard photolithography process
It sets, plating low-melting-point metal such as Sn forms sunk structure 108.Then, it using standard photolithography process, is exposed on basal layer embedding out
Refractory metal Cu is electroplated in first raised position of nested structure and the second raised position of recessed portion, forms the first raised 106 Hes
Second protrusion 107.
In addition, refractory metal of the invention can also be one of higher melting-point metal such as Cu, Au, Ni or its
Meaning combination.Low-melting-point metal can be one of lower melting-point metal such as Sn, In, Ga or any combination thereof.
Secondly, the nested structure of two wafers is aligned on bonder, makes wherein wafer in bonding steps S2
The first protrusion of nested structure 106 be mutually aligned and be bonded with the sunk structure 108 of the nested structure of another wafer, repeatedly
Repeatedly complete the bonding of multilayer wafer, wherein the first protrusion 106 and sunk structure 108 constitute solid-liquid and spread metal pair.
Finally, being made annealing treatment to the multilayer wafer for completing bonding, annealing temperature is according to eutectic in annealing steps S3
The fusing point of point metal material is set between 150 DEG C -250 DEG C, and annealing time is preferably 5min ~ 25min, and solid-liquid is made to spread metal pair
In refractory metal and low-melting-point metal thawing diffuse to form intermetallic compound realize electrical connection, resulting structures such as Fig. 6 institute
Show.Certainly, the present invention is not limited thereto, and the fusing point of low melting point metal material can also be lower, and annealing time can also be longer.
The method for realizing quick normal temperature bonding based on nested structure and annealing of the invention is suitable for wafer scale bonding, chip
To wafer bonding, chip to chip bonding, bonding chip type is unlimited.Substrate is not limited, ultra-thin chip, sensor core
Connection can be achieved in piece, high-power die etc., can be greatly promoted three-dimensionally integrated realization.
The present invention is by the mechanical connection in bonding process and is electrically connected process and separates, using nested structure carry out wafer/
The mechanical connection of chip utilizes being electrically connected for the last bonded interface for realizing multilayer chiop of annealing.By repeatedly mechanical
Connection procedure realizes that chip stacks, and primary annealing, which is realized, to be electrically connected, to greatly shorten thermal diffusion time-consuming in repeatedly bonding
Time, repeatedly bonding is identical as a bonding time.This method is simple and effective, can save the production time, improves production efficiency,
In addition, since bonding temperature reduces, so as to effectively avoid device caused by being bonded because of multiple high temp from damaging.
More than, for the specific embodiment party of the method for the invention for realizing quick normal temperature bonding based on nested structure and annealing
Formula is described in detail, but the present invention is not limited thereto.The specific embodiment of each step according to circumstances can be different.This
Outside, the sequence of part steps can exchange, and part steps can be omitted.For example, nesting can be formed only on a wafer
First protrusion of structure, only forms the recessed portion of nested structure on another wafer.Or be also possible that a face of wafer only
The first protrusion for forming nested structure, only forms the recessed portion of nested structure in another face of wafer.As long as in short, more
In the stacking process of a wafer or multiple chips, the first protrusion of the wherein nested structure of wafer and another can be made
The sunk structure of the nested structure of wafer is mutually aligned and is bonded.
Claims (10)
1. a kind of quick room temperature micro convex point bonding method based on nested structure and annealing, which is characterized in that specific steps are as follows:
(1) it forms nested structure: being respectively formed nested structure, the nested structure, both ends difference in the front and back of wafer
It is formed with the first protrusion and recessed portion, the recessed portion includes sunk structure and the second protrusion around the sunk structure, institute
The height for stating the second protrusion is greater than the height of the sunk structure, and the first protrusion and the second protrusion are using high in the nested structure
The sunk structure of melting metal material, the recessed portion uses low-melting-point metal；
(2) it is bonded: being directed at the nested structures of two wafers on bonder, make the wherein nested structure of wafer
First protrusion is mutually aligned and is bonded with the sunk structure of the nested structure of another wafer, repeatedly completes more
The bonding of layer crystal circle；Wherein, first protrusion and the sunk structure constitute solid-liquid diffusion metal pair；
(3) it anneals: the multilayer wafer for completing bonding is made annealing treatment, make the Gao Rong of the solid-liquid diffusion metal centering
Point metal and low-melting-point metal thawing diffuse to form intermetallic compound and realize electrical connection.
2. bonding method according to claim 1, which is characterized in that the annealing temperature is according to the low-melting-point metal material
The fusing point of material is set between 150 DEG C -250 DEG C.
3. bonding method according to claim 1 or 2, which is characterized in that annealing time is 5min ~ 25min.
4. bonding method according to claim 1, which is characterized in that the refractory metal is one of Cu, Au, Ni
Or any combination thereof.
5. bonding method according to claim 1, which is characterized in that the low-melting-point metal is one of Sn, In, Ga
Or any combination thereof.
6. bonding method according to claim 1, which is characterized in that the nested structure forming step includes following sub-step
It is rapid:
Alignment mark figure is formed on wafer；
Form adhesion layer and seed layer；
Using standard photolithography process, the basic layer pattern of wiring pattern out and nested structure is exposed, is plated out with plating or chemical plating
High melting point metal materials, basis of formation layer；
Using standard photolithography process, the basal layer expose nested structure out the first raised position and recessed portion it is second convex
Position is played, refractory metal is electroplated, forms the second protrusion of the first protrusion and recessed portion；
Low-melting-point metal is electroplated in second protrusion and forms the sunk structure, then dry etching adhesion layer and seed
Layer；
Interim bonding protection existing graphics is carried out to the front of wafer, reversion wafer repeats the above steps at its back side, completes back
The production of the nested structure in face, the then interim bonding of removal.
7. bonding method according to claim 1, which is characterized in that the nested structure forming step includes following sub-step
It is rapid:
Alignment mark figure is formed on wafer；
Form adhesion layer and seed layer；
Using standard photolithography process, the basic layer pattern of wiring pattern out and nested structure is exposed, is plated out with plating or chemical plating
High melting point metal materials, basis of formation layer；
Eutectic is electroplated in the sunk structure for exposing the recessed portion of nested structure out of the basal layer using standard photolithography process
Point metal, forms the sunk structure of recessed portion；
Using standard photolithography process, exposed on the basal layer nested structure out the first raised position and recessed portion second
Raised position, plating refractory metal form the first protrusion and the second protrusion；
Interim bonding protection existing graphics is carried out to the front of wafer, reversion wafer repeats the above steps at its back side, completes back
The production of the nested structure in face, the then interim bonding of removal.
8. bonding method according to claim 6 or 7, which is characterized in that the adhesive layer material is TiW, Ti or Cr.
9. temperature bonding method according to claim 6 or 7, which is characterized in that the adhesion layer is received with a thickness of 20-50
Rice, the seed layer with a thickness of 50-100 nanometers, the basal layer with a thickness of 2-3 microns.
10. bonding method according to claim 1, which is characterized in that the height of the sunk structure is 1-3 microns, institute
The height for stating the second protrusion is 4-6 microns.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022011622A1 (en) * | 2020-07-16 | 2022-01-20 | Yangtze Memory Technologies Co., Ltd. | Methods for bonding semiconductor structures and semiconductor devices thereof |
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