CN109976670B - Design method of serial nonvolatile memory controller supporting data protection function - Google Patents
Design method of serial nonvolatile memory controller supporting data protection function Download PDFInfo
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- CN109976670B CN109976670B CN201910201147.XA CN201910201147A CN109976670B CN 109976670 B CN109976670 B CN 109976670B CN 201910201147 A CN201910201147 A CN 201910201147A CN 109976670 B CN109976670 B CN 109976670B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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Abstract
The invention relates to the field of serial nonvolatile memory controllers, in particular to a serial nonvolatile memory controller design method supporting a data protection function, which comprises the following steps: 1) Generating a chip unique ID based on the test of an SoC chip integrated with a storage controller and storing the chip unique ID in an EFUSE; 2) Generating a random number determined by the chip based on the generated unique ID; 3) Dividing a transmission FIFO of a universal serial nonvolatile memory controller into an address command FIFO and a data special FIFO; 4) And performing XOR logic processing on the generated random number and the split FIFO input to finish the writing processing of actual data, and performing XOR logic processing on the output of the receiving FIFO by using the same random number to obtain actual effective data. The invention ensures the uniqueness of the random number through the uniqueness of the chip ID, thereby realizing the data protection of the chip to external serial nonvolatile storage.
Description
Technical Field
The invention relates to the field of serial nonvolatile memory controllers, in particular to a serial nonvolatile memory controller design method supporting a data protection function.
Background
In order to match the application scheme of the chip terminal in the SoC chip design in the digital control field and the consumer wireless communication field, it is necessary to provide a scalable development support based on the nonvolatile storage. Application programs and user data for a particular product solution may be stored in the non-volatile storage.
At present, the non-volatile storage of a miniaturized SoC chip is mainly realized by the following two schemes: 1. non-volatile storage (eflash) is integrated during chip design, and chips (Die) produced by a wafer factory comprise the non-volatile storage; 2. the chip is interconnected with the external nonvolatile storage through the chip integrated storage controller, so that the requirement of the nonvolatile storage in the scheme is met. Considering the cost factors of production, testing and solution development, solution "2" is often used in consumer electronics solutions. Meanwhile, the external nonvolatile memory is mainly controlled by serial access.
The integration of the serial nonvolatile memory and the SoC chip can be realized based on PCB on-board interconnection, and can also be interconnected in an SIP mode when the SoC chip is packaged. However, after the application schemes of the specific products of the two are released, the data in the nonvolatile storage can be acquired in a parsing manner based on the specific products. For an application program, the method is an implementation mechanism of a replication scheme; for the data stored therein, leakage of the user data is obtained.
Copying of the application program can cause imitation of the product, thereby causing loss of early research and development efforts and defects of actual product sale; the leakage of user data can cause doubts of end users on product quality, so that the product competitiveness is reduced. Generally, the positioning and market expectation of the initial product are affected, and thus, the capital and manpower loss is caused.
Therefore, in view of the above situation, there is an urgent need to develop a serial nonvolatile memory controller design method supporting a data protection function to overcome the shortcomings in the current practical application.
Disclosure of Invention
The present invention is directed to a serial nonvolatile memory controller design method supporting data protection function, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
the design method of the serial nonvolatile memory controller supporting the data protection function comprises the following steps:
1) Generating a chip unique ID based on the test of an SoC chip integrated with a storage controller and storing the chip unique ID in an EFUSE;
2) Generating a random number determined by the chip based on the unique ID generated in the step 1);
3) Dividing a transmission FIFO of a universal serial nonvolatile memory controller into an address command FIFO and a data special FIFO;
4) And (3) carrying out XOR logic processing on the random number generated in the step 2) and the split FIFO input in the step 3) to finish the write-in processing of actual data, and simultaneously carrying out XOR logic processing on the output of the receiving FIFO by using the same random number to obtain actual effective data to finish the protection and recovery of the data.
As a further scheme of the invention: in the step 1): the chip unique ID is generated by CP/FT testing and stored in EFUSE.
As a further scheme of the invention: in the step 1): in the CP test, specific Wafer ID and Die are generated on specific coordinates of the whole Wafer.
As a further scheme of the invention: in the step 2): a random number generator is used to generate a 32bits random number.
As a further scheme of the invention: in the step 3): and the time-sharing reading of the sending serial shift register is realized based on read-write control logic.
The design method of the serial nonvolatile memory controller supporting the data protection function is applied to the field of digital control.
The design method of the serial nonvolatile memory controller supporting the data protection function is applied to the field of consumer wireless communication.
Compared with the prior art, the invention has the beneficial effects that:
the method comprises the steps of firstly realizing the generation of the unique ID of each chip in the design and test processes of the SoC chip, and then generating the random number which is uniquely determined for each chip by taking the chip ID as a seed through a random number generator. The invention realizes the protection of data in nonvolatile storage by splitting the transmission FIFO into the address command FIFO and the data FIFO and carrying out simple XOR logic on the data of the data FIFO and the generated random number. The uniqueness of the chip ID guarantees the uniqueness of the random number, so that the data protection of the chip for external serial nonvolatile storage is realized.
Drawings
Fig. 1 is a schematic structural diagram of an interconnection principle of an SoC chip and a serial nonvolatile memory according to the present invention.
FIG. 2 is a schematic diagram of a serial nonvolatile memory controller according to the present invention.
Detailed Description
The technical solution of the present patent will be described in further detail with reference to the following embodiments.
Reference will now be made in detail to embodiments of the present patent, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present patent and are not to be construed as limiting the present patent.
Example 1
Referring to fig. 1-2, in an embodiment of the present invention, a method for designing a serial nonvolatile memory controller supporting a data protection function includes the following steps:
1) Based on CP/FT test integrated with a storage controller SoC chip, generating a chip unique ID according to corresponding deterministic information in the CP/FT test and storing the chip unique ID in an EFUSE;
2) Generating a random number of 32bits using a pseudo random number generator based on the unique ID generated in the step 1);
3) The method comprises the steps of splitting a transmission FIFO of a universal serial nonvolatile memory controller into an address command FIFO and a data special FIFO, and simultaneously realizing time-sharing reading of a transmission serial shift register by using a read-write control logic;
4) And performing XOR logic processing on the random number generated in the step 2) and the split FIFO input in the step 3) to complete the writing processing of the actual data, and performing XOR logic processing on the output of the receiving FIFO by using the same random number to obtain the actual effective data. The uniqueness of the chip ID guarantees the uniqueness of the random number, so that the data protection of the chip for external serial nonvolatile storage is realized.
Example 2
Referring to fig. 1-2, the present embodiment is different from embodiment 1 in that:
in this embodiment, in step 1): the ID of the chip can be generated by the specific reference ID and the specific coordinates of Die on the whole Wafer in the CP test.
In this embodiment, in step 1): the eFuse is realized in the chip design.
In this embodiment, in step 2): the pseudo-random number generator is a software implementation.
In this embodiment, in step 3): the split of the transmission FIFO is mainly random number XOR logic, so that the processing of address and storage command words is avoided.
In this embodiment, in step 4): the software driven access FIFO is the address that needs to distinguish between the Transmit Address Command FIFO and the Transmit data FIFO.
The method comprises the steps of firstly realizing the generation of the unique ID of each chip in the design and test processes of the SoC chip, and then generating the uniquely determined random number for each chip by taking the chip ID as a seed through a random number generator. The writing and reading of the external memory by the serial memory controller are realized by the parallel access of the CPU and the control of the shift register. Generally, the transmission and the buffering of the parallel data are realized by two FIFOs (transmission and reception), thereby improving the access efficiency of the system. The invention realizes the protection of data in nonvolatile storage by splitting the transmission FIFO into the address command FIFO and the data FIFO and carrying out simple XOR logic on the data of the data FIFO and the generated random number.
The above are only preferred embodiments of the present invention, and it should be noted that, for those skilled in the art, it can make several changes and modifications without departing from the concept of the present invention, and these should also be considered as the protection scope of the present invention, which will not affect the effect of the implementation of the present invention and the practicability of the patent.
Claims (3)
1. The design method of the serial nonvolatile memory controller supporting the data protection function is characterized by comprising the following steps:
1) Generating a chip unique ID based on the test of an SoC chip integrated with a storage controller and storing the chip unique ID in an EFUSE;
2) Generating a random number determined by the chip based on the unique ID generated in the step 1);
3) Dividing a transmission FIFO of a universal serial nonvolatile memory controller into an address command FIFO and a data special FIFO;
4) Carrying out XOR logic processing on the random number generated in the step 2) and the split FIFO input in the step 3) to finish the writing processing of actual data, and simultaneously carrying out XOR logic processing on the output of the receiving FIFO by using the same random number to obtain actual effective data;
wherein, in the step 1): generating a unique ID of the chip through CP/FT test and storing the unique ID in the EFUSE;
in the step 1): in CP test, specific reference ID and Die are generated on the whole reference;
in the step 2): generating a 32bits random number using a pseudorandom number generator;
in the step 3): and the time-sharing reading of the sending serial shift register is realized based on read-write control logic.
2. The application of the serial nonvolatile memory controller design method supporting data protection function in digital control field as claimed in claim 1.
3. The use of the serial non-volatile memory controller design method supporting data protection functions as claimed in claim 1 in the field of consumer wireless communications.
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| CN103020535B (en) * | 2012-12-06 | 2016-05-04 | 苏州国芯科技有限公司 | A kind of data encrypting and deciphering system with comparing function |
| CN104412327B (en) * | 2013-01-02 | 2019-02-12 | 默思股份有限公司 | Built-in self-test and prosthetic device and method |
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