WO2010047575A2

WO2010047575A2 - Autocorrelation circuit for random number generator

Info

Publication number: WO2010047575A2
Application number: PCT/MY2009/000172
Authority: WO
Inventors: Binti M. Thamrin Norashikin; Witjakson Gunawan
Original assignee: Mimos Berhad
Priority date: 2008-10-20
Filing date: 2009-10-20
Publication date: 2010-04-29
Also published as: MY146159A; WO2010047575A3

Abstract

A system (10) for eliminating autocorrelation bits in random number comprising a random number generator for generating a series of random bits (15), a shift register (11) having a predetermined bit length for serially receiving the randomly varying bits (15) and produce a parallel output, a counter (13) having its maximum value determined by the shift register (11) and clocked by a clocking signal, CLK which is same with the shift register (11) to count the shifted bits, and an eliminator module (12) which is activated by the counter (13) when the shifted bits have reached the maximum value, wherein the eliminator module (12) will then identify the contiguous zero and one bits and discard the unwanted bits to produce an uncorrelated random number (16).

Description

Autocorrelation Circuit for Random Number Generator

Field of Invention

The present invention relates generally to the field of random number generator and more particularly to a system and method for eliminating autocorrelation in random numbers.

Background of the Invention

Random numbers are essential in various fields, such as scientific computation fields, games, mathematical statistics, data protection, technological processes, communication security for example it is used to generate keys for encrypting data transmitted over a transmission line to avoid unauthorized tapping of the transmission line. Random number generators (RNG) are divided into two basic types. RNGs that base their output on a physical source of randomness which generate numbers from a non-deterministic source, are known as True Random Number Generators (TRNGs) . RNGs that are given an initial random seed and thereafter generate random-seeming numbers in a deterministic way are known as Pseudo Random Number Generators (PRNGs) .

The drawback of the random number generator is that it is difficult to obtain a sequence of true random numbers. This is because, the numbers generated at the output of a random number generator are either biased or autocorrelated. In the situation where the numbers are biased, it is meant that there is greater than a fifty per cent chance that each bit will be only one of the two binary values.

An autocorrelation is a phenomenon where signals tend to be periodic, cyclical or there is a predictable relationship between parts of the same signal. In random number generator, especially when a hardware random number generator is used, the occurrence of autocorrelation can cause the random signal to have a periodic pattern in certain time, by producing a contiguous bit l's and O's and this is extremely intolerable. If this happen, the random bits is predicted and the security of the generated number can be compromised. Furthermore, the presence of autocorrelation can significantly contribute to the failure of available and standard statistical tests in testing the randomness of the generated random bits. Figure 1 shows an example of bad random sequence that contains the repetitive pattern caused by autocorrelation.

The present invention has overcome the drawbacks of the existing methods by providing a hardware random number generator, a shift register, eliminator module, counter and a controller module to provide the uncorrelated random number. An objective of the present invention is to provide a circuit that can reduce or eliminate autocorrelation problem in a random binary strings produced by a true random number generator.

Yet another objective of the present invention is to provide a random number generator that is simple in design and inexpensive to manufacture.

These and other advantages will become apparent to those skilled in this art upon reading the following detailed description in conjunction with the accompanying drawings.

Summary of the Invention

In the present invention, a system for eliminating autocorrelation bits in random number comprising a random number generator for generating a series of random bits, a shift register having a predetermined bit length, coupled to the random number generator for serially receiving the randomly varying bits and produce a parallel output, a counter connected to the shift register, the counter having its maximum value determined by the shift register- and clocked by a clocking signal, CLK which is same with the shift register to count the shifted bits;, and an eliminator module which is activated by the counter when the shifted bits have reached the maximum value, wherein the eliminator module will then identify the contiguous zero and one bits and discard the unwanted bits.

In accordance to the invention, the eliminator module includes an identifier unit and a removal unit. The identifier unit comprises a plurality of AND gates with a predefined N integer of average number of contiguous bits of zero and one.

In accordance to the invention, the system further comprising a control unit which controls all the signals flow in the system.

A method for eliminating autocorrelation bits in random number generated by a random number generator, the method comprising the steps of generating a series of random bits, shifting the random bits and producing a parallel output, counting the shifted bits to determine whether the bits have reached its maximum value, and eliminating autocorrelation in the random bits by identifying the contiguous zero and one bits and discarding the excessive bits.

Brief Description of the Drawings

Other objects, features, and advantages of the invention will be apparent from the following description when read with reference to the accompanying drawings. In the drawings, wherein like reference numerals denote corresponding parts throughout the several views:

Fig. 1 shows a block diagram illustrating the configuration of a system for eliminating autocorrelation effect in random numbers of the present invention; and

Fig. 2 is a flowchart of the control unit of the system.

Detailed Description of the Preferred Embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known methods, procedures and/or components have not been described in detail so as not to obscure the invention. Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Fig. 1 is a block diagram illustrating the configuration of a system (10) capable of eliminating autocorrelation effect in random strings produced by a random number generator (RNG) according to an exemplary embodiment of the present invention. The random number generator system (10) incorporates a shift register (11), an eliminator module (12), a counter (13) and a control unit (14) . The random number generator (RNG) is operable to output a series of random numbers. Random number means any sequence of binary signals, a Gaussian or any other distribution of signals, a sequence of signals representing a number between zero and one, a sequence of signals representing a decimal number, or any other form that includes the desired randomness.

A string of serial input (15) generated from the random number generator unit (not shown) is input to the system (10) to produce an iuncorrelated random number (16) . This serial input (15) is fed into the shift register (11) for serially receiving the randomly varying bits and produce a parallel output for easier elimination process later. The eliminator module (12) is divided into two units namely an identifier unit (12a) which consists of chain of AND gates (12a) and a removal unit (12b) as shown in Fig. 1. The serial input (15) passes through an n-bit shift register (11) which determines the number of AND gates (12a) going to be used later.

The counter (13) is connected to the shift register (11) . When the n-bit shift register (11) receives the input (15) from the random number generator, the n-bit counter (13) is activated. The shift register (11) is clocked by a clocking signal, CLK and the CLK for the shift register (11) is the same CLK for the counter (13) . The counter (13) increases the counting steps whenever it detects the rising edge of the CLK as the data is shifted in the shift register (11) . This counter (13) is used to count the number of inputs received by the shift register (11) and if the maximum value is achieved, it starts the eliminator module (12) to eliminate autocorrelation in the random number .

The control unit (14) operates as the main control processing unit in the system (10) . The control unit (14) receives counter value from the counter (13) and invokes the ^Λstart' signal to start the elimination process. There are three stages of registers in the control unit (14), which are first register, REGl (Start) (17), second register, REG2 (Wait) (18) and third register, REG3 (Execute) (19) . Whenever the system (10) is powered up or idles, the current state is always at first register, REGl (17) as shown in Fig. 2. Once the system (10) starts, the state moves to second register, REG2 (18) where it receives counter value from the counter (13) . If the value reaches its maximum value which means that the shift register (11) is full and the elimination process can be started. Third register, REG3 (19) will then invokes ^Λstart' signal to the eliminator module (12) . The identifier unit (12a) of the eliminator module (12) comprises a plurality of AND gates (21) to identify the contiguous bits l's and O's before discard them through the removal unit (12b) . The number of AND gates, (R) can be determined by dividing the total n-bits in the shift register (11) with N number of bits' 1 and O's to be eliminated by means of equation (1) below:

R = n DIV N (1)

For a better implementation, the remainder from the division should be 0. If the total number of AND gates (21), R is known, the AND gates (21) are cascaded. The P value (20) as shown in Fig. 2 is the number of desired N number of contiguous bits l's and O's to be discarded. It is hard-coded in a storage means (22) which is a buffer and can be called by multiple of AND gates (21) . The X₁, X₂, X₃ ... X_R is a part of the n-bits of shifted input. It can be determined as:

Where ,

Nl = N

N2 ⁼ Nl + N

N3 ⁼ Nl + 2N

NR = Ni + ( R- I ) N

The results of AND process is stored in buffers (22) for further process. The produce bits in these buffers (22) are in N size for each, Zi, Z₂, Z₃ .... Z_R.

In the removal unit (12b), it discards any Zi value that contains all l's and concatenates the accepted sequence. The condition of removal unit (12b) is as below: -

For i = 0 to R

If Zi = "111..I_N" or Zi = "000..O_N" then

Null; Else Y = Y I I Zi;

Next i

This system (10) is necessary in producing a string of random bits that is not correlated to itself after certain of time. As a result, the produced random number can be made more random and autocorrelation defect can be removed. As will be readily apparent to those skilled in the art, the present invention may easily be produced in other specific forms without departing from its essential characteristics. The present embodiments is, therefore, to be considered as merely illustrative and not restrictive, the scope of the invention being indicated by the claims rather than the foregoing description, and all changes which come within therefore intended to be embraced therein.

Claims

1. A system (10) for eliminating autocorrelation bits in random number comprising: a random number generator for generating a series of random bits (15); a shift register (11) having a predetermined bit length, coupled to said random number generator for serially receiving said randomly varying bits (15) and produce a parallel output; a counter (13) connected to said shift register (11), said counter (13) having its maximum value determined by said shift register (11) and clocked by a clocking signal, CLK which is same with said shift register (11) to count the shifted bits; and an eliminator module (12) which is activated by said counter

(13) when said shifted bits have reached said maximum value, wherein said eliminator module (12) will then identify the contiguous zero and one bits and discard the unwanted bits to produce an uncorrelated random number (16) .

2. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 1, wherein said eliminator module (12) includes an identifier unit (12a) and a removal unit (12b).

3. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 2, wherein said identifier unit (12a) comprises a plurality of AND gates (21) with a predefined N integer of average number of contiguous bits of zero and one.

4. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 3, wherein said N integer is the number of contiguous bits of zero and one to be eliminated and gathered from the results of AND gates (21) process.

5. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 4, wherein said contiguous bits of zero and one to be eliminated is stored in storage means (22) .

6. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 5, wherein said storage means (22) is buffer.

7. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 5, wherein said unwanted contiguous bits stored in storage means is removed by said removal unit (12b) .

8. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 1, wherein said system (10) further comprising a control unit (14) which controls all the signals flow in said system (10) .

9. The system (10) for eliminating autocorrelation bits in random number as claimed in claim 8, wherein said control unit (14) comprising: a first register REGl (17) as initial stage of operation; a second register REG2 (18) connected to said first register (17) and said counter (13) to receive signals flow from said first register (17) when said system (10) starts and to receive counter value from said counter (13); and a third register REG3 (19) connected to said second register (18) and eliminator module (12) to receive invoke signal from said second register (18) when said maximum value of said counter (13) is reached and to activate said eliminator module (12) .

10. A method for eliminating autocorrelation bits in random number generated by a random number generator, the method comprising the steps of: generating a series of random bits; shifting said random bits and producing a parallel output; counting the shifted bits to determine whether said bits have reached its maximum value; and eliminating autocorrelation in said random bits by identifying the contiguous zero and one bits and discarding the excessive bits.

11. The method for eliminating autocorrelation bits in random number as claimed in claim 10, wherein said method further comprising the step of invoking for eliminating process by a control unit (14) from said step of counting.