CN109952709B

CN109952709B - Method and device for channel coding in base station and user equipment

Info

Publication number: CN109952709B
Application number: CN201780069398.6A
Authority: CN
Inventors: 张晓博
Original assignee: Shanghai Langbo Communication Technology Co Ltd
Current assignee: Shanghai Langbo Communication Technology Co Ltd
Priority date: 2017-02-12
Filing date: 2017-02-12
Publication date: 2023-07-21
Anticipated expiration: 2037-02-12
Also published as: CN116723542A; WO2018145306A1; CN109952709A

Abstract

The invention discloses a method and a device for channel coding in a base station and user equipment. The base station sequentially performs first channel coding and transmits a first wireless signal. Wherein a first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The output of the channel code is used to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in a first bit packet are used to generate the first sub-block of bits. The first bit packet is related to the number of bits in the second bit sub-block or the first bit packet is related to the number of bits in the first bit block. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits. The invention can lighten the blind detection burden of the user equipment or support more flexible information transmission formats.

Description

Method and device for channel coding in base station and user equipment

Technical Field

The present invention relates to a transmission scheme of a wireless signal in a wireless communication system, and more particularly, to a method and apparatus for transmission of channel codes.

Background

Polar Codes (Polar Codes) are a coding scheme first proposed by the university of turkish Bi Erken, erdal Arikan, in 2008, which can implement a code construction method for symmetric binary input discrete memoryless channels (B-DMC, binary input Discrete Memoryless Channel). At the 3GPP (3 rd Generation Partner Project, third generation partnership project) RAN1#87 conference, the 3GPP has determined a control channel coding scheme employing a Polar code scheme as a 5GeMBB (enhanced mobile broadband) scenario.

Different DCI (Downlink Control Information ) formats in a conventional LTE (Long Term Evolution ) system correspond to different numbers of coded bits, and a UE (User Equipment) performs blind detection on a PDCCH (Physical Downlink Control Channel) carrying DCI according to all possible DCI formats corresponding to a current transmission mode. The receiving method of the PDCCH can cause the increase of blind detection times at the UE side when the bit number candidates corresponding to the DCI are increased.

Disclosure of Invention

The inventor found through research that the length of the input bit block corresponding to the polar code generator is the power of 2 to the power of N, and N is a positive integer, so for a certain number of information bits, the length of the input bit block corresponding to the polar code-based channel encoder is fixed with the polar code used, and the difference is only that the number of frozen bits is different. This characteristic of the polarization code may be used to compose bits corresponding to the indication information of the number of DCI bits, frozen bits into a fixed-length bit block into an input bit block for generating the polarization code. The receiving end firstly decodes to obtain indication information of the quantity of the DCI bits by utilizing the characteristics of the polar code serial decoder, then determines the exact quantity of the frozen bits in the input bit block by the indication information, and then uses the exact quantity of the frozen bits for subsequent decoding to obtain the DCI bits, thereby reducing the blind detection times and the processing burden of the UE. The indication information needs to be guaranteed to have higher transmission reliability as key information of the decoding of the DCI bits which are decoded first. Therefore, an error check code or an error correction code may be used to first encode the indication information, and the output of the first encoding is used as a bit corresponding to the indication information in the input bit block, thereby ensuring the transmission reliability of the indication information.

The present invention provides a solution to the above problems. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be arbitrarily combined with each other. For example, embodiments in a first node and features in embodiments of the present application may be applied to a second node and vice versa.

The invention discloses a method used in a base station of channel coding, which comprises the following steps:

-step a. Performing a first channel coding;

-step b. Transmitting the first wireless signal.

Wherein a first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The output of the first channel code is used to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in a first bit packet are used to generate the first sub-block of bits. The first bit packet is related to the number of bits in the second bit sub-block or the first bit packet is related to the number of bits in the first bit block. The first bit packet includes a positive integer number of bits in the first bit sub-block and the second bit sub-block, respectively. The number of bits in the second sub-block of bits is one of the K candidate values. The candidate value is a positive integer, and K is a positive integer greater than 1. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

As an embodiment, the above method has the advantage that different numbers of information bits use the same channel coding, so that blind detection times and time-frequency occupied resources of the UE side are reduced. The bits in the first sub-block of bits may be used to determine other information than the first sub-block of bits or to ensure the reliability of the transmission of the first sub-block of bits.

As one embodiment, the first wireless signal is a multicarrier symbol.

As an embodiment, the first wireless signal is an OFDM (Orthogonal Frequency Division Multiplexing ) symbol.

As an embodiment, the first wireless signal is a DFT-S-OFDM (Discrete Fourier Transform Spread OFDM, discrete fourier transform orthogonal frequency division multiplexing) symbol.

As one embodiment, the output of the first channel code is modulated to generate the first wireless signal.

As one embodiment, the output of the first channel code is subjected to multi-antenna precoding to generate the first wireless signal.

As an embodiment, the first bit block is used as an input for the first channel coding.

As an embodiment, each segment of the first bit block is segmented as an input to the first channel coding.

As an embodiment, the first bit block corresponds to a portion of bits of the first channel encoded input.

As an embodiment, the first bit block comprises only all information bits in the first channel encoded input.

As an embodiment, the first bit block includes only a part of information bits in the first channel coding input and check bits corresponding to the part of information bits.

As an embodiment, the first bit block corresponds to all bits of the first channel encoded input.

As an embodiment, the first bit packet explicitly indicates the number of bits in the second bit sub-block.

As an embodiment, the first bit packet implicitly indicates the number of bits in the second bit sub-block.

As an embodiment, an index of the candidate value among the K candidate values is used to determine the first bit packet.

As an embodiment, the value of the first sub-block of bits is independent of the bits in the second sub-block of bits.

As an embodiment, the position of the bits in the first bit sub-block in the first bit block is determined by default.

As an embodiment, the default determination means that no downlink signaling configuration is required.

As an embodiment, the default determination refers to a configuration that does not require explicit downlink signaling.

As an embodiment, the default determination is fixed.

As an embodiment, the default determination means that: for a given number of bits of the first bit sub-block, the position of the first bit sub-block in the first bit block is fixed.

As an embodiment, the default determination means that: for a given number of bits of the first bit block, the position of the first bit sub-block in the first bit block is fixed.

As an embodiment, the default determination means that: for the first bit block of a given time-frequency resource, the position of the first bit sub-block in the first bit block is fixed.

As an embodiment, the positions of the bits in the first sub-block of bits in the first block of bits are discontinuous.

As an embodiment, the positions of the bits in the first sub-block of bits in the first block of bits are consecutive.

As an embodiment, the positions of the bits in the second sub-block of bits in the first block of bits are discontinuous.

As an embodiment, the positions of the bits in the second sub-block of bits in the first block of bits are consecutive.

As an embodiment, the first bit sub-block is at the forefront of the first bit block. The first bit and the second bit are any two bits in the first bit block, and the first bit is before the second bit: in the decoding order of the base station hypothesis receiver, the first bit is decoded before the second bit.

As an embodiment, the number of bits in the first sub-block of bits is a fixed constant.

As an embodiment, the number of bits in the first sub-block of bits is configurable.

As an embodiment, the K candidate values respectively correspond to K DCI (Downlink Control Information ) formats (formats).

As an embodiment, the base station assumes that the probability of the receiver erroneously decoding the first sub-block of bits based on a first assumption that the number of bits in the second sub-block of bits is equal to the maximum of the K candidate values is not higher than a first threshold.

As one embodiment, the receiver of the first wireless signal calculates a first coding rate based on the receiver and informs the base station of the first coding rate, and the base station performs the first channel coding on the first bit block based on the first coding rate. The encoding rate corresponding to the first bit block being less than or equal to the first encoding rate is one of conditions that the probability of error coding the first bit sub-block is not higher than the first threshold on the premise of the first assumption.

As one embodiment, a receiver of the first wireless Signal calculates a first SNR (Signal-to-Noise Ratio) based on the receiver, and notifies the first SNR to the base station, which sets a transmission power of the first wireless Signal based on the first SNR. The SNR corresponding to the first wireless signal being greater than or equal to the first SNR is one of conditions that a probability of error coding the first bit sub-block is not higher than the first threshold on the premise of the first hypothesis.

As one embodiment, the receiver of the first wireless signal calculates a first modulation scheme based on the receiver, and notifies the base station of the first modulation scheme, and the base station sets the modulation scheme of the first wireless signal based on the first modulation scheme. The modulation scheme corresponding to the first wireless signal having higher reliability than the first modulation scheme is one of conditions that the probability of error decoding the first bit sub-block is not higher than the first threshold on the premise of the first hypothesis.

As an embodiment, at least one of the first radio signal modulation scheme and the first radio signal transmission power is a code rate corresponding to the first bit block, and the assumed condition is satisfied.

As an embodiment, the first bit sub-block is a result of encoding the first bit packet.

As an embodiment, the first bit sub-block includes bits in the first bit packet and redundancy check bits corresponding to the bits in the first bit packet.

As an embodiment, the first bit sub-block comprises bits in the first bit packet repeated X times, the X being greater than 1.

As an embodiment, the bits in the first sub-block of bits are used to determine other information than the first sub-packet of bits.

As a sub-embodiment of the above embodiment, the second bit sub-block includes at least one of { CIF field, resource allocation field, MCS (Modulation and Coding Status, modulation coding state) field, NDI field, HARQ process number field, TPC field, field for indicating parameters of DMRS, CRC bits }.

In particular, according to one aspect of the invention, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As an embodiment, the above method has the advantage of improving the transmission reliability of the first bit packet.

As an embodiment, the first coding is used to improve the transmission reliability of the first bit packet.

As an embodiment, the first code is a CRC (Circular Redundancy Check, cyclic redundancy check) code.

As an embodiment, the first code is a linear block code.

As an embodiment, the first code is a convolutional code.

As an example, the first code is TBCC (Tail-biting Convolutional Code, tail biting convolutional code).

As an embodiment, the first bit sub-block is the output of the first encoding.

As an embodiment, a portion of the bits in the first sub-block of bits are the output of the first encoding.

As an embodiment, the bits in the first sub-block of bits consist of the bits in the first packet of bits and the output of the first encoding.

As an embodiment, the output of the first encoding is CRC bits corresponding to the first bit packet.

As an embodiment, the output of the first encoding is PC bits corresponding to the first bit packet.

Specifically, according to one aspect of the present invention, the step a further includes the steps of:

Step A0. sends the first information.

Wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As an embodiment, the above method has the advantage of supporting more flexible configuration of information bit transmission, thereby improving transmission efficiency and reliability.

As an embodiment, the first information is semi-statically configured.

As an embodiment, the first information is UE-specific.

As an embodiment, the first information includes one or more RRC (Radio Resource Control ) IEs (Information Element, information particles).

As a sub-embodiment of the above embodiment, a part of the RRC IEs in the plurality of RRC IEs are cell-common, and the remaining part of the RRC IEs in the plurality of RRC IEs are UE-specific.

As an embodiment, the first information explicitly indicates at least one of { the number of bits in the first bit sub-block, the first encoding, the K candidate values }.

As an embodiment, the first information implicitly indicates at least one of { the number of bits in the first bit sub-block, the first encoding, the K candidate values }.

As an embodiment, the first information indicates a current transmission setting of the UE, the transmission setting implicitly indicating at least one of { the number of bits in the first bit sub-block, the first coding, the K candidate values }.

As an embodiment, the transmission settings comprise multiple antenna related parameters.

As an embodiment, the transmission settings comprise carrier aggregation related parameters.

step a1. Determining the number of bits in the third sub-block of bits.

Wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As an embodiment, the above method has the advantage that the reliability of the transmission of the first bit sub-block is further ensured.

As an embodiment, the positions of the bits in the third sub-block of bits in the first block of bits are discontinuous.

As an embodiment, the positions of the bits in the third sub-block of bits in the first block of bits are consecutive.

As an embodiment, the number of bits in the third sub-block of bits ensures that the probability of the receiver erroneously decoding the first sub-block of bits based on a first assumption that the number of bits in the second sub-block of bits is equal to the maximum of the K candidate values is not higher than the first threshold.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2. The number of bits in the third sub-block of bits is equal to L-L1-L2. The L, the L1 and the L2 are all positive integers, wherein the L is greater than L1+L2.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, the maximum value of the K candidate values is K1, and the number of bits in the third bit sub-block is greater than L-L1-K1.

As an embodiment, the base station allocates P1 CCEs (Control Channel Element, control channel particles) to the first bit block based on the first threshold, and the number of bits in the codeword carried on the P1 CCEs is the L.

As an embodiment, the number of bits in the third sub-block of bits ensures that the probability of the receiver to erroneously decode the first block of bits based on a second assumption that is: the first sub-block of bits received according to the first hypothesis is correctly decoded and used to determine the number of bits in the second sub-block of bits.

As an embodiment, the first threshold is smaller than the second threshold.

As an embodiment, the first threshold value is equal to the second threshold value.

As one embodiment, the received first bit sub-block is the same as the first bit sub-block transmitted by the base station (i.e., the first bit sub-block is correctly coded).

As one embodiment, the received first bit sub-block is different from the first bit sub-block transmitted by the base station (i.e., the first bit sub-block is incorrectly coded).

As an embodiment, { UCI (Uplink Control Information ) fed back by the receiver of the first radio signal, modulation scheme of the first radio signal, transmission power of the first radio signal } at least one of which is used to determine the number of bits in the third bit sub-block.

As an embodiment, the third sub-block of bits comprises a first set of frozen bits and a second set of frozen bits. The maximum of the K candidate values is used to determine the number of bits in the first frozen bit set. The number of bits in the second sub-block of bits is used to determine the number of bits in the second frozen bit set.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, the number of bits in the second bit sub-block is L2, and the maximum value of the K candidate values is K1. The number of bits in the first frozen bit set is equal to L-L1-K1. The number of bits in the second frozen bit set is equal to K1-L2. The L, L1, L2 and K1 are all positive integers.

Specifically, according to one aspect of the present invention, the first code is based on an error-detecting code (error-detecting code).

As an embodiment, the above method has the advantage that the error detection code can be used to detect the correctness of the transmission of the indication information, thereby improving the reliability of detecting the transmission of the indication information.

As an embodiment, the error detection code is a CRC (Circular Redundancy Check, cyclic redundancy check) code.

As an embodiment, the error detection code is a PC (Parity Check) code.

In particular, according to an aspect of the invention, the first coding is based on an error-correcting code.

As an embodiment, the above method has the advantage that the error correction code can correct the error transmission of the indication information, thereby improving the transmission reliability of the detection indication information.

As an example, the error correction code is TBCC (Tail-biting Block Convolutional Code, tail biting convolutional code).

As an embodiment, the error correction code is a Turbo code.

As an embodiment, the first encoding comprises a first stage encoding and a second stage encoding, the output of the first stage encoding being used as the input of the second stage encoding. The first encoding uses an error detection code and the second encoding uses an error correction code.

Specifically, according to one aspect of the present invention, the average channel capacity of the sub-channel mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channel mapped by the bits in the second bit sub-block.

As an embodiment, the above method has the advantage that the second bit sub-block corresponds to a better sub-channel than the first bit sub-block, thereby improving the transmission reliability of the second bit sub-block.

As an embodiment, the channel capacity of the Sub-channel (Sub-channel) to which any bit in the second bit Sub-block is mapped is larger than the channel capacity of the Sub-channel to which any bit in the first bit Sub-block is mapped.

As an embodiment, the channel capacity corresponding to at least one sub-channel in the sub-channels mapped by the bits in the second bit sub-block is smaller than the channel capacity corresponding to at least one sub-channel in the sub-channels mapped by the bits in the first bit sub-block, and the average value of the channel capacities of the sub-channels mapped by the bits in the second bit sub-block is larger than the average value of the channel capacities of the sub-channels mapped by the bits in the first bit sub-block.

As an embodiment, the base station assumes that the decoding order of the receiver of the first wireless signal receiver is from a bit corresponding to a subchannel with a low channel capacity to a bit corresponding to a subchannel with a high channel capacity.

In particular, according to an aspect of the invention, the arbitrary bits in the first sub-block of bits are decoded before the arbitrary bits in the second sub-block of bits.

As an embodiment, the above method has the advantage that the first sub-block of bits can be pre-empted in the decoding order, thereby improving the decoding efficiency.

As an embodiment, the third sub-block of bits comprises a first set of frozen bits and a second set of frozen bits. The maximum of the K candidate values is used to determine the number of bits in the first frozen bit set. The number of bits in the second sub-block of bits is used to determine the number of bits in the second frozen bit set. The receiver performs serial channel decoding based on the first channel coding on the received first bit block: 1) Taking the bits in the first frozen bit set as known bits, and performing serial decoding on the output of the sub-channel where the bits in the first bit sub-block are positioned to obtain an estimated value of the first bit sub-block; 2) Obtaining the first bit packet using the estimated value of the first bit sub-block as an input to a decoder based on the first encoding; 3) Using the first bit packet to determine a number of bits in the second sub-block of bits, thereby determining the second set of frozen bits; 4) And using the first bit packet to recover the bits in the first bit sub-block, using the bits in the second frozen bit set and the bits in the first bit sub-block as known bits, and performing serial decoding on the output of the sub-channel where the bits in the second bit sub-block are located to obtain the bits in the second bit sub-block (i.e. recovering the first bit block).

As an embodiment, the serial channel decoding order based on the first channel coding is from the bit corresponding to the sub-channel with low channel capacity to the bit corresponding to the sub-channel with high channel capacity, and the capacity of the sub-channel corresponding to any bit in the first bit sub-block is lower than the capacity of the sub-channel corresponding to any bit in the second bit sub-block.

As an embodiment, the capacity of the sub-channel corresponding to any bit in the first frozen bit set is lower than the capacity of the sub-channel corresponding to any bit in the first bit sub-block, and the capacity of the sub-channel corresponding to any bit in the first bit sub-block is lower than the capacity of the sub-channel corresponding to any bit in the second frozen bit set.

As an embodiment, the serial channel decoding order based on the first channel coding is from a bit corresponding to a sub-channel with a high channel capacity to a bit corresponding to a sub-channel with a low channel capacity, and the capacity of the sub-channel corresponding to any bit in the first bit sub-block is higher than the capacity of the sub-channel corresponding to any bit in the second bit sub-block.

As an embodiment, the first bit block is multiplied by a generation matrix based on a polarization code in the first channel coding to obtain the output bit block. The row number of the generator matrix corresponding to any one bit in the first bit sub-block is smaller than the row number of the generator matrix corresponding to any one bit in the second bit sub-block. The base station assumes that the decoding order of the received bit blocks by the receiver is in increasing order of the row numbers of the generator matrix corresponding to the bits in the received bit blocks.

As an embodiment, the generator matrix is a Kronecker matrix.

As an embodiment, the generator matrix is a matrix obtained by performing bit inversion on a row number of a Kronecker matrix.

In particular, according to an aspect of the invention, the second sub-block of bits comprises a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As an embodiment, the above method has the advantage that the second set of bits acts as a redundancy check for the first sub-block of bits and the first set of bits, thereby improving the reliability of the transmission.

As an embodiment, the bits in the second set of bits are CRC (Circular Redundancy Check, cyclic redundancy check) bits corresponding to the bits in the first sub-block of bits and the bits in the second sub-block of bits.

As an embodiment, the bits in the second bit set are PC (Parity Check) bits corresponding to the bits in the first bit sub-block and the bits in the second bit sub-block.

As an embodiment, the bits in the second set of bits correspond to a CRC generator polynomial, the inputs of which are the bits in the first sub-block of bits and the bits in the second sub-block of bits.

Specifically, according to one aspect of the present invention, the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As an embodiment, the above method has the advantage that the second bit sub-block can be configured more flexibly, and the additional signaling overhead is saved.

As an embodiment, the bits in the first bit packet explicitly indicate the position of the bits in the second bit sub-block in the first bit block.

As an embodiment, the bits in the first bit packet implicitly indicate the position of the bits in the second bit sub-block in the first bit block.

As an embodiment, the bits in the first bit packet indicate the relative positions of the second bit sub-block and the first bit sub-block.

As an embodiment, the bits in the first bit packet explicitly indicate the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet implicitly indicate the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet indicate the number of bits in the second bit sub-block, and the number of bits in the second bit sub-block corresponds to the information format of the second bit sub-block one to one.

As an embodiment, bits in the first bit packet are used to partially determine the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet together with other configuration parameters determine the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet explicitly indicate the polynomial corresponding to the redundancy check bits in the first bit block.

As an embodiment, the bits in the first bit packet implicitly indicate a polynomial corresponding to the redundancy check bits in the first bit block.

As an embodiment, the bits in the first bit packet indicate the number of bits in the second bit sub-block, and the number of bits in the two bit sub-block determines a polynomial corresponding to the redundancy check bits in the first bit block.

Specifically, according to an aspect of the present invention, the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

As an embodiment, the above method has the advantage of reducing the number of blind tests on the physical layer control channel by the UE side.

As an embodiment, the physical layer control channel is a physical layer channel that can only carry physical layer signaling.

As one embodiment, the DCI is UE-specific.

As an embodiment, the physical layer control channel is a PDCCH.

As an embodiment, the physical layer control channel is ePDCCH (enhanced PDCCH), enhanced physical layer downlink control channel.

As an embodiment, the physical layer control channel is a spdcc (short PDCCH) short physical layer downlink control channel.

As an embodiment, the physical layer control channel is an NR-PDCCH (New Radio PDCCH, new Radio physical layer downlink control channel).

The invention relates to a method used in a user equipment for channel coding, comprising the following steps:

-step a. Receiving a first wireless signal;

-step b. Performing a first channel decoding.

Wherein the first channel coding corresponds to a first channel coding, the first channel coding being based on a polarization code, a first block of bits being used for input of the first channel coding. The output of the first channel code is used to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in a first bit packet are used to generate the first sub-block of bits. The first bit packet is related to the number of bits in the second bit sub-block or the first bit packet is related to the number of bits in the first bit block. The first bit packet includes a positive integer number of bits in the first bit sub-block and the second bit sub-block, respectively. The number of bits in the second sub-block of bits is one of the K candidate values. The candidate value is a positive integer, and K is a positive integer greater than 1. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

As one embodiment, the first channel coding is used to recover the first block of bits.

As one embodiment, the first channel coding is used to recover the second bit sub-block.

As one embodiment, the first channel coding is used to recover a portion of the bits in the second sub-block of bits.

As one embodiment, the first wireless signal carries check information corresponding to the first bit block, and the channel decoding determines whether to correctly recover the first bit block based on the check information.

As one embodiment, the first bit block includes check information corresponding to information bits in the first bit block, and the channel decoding determines whether to correctly recover the first bit block based on the check information.

Specifically, according to one aspect of the present invention, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

step A0. receives the first information.

Specifically, according to one aspect of the present invention, the step B further includes the steps of:

step B0. determines the number of bits in the third bit sub-block.

As one embodiment, the number of bits in the third sub-block of bits ensures that the probability of the receiver error coding the first sub-block of bits based on the first assumption is not higher than the first threshold.

As one embodiment, the number of bits in the first sub-block of bits is L1. The number of bits in the second sub-block of bits is L2. The number of bits in the third sub-block of bits is equal to L-L1-L2. The L, the L1 and the L2 are all positive integers, wherein the L is greater than L1+L2.

As one embodiment, the first channel coding is serial channel coding. The first bit sub-block is recovered before the second bit sub-block.

As one embodiment, the first channel coding uses the first sub-block of bits as known bits in a subsequent coding process after recovering the first sub-block of bits.

As an embodiment, the first bit block consists of bits in the first bit sub-block, bits in the second bit sub-block and bits in the third bit sub-block. The third sub-block of bits includes a first set of frozen bits and a second set of frozen bits. The maximum of the K candidate values is used to determine the number of bits in the first frozen bit set. The number of bits in the second sub-block of bits is used to determine the number of bits in the second frozen bit set. The process of the first channel coding is: 1) Taking the bits in the first frozen bit set as known bits, and performing serial decoding on the output of the sub-channel where the bits in the first bit sub-block are positioned to obtain an estimated value of the first bit sub-block; 2) Obtaining the first bit packet using the estimated value of the first bit sub-block as an input to a decoder based on the first encoding; 3) Using the first bit packet to determine a number of bits in the second sub-block of bits, thereby determining the second set of frozen bits; 4) And using the first bit packet to recover the bits in the first bit sub-block, using the bits in the first bit sub-block and the bits in the second frozen bit set as known bits, and performing serial decoding on the output of the sub-channel where the bits in the second bit sub-block are located to obtain the bits in the second bit sub-block (i.e. recovering the first bit block).

As an embodiment, the bits in the second set of bits are used to check the bits in the first sub-block of bits and the bits in the first set to determine if the reception is correct.

As an embodiment, the Check is a PC (Parity Check).

As an embodiment, the check is a CRC (Circular Redundancy Check, cyclic redundancy check).

The invention discloses a base station device used for channel coding, which comprises the following modules:

-a first execution module: for performing a first channel coding;

-a first transmission module: for transmitting the first wireless signal.

As an embodiment, the above base station apparatus is characterized in that an output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As an embodiment, the above base station device is characterized in that the first execution module is further used for transmitting the first information. Wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As an embodiment, the above base station device is characterized in that the first execution module is further used for determining the number of bits in the third sub-block of bits. Wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As an embodiment, the above base station apparatus is characterized in that the first code is based on an error-detecting code (error-detecting code).

As an embodiment, the above base station apparatus is characterized in that the first code is based on an error-correcting code (error-correcting code).

As an embodiment, the above base station device is characterized in that the average channel capacity of the sub-channels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As an embodiment, the above base station device is characterized in that any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As an embodiment, the above base station device is characterized in that the second bit sub-block comprises a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As an embodiment, the above base station apparatus is characterized in that the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As an embodiment, the above base station apparatus is characterized in that the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

The invention discloses a method used in user equipment of channel coding, which comprises the following steps:

-step a. Receiving a first wireless signal;

-step b. Performing a first channel decoding.

As an embodiment, the above-mentioned user equipment is characterized in that the output of the first bit packet after the first encoding is used for determining the first bit sub-block.

As an embodiment, the above-mentioned user equipment is characterized in that the first receiving module is further used for receiving the first information. Wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As an embodiment, the above user equipment is characterized in that the second execution module is further configured to determine the number of bits in the third sub-block of bits. Wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As an embodiment, the above-mentioned user equipment is characterized in that the first code is based on an error-detecting code.

As an embodiment, the above-mentioned user equipment is characterized in that the first code is based on an error-correcting code.

As an embodiment, the above-mentioned user equipment is characterized in that the average channel capacity of the sub-channel mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channel mapped by the bits in the second bit sub-block.

As an embodiment the above user equipment is characterized in that any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As an embodiment, the above-mentioned user equipment is characterized in that the second bit sub-block comprises a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As an embodiment, the above user equipment is characterized in that the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As an embodiment, the above user equipment is characterized in that the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

As an embodiment, the present invention has the following advantages over the conventional scheme:

-the characteristic of Polar code serial decoding is utilized, and the blind detection times at the UE side are reduced through the internal indication of the code block;

-by additional encoding of the indication information, the reliability of the transmission of the indication information is increased;

support of more flexible and diverse DCI formats;

-guaranteeing reliability of DCI transmission.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings in which:

fig. 1 shows a flow chart of wireless transmission according to an embodiment of the invention;

FIG. 2 shows a schematic diagram of constructing a first bit block according to one embodiment of the invention;

fig. 3 shows a schematic diagram of a relationship between a first bit block and a first wireless signal according to one embodiment of the invention;

FIG. 4 shows a schematic diagram of a first encoding according to an embodiment of the invention;

FIG. 5 shows a schematic diagram of a relationship of { first bit sub-block, first set of bits in second bit sub-block } to second set of bits in second bit sub-block, according to one embodiment of the invention;

Fig. 6 shows a schematic diagram of a first channel coding according to an embodiment of the invention;

FIG. 7 shows a schematic diagram of first channel decoding according to one embodiment of the invention;

fig. 8 shows a schematic diagram of a mapping relationship of a first bit sub-block and a second bit sub-block on a sub-channel according to an embodiment of the present invention;

FIG. 9 shows a schematic diagram of a first bit sub-block and a second bit sub-block in decoding order according to one embodiment of the invention;

fig. 10 shows a block diagram of a processing arrangement for use in a base station according to an embodiment of the invention;

fig. 11 shows a block diagram of a processing arrangement for use in a user equipment according to an embodiment of the invention.

Example 1

Embodiment 1 illustrates a flow chart of wireless transmission, as shown in fig. 1. In fig. 1, a base station N1 is a serving cell maintenance base station of a UE U2. In fig. 1, the steps in blocks F1, F2 and F3 are optional, respectively.

For N1, transmitting first information in step S11; determining the number of bits in the third bit sub-block in step S12; performing first channel coding in step S13; the first wireless signal is transmitted in step S14.

For U2, receiving first information in step S21; receiving a first wireless signal in step S22; determining the number of bits in the third sub-block of bits in step S23; the first channel decoding is performed in step S24.

In embodiment 1, a first block of bits is used by N1 for the input of a first channel code. The first channel coding is based on a polarization code. The first channel coding corresponds to a first channel coding. The output of the first channel code is used by N1 to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in the first bit packet are used by N1 to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block. The first bit packet includes a positive integer number of bits in the first bit sub-block and the second bit sub-block, respectively. The number of bits in the second sub-block of bits is one of the K candidate values. The candidate value is a positive integer, and K is a positive integer greater than 1. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

As a sub-embodiment 1 of embodiment 1, an output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As sub-embodiment 2 of embodiment 1, the step in block F1 is selected, the first information being used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As sub-embodiment 3 of embodiment 1, a block F2 is selected, the first bit block further comprising bits in a third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As sub-embodiment 4 of embodiment 1, the first code is based on an error-detecting code.

As sub-embodiment 5 of embodiment 1, the first encoding is based on an error-correction code (error-correction code).

As sub-embodiment 6 of embodiment 1, the average channel capacity of the sub-channel mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channel mapped by the bits in the second bit sub-block.

As sub-embodiment 7 of embodiment 1, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As sub-embodiment 8 of embodiment 1, the second sub-block of bits includes a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 1, the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As a sub-embodiment 10 of embodiment 1, the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

As a sub-embodiment 11 of embodiment 1, the steps in block F3 exist, the first bit block further comprising bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As a sub-embodiment 12 of embodiment 1, the first bit packet indicates a format of physical layer signaling corresponding to the first bit block.

As sub-embodiment 13 of embodiment 1, the first bit packet indicates the number of bits in the second bit sub-block from the K candidate values.

As sub-embodiment 14 of embodiment 1, each bit in the first bit packet occurs X times in the first bit sub-block, where X is a positive integer greater than 1.

As a sub-embodiment 15 of embodiment 1, the number of bits in the first bit packet is equal to ceil (log 2 (K)), where ceil represents a round-up.

As Sub-embodiment 16 of embodiment 1, the channel capacity of the Sub-channel (Sub-channel) to which any bit in the second bit Sub-block is mapped is larger than the channel capacity of the Sub-channel to which any bit in the first bit Sub-block is mapped.

As sub-embodiment 17 of embodiment 1, the index of the sub-channel corresponding to any bit in the first bit sub-block is smaller than the index of the sub-channel corresponding to any bit in the second bit sub-block.

The above sub-embodiments 1 to 11 can be arbitrarily combined without collision.

Example 2

Embodiment 2 illustrates a schematic diagram of constructing a first bit block, as shown in fig. 2.

In embodiment 2, a first bit block is used by the base station for the input of the first channel coding, the bits in the first bit block consisting of bits in the first bit sub-block, bits in the second bit sub-block, and bits in the third bit sub-block. The number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2. And the base station calculates the number of bits in the third bit sub-block according to the L, the L1 and the L2 to be L-L1-L2. The bits in the third sub-block of bits are frozen bits. The freeze bit is a bit with a default value. The base station constructs a switching matrix (Permutation Matrix) P with the row number and the column number of L, cascades the first bit sub-block, the second bit sub-block and the third bit sub-block to obtain a bit sequence with the length of L, and multiplies the bit sequence by the switching matrix P to obtain the first bit block. The switching matrix refers to: any row or column of a matrix includes only one 1, the remainder being 0.

As sub-embodiment 1 of embodiment 2, bits in the first sub-block of bits are consecutive in the first sub-block of bits.

As sub-embodiment 2 of embodiment 2, the bits in the first sub-block of bits are discontinuous in the first sub-block of bits.

As sub-embodiment 3 of embodiment 2, the bits in the second sub-block of bits are consecutive in the first sub-block of bits.

As sub-embodiment 4 of embodiment 2, the bits in the second sub-block of bits are discontinuous in the first sub-block of bits.

As sub-embodiment 5 of embodiment 2, the bits in the third sub-block of bits are consecutive in the first block of bits.

As sub-embodiment 6 of embodiment 2, the bits in the third sub-block of bits are discontinuous in the first sub-block of bits.

Example 3

Embodiment 3 illustrates a schematic diagram of the relationship between the first bit block and the first wireless signal, as shown in fig. 3.

In embodiment 3, at the base station side, a first bit block is used for the input of a first channel coding module, and the output of the first channel coding module obtains a first wireless signal after passing through a post-processing module. At the UE end, the output of the first wireless signal after passing through the preprocessing module is used as the input of the first channel decoding module, and the first bit block is the output of the first channel decoding module. The first channel coding module and the first channel decoding module are respectively a coding module and a decoding module based on polarization codes.

As a sub-embodiment 1 of embodiment 3, the first radio signal is an OFDM symbol carrying the first bit block, and the post-processing operations in the post-processing module include operations of modulation mapping, multi-antenna precoding, RE (Resource Element) mapping, and OFDM signal generation.

As sub-embodiment 2 of embodiment 3, the first wireless signal is an OFDM symbol carrying the first bit block, and the preprocessing operation in the preprocessing module includes operations of OFDM signal demodulation, channel estimation, channel equalization, RE demapping, and demodulation mapping.

As a sub-embodiment 3 of embodiment 3, the output of the first channel coding is the result of multiplying the first bit block by a Kronecker matrix.

As sub-embodiment 4 of embodiment 3, the output of the first channel coding is a result of multiplying a bit sequence formed by bit-inverting the bit sequence number in the first bit block by a Kronecker matrix.

As sub-embodiment 5 of embodiment 3, the first channel decoding module is an SC (Successive Cancelation Decoding, serial cancellation) decoder based on a polarization code.

As sub-embodiment 6 of embodiment 3, the first channel decoding module is a SCL (Successive Cancellation List, serial cancellation list) decoder based on a polar code.

As sub-embodiment 7 of embodiment 3, the first channel decoding module is based on a SCS (Successive Cancellation Stack) decoder.

Example 4

Embodiment 4 illustrates a schematic diagram of a first code, as shown in fig. 4.

In embodiment 4, the first code includes an error detection code generation module and an error correction code generation module. A first bit packet is used for an input of the error-detecting code generating module, an output of the error-detecting code generating module being used as an input of the error-correcting code generating module together with the first bit packet, a first bit sub-block being an output of the error-correcting code generating module.

As sub-embodiment 1 of embodiment 4, the error detection code is a cyclic redundancy check code.

As sub-embodiment 2 of embodiment 4, the error detection code is a parity check code.

As sub-embodiment 3 of embodiment 4, the error correction code is a forward error correction (FEC, forward Error Correction) code.

As a sub-embodiment 4 of embodiment 4, the error correction code is a linear block code.

As a sub-embodiment 5 of embodiment 4, the error correction code is a tail biting convolutional code.

As a sub-embodiment 6 of embodiment 4, the error correction code is a Turbo code.

Example 5

Embodiment 5 illustrates a schematic diagram of the relationship of { first bit sub-block, first bit set in second bit sub-block } to second bit set in second bit sub-block, as shown in fig. 5.

In embodiment 5, the first set of bits in the first sub-block of bits and the second sub-block of bits are inputs to a parity bit generation module and the second set of bits in the second sub-block of bits are outputs of the parity bit generation module.

As sub-embodiment 1 of embodiment 5, the check bit generation module is a CRC code generator, and the second bit set is the first bit sub-block and the CRC code of the first bit set.

As sub-embodiment 2 of embodiment 5, the check bit generation module is a parity code generator, and the second bit set is the first bit sub-block and a parity code of the first bit set.

Example 6

Embodiment 6 illustrates a schematic diagram of a first channel coding, as shown in fig. 6.

In embodiment 6, the first channel coding includes a first bit packet generation module, a first coding module, a first bit block generation module, and a polarization code generation module. The number of bits in the second sub-block of bits is used as input to the first bit packet generation module, the output of which is the first bit packet. The first bit packet is applied to an input of the first encoding module, an output of which is a first bit sub-block. The second sub-block of bits includes a first set of bits and a second set of bits. The first sub-block of bits and the first set of bits are used for an input of the first bit block generation module, an output of the first bit block generation module being a first bit block. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The first bit block is used for the polarization code generation module. The output of the polarization code generation module is the output of the first channel code.

As sub-embodiment 1 of embodiment 6, the bits in the first bit packet are used to determine the number of bits in the second bit sub-block.

As sub-embodiment 2 of embodiment 6, the value of the first bit packet is equal to the number of bits in the second bit sub-block.

As sub-embodiment 3 of embodiment 6, the value of one bit sub-block in the first bit packet is equal to the number of bits in the second bit sub-block.

As sub-embodiment 4 of embodiment 6, the first coding module is as shown in embodiment 4.

As sub-embodiment 5 of embodiment 6, the first bit block generation module calculates the number of bits in the third bit sub-block from the number of bits in the first bit sub-block and the number of bits in the second bit sub-block, and then performs the operation shown in embodiment 2 to generate the first bit block.

As sub-embodiment 6 of embodiment 6, the length of the first bit block is a power of 2 to N, where N is a positive integer.

As sub-embodiment 7 of embodiment 6, the first bit block generating module includes the check bit generating module of embodiment 5.

Example 7

Embodiment 7 illustrates a schematic diagram of first channel decoding according to an embodiment of the present invention, as shown in fig. 7.

In embodiment 7, the first channel decoding includes a polar code decoding I module, a first decoding module, a first encoding module, an information bit number determining module, a polar code decoding II module, and a bit checking module.

In embodiment 7, the polarization code decoding I module and the polarization code decoding II module both correspond to the polarization code generating module in embodiment 6. The polarization code generation module is related to the length of the first bit block. The bit check module corresponds to the check bit generation module in embodiment 5. The first bit block is composed of bits in the first bit sub-block, bits in the second bit sub-block, and bits in the third bit sub-block. The bits in the third sub-block of bits are frozen bits. The third sub-block of bits includes a first set of frozen bits and a second set of frozen bits. The bits in the first sub-block of bits are used to determine the number of bits in the second sub-block of bits. The number of bits in the second sub-block of bits is one candidate of K candidates. The maximum of the K candidate values is used to determine the first frozen bit set. The number of bits in the second sub-block of bits is used to determine the second set of frozen bits. The second sub-block of bits includes a first set of bits and a second set of bits. The second set of bits is check bits corresponding to bits in the first sub-block of bits and bits in the first set of bits.

In embodiment 7, the first frozen bit set and the demodulation result of the first wireless signal are used as input of a polar code decoding I block, and the estimated value of the first bit sub-block is output of the polar code decoding I block. The estimated value of the first sub-block of bits is applied to an input of the first coding module, and the first packet of bits is an output of the first coding module. The first coding module corresponds to the first coding module. The first bit packet is used for an input of the first encoding module, an output of which is the first bit sub-block. The first bit packet is also used as input to the information bit number determination module, the output of which is the number of bits in the second sub-block of bits and the second frozen set of bits. The first sub-block of bits, the number of bits in the second sub-block of bits, and the second set of frozen bits are used for an input of the polar code decoding II module, an output of which is the second sub-block of bits. The first bit sub-block and the second bit sub-block are used for input of the bit check module, the output of the bit check module being a first set of bits in the second bit sub-block.

As sub-embodiment 1 of embodiment 7, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, the number of bits in the second bit sub-block is L2, and the maximum value of the K candidate values is K1. The number of bits in the third sub-block of bits is L-L1-L2, wherein the number of bits in the first set of frozen bits is L-L1-K1 and the number of bits in the second set of frozen bits is K1-L2.

As sub-embodiment 2 of embodiment 7, the polarization code decoding I module and the polarization code decoding II module generate matrices based on the same polarization code. The polarization code generation matrix is used for the polarization code generation module. The bits in the first frozen bit set are used as known bits in the polar code decoding I module. The polar code decoding I module decodes only the output of the subchannel corresponding to the bits in the first bit sub-block. The bits in the first sub-block of bits are used as known bits in the polar code decoding II module.

As sub-embodiment 3 of embodiment 7, the polarization code decoding I module and the polarization code decoding II module use SC (Success ive Cancellat ion) decoders.

As sub-embodiment 4 of embodiment 7, the first coding module is as shown in embodiment 4.

As sub-embodiment 5 of embodiment 7, the second set of bits is a CRC check bit corresponding to the bits in the first sub-block of bits and the bits in the first set of bits.

Example 8

Embodiment 8 illustrates a schematic diagram of the mapping relationship of the first bit sub-block and the second bit sub-block on the sub-channel, as shown in fig. 8.

The number of bits in the first sub-block of bits is L1 and the number of bits in the second sub-block of bits is L2. Bits in the first bit sub-block are in one-to-one correspondence with L1 sub-channels, and bits in the second bit sub-block are in one-to-one correspondence with L2 sub-channels. The channel capacity corresponding to any one of the L1 sub-channels is higher than the channel capacity corresponding to any one of the L2 sub-channels.

Example 9

Embodiment 9 illustrates a schematic diagram of the first bit sub-block and the second bit sub-block in decoding order, as shown in fig. 9.

In embodiment 9, any bits in the first bit sub-block are decoded before any bits in the second bit sub-block

As a sub-embodiment 1 of embodiment 9, an sc decoder is used for the decoding.

As sub-embodiment 2 of embodiment 9, an scl decoder is used for said decoding.

As sub-embodiment 3 of embodiment 9, an scs decoder is used for the decoding.

Example 10

Embodiment 10 illustrates a block diagram of a processing apparatus for use in a base station, as shown in fig. 10. In fig. 10, the base station apparatus 200 is mainly composed of a first execution module 201 and a first transmission module 202.

In embodiment 10, the first performing module 201 is configured to perform first channel coding, and the first transmitting module 202 is configured to transmit the first wireless signal.

In embodiment 10, a first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The output of the first channel code is used to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in a first bit packet are used to generate the first sub-block of bits. The number of bits in the second sub-block of bits is related to the first packet of bits. The first bit packet includes a positive integer number of bits in the first bit sub-block and the second bit sub-block, respectively. The number of bits in the second sub-block of bits is one of the K candidate values. The candidate value is a positive integer, and K is a positive integer greater than 1. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

As sub-embodiment 1 of embodiment 10, an output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As sub-embodiment 2 of embodiment 10, the first execution module 201 is further configured to send the first information. Wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As sub-embodiment 3 of embodiment 10, the first execution module 201 is further used to determine the number of bits in the third sub-block of bits. Wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As sub-embodiment 4 of embodiment 10, the first code is based on an error-detecting code.

As sub-embodiment 5 of embodiment 10, the first encoding is based on an error-correction code (error-correction code).

As sub-embodiment 6 of embodiment 10, the average channel capacity of the sub-channels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As sub-embodiment 7 of embodiment 10, any bits in the first bit sub-block are decoded before any bits in the second bit sub-block.

As sub-embodiment 8 of embodiment 10, the second sub-block of bits includes a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 10, the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As a sub-embodiment 10 of embodiment 10, the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

Example 11

Embodiment 11 illustrates a block diagram of a processing apparatus for use in a user equipment, as shown in fig. 10. In fig. 10, the user device 300 is mainly composed of a first receiving module 301 and a second executing module 302.

In embodiment 11, the first receiving module 301 is configured to receive a first wireless signal; the second execution module 302 is configured to execute the first channel decoding.

In embodiment 11, the first channel coding corresponds to a first channel coding, the first channel coding being based on a polarization code, a first block of bits being used for input of the first channel coding. The output of the first channel code is used to generate the first wireless signal. The first bit block includes bits in a first bit sub-block and bits in a second bit sub-block. Bits in a first bit packet are used to generate the first sub-block of bits. The number of bits in the second sub-block of bits is related to the first packet of bits. The first bit packet includes a positive integer number of bits in the first bit sub-block and the second bit sub-block, respectively. The number of bits in the second sub-block of bits is one of the K candidate values. The candidate value is a positive integer, and K is a positive integer greater than 1. The number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

As sub-embodiment 1 of embodiment 11, an output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As sub-embodiment 2 of embodiment 11, the first receiving module 301 is further configured to receive first information. Wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

As sub-embodiment 3 of embodiment 11, the second execution module 302 is further configured to determine the number of bits in the third sub-block of bits. Wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits. The maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

As sub-embodiment 4 of embodiment 11, the first code is based on an error-detecting code.

As sub-embodiment 5 of embodiment 11, the first encoding is based on an error-correction code (error-correction code).

As sub-embodiment 6 of embodiment 11, the average channel capacity of the sub-channels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As sub-embodiment 7 of embodiment 11, any bits in the first bit sub-block are decoded before any bits in the second bit sub-block.

As sub-embodiment 8 of embodiment 11, the second sub-block of bits includes a first set of bits and a second set of bits. The bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 11, the bits in the first bit packet are further used to determine at least one of { the position of the bits in the second bit sub-block in the first bit block, the information format of the second bit sub-block, and the polynomial corresponding to the redundancy check bits of the first bit block }.

As a sub-embodiment 10 of embodiment 11, the first radio signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI).

Those of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described methods may be implemented by a program that instructs associated hardware, and the program may be stored on a computer readable storage medium, such as a read-only memory, a hard disk or an optical disk. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module unit in the above embodiment may be implemented in a hardware form or may be implemented in a software functional module form, and the application is not limited to any specific combination of software and hardware. The UE or the terminal in the invention comprises, but is not limited to, wireless communication equipment such as mobile phones, tablet computers, notebooks, network cards, NB-IOT terminals, eMTC terminals and the like. The base station or system equipment in the invention comprises, but is not limited to, wireless communication equipment such as macro cellular base stations, micro cellular base stations, home base stations, relay base stations and the like.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method in a base station for channel coding, comprising the steps of:

-step a. Performing a first channel coding;

-step b. Transmitting a first wireless signal;

wherein a first block of bits is used for the input of the first channel coding; the first channel coding is based on a polarization code; the output of the first channel code is used to generate the first wireless signal; the first bit block comprises bits in a first bit sub-block and bits in a second bit sub-block; the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI); bits in a first bit packet are used to generate the first sub-block of bits; bits in the first bit packet are used to determine a number of bits in the second bit sub-block; the first bit packet, the first bit subblock and the second bit subblock respectively comprise a positive integer number of bits; the number of bits in the second sub-block of bits is one of the K candidate values; the candidate value is a positive integer, and K is a positive integer greater than 1; the number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

2. The method of claim 1, wherein the output of the first bit packet after first encoding is used to determine the first bit sub-block.

3. The method according to claim 2, wherein the step a further comprises the steps of:

-step A0. sends a first message;

4. A method according to any one of claims 1 to 3, wherein step a further comprises the steps of:

determining the number of bits in the third sub-block of bits;

wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits; the maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

5. A method according to any of claims 2 to 3, characterized in that the first encoding is based on error-detecting codes (error-detecting codes); or the first encoding is based on an error-correction code (error-correction code).

6. A method according to any of claims 1 to 3, characterized in that the average channel capacity of the sub-channels to which the bits in the first bit sub-block are mapped is smaller than the average channel capacity of the sub-channels to which the bits in the second bit sub-block are mapped; or any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

7. A method according to any of claims 1 to 3, wherein the second sub-block of bits comprises a first set of bits and a second set of bits; the bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

8. A method according to any of claims 1-3, characterized in that the bits in the first bit packet are also used for determining the information format of the second bit sub-block.

9. A method according to any of claims 1 to 3, wherein the first wireless signal is transmitted on a physical layer control channel.

10. A method in a user equipment for channel coding, comprising the steps of:

-step a. Receiving a first wireless signal;

-step b. Performing a first channel decoding;

wherein the first channel coding corresponds to a first channel coding, the first channel coding being based on a polarization code, a first block of bits being used for input of the first channel coding; the output of the first channel code is used to generate the first wireless signal; the first bit block comprises bits in a first bit sub-block and bits in a second bit sub-block; the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI); bits in a first bit packet are used to generate the first sub-block of bits; bits in the first bit packet are used to determine a number of bits in the second bit sub-block; the first bit packet, the first bit subblock and the second bit subblock respectively comprise a positive integer number of bits; the number of bits in the second sub-block of bits is one of the K candidate values; the candidate value is a positive integer, and K is a positive integer greater than 1; the number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

11. The method of claim 10, wherein the output of the first bit packet after first encoding is used to determine the first bit sub-block.

12. The method of claim 11, wherein said step a further comprises the steps of:

-step A0. receives a first message;

13. The method according to any one of claims 10 to 12, wherein said step B further comprises the steps of:

step B0. determines the number of bits in the third bit sub-block;

14. The method according to any of claims 11 to 12, wherein the first encoding is based on error-detecting code (error-detecting code); or the first encoding is based on an error-correction code (error-correction code).

15. The method according to any of the claims 10 to 12, characterized in that the average channel capacity of the sub-channels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block; or any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

16. The method according to any of claims 10 to 12, wherein the second sub-block of bits comprises a first set of bits and a second set of bits; the bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

17. The method according to any of the claims 10 to 12, characterized in that the bits in the first bit packet are also used for determining the information format of the second bit sub-block.

18. The method according to any of claims 10 to 12, wherein the first wireless signal is transmitted on a physical layer control channel.

19. A base station apparatus for channel coding, comprising the following modules:

-a first execution module: for performing a first channel coding;

-a first transmission module: for transmitting a first wireless signal; wherein a first block of bits is used for the input of the first channel coding; the first channel coding is based on a polarization code; the output of the first channel code is used to generate the first wireless signal; the first bit block comprises bits in a first bit sub-block and bits in a second bit sub-block; the first bit sub-block and the second bit sub-block belong to the same Downlink Control Information (DCI); bits in a first bit packet are used to generate the first sub-block of bits; bits in the first bit packet are used to determine a number of bits in the second bit sub-block; the first bit packet, the first bit subblock and the second bit subblock respectively comprise a positive integer number of bits; the number of bits in the second sub-block of bits is one of the K candidate values; the candidate value is a positive integer, and K is a positive integer greater than 1; the number of bits in the first sub-block of bits is greater than the number of bits in the first packet of bits.

20. The base station apparatus of claim 19, wherein the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

21. The base station device of claim 20, wherein the first execution module is further configured to transmit first information; wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

22. The base station device according to any of claims 19 to 21, wherein the first execution module is further configured to determine the number of bits in a third sub-block of bits; wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits; the maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

23. The base station apparatus according to any one of claims 20 to 21, wherein the first coding is based on error-detecting code (error-detecting code); or the first encoding is based on an error-correction code (error-correction code).

24. The base station apparatus according to any one of claims 19 to 21, wherein an average channel capacity of a subchannel mapped by bits in the first bit sub-block is smaller than an average channel capacity of a subchannel mapped by bits in the second bit sub-block; or any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

25. The base station device according to any of claims 19 to 21, wherein the second sub-block of bits comprises a first set of bits and a second set of bits; the bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

26. The base station device according to any of the claims 19 to 21, characterized in that the bits in the first bit packet are also used for determining the information format of the second bit sub-block.

27. The base station apparatus according to any of claims 19 to 21, wherein the first wireless signal is transmitted on a physical layer control channel.

28. A user equipment for channel coding, comprising the following modules:

-a first receiving module: for receiving a first wireless signal;

-a second execution module: for performing a first channel decoding;

29. The user equipment of claim 28, wherein the output of the first bit packet after first encoding is used to determine the first bit sub-block.

30. The user device of claim 29, wherein the first receiving module is further configured to receive first information; wherein the first information is used to determine at least one of { the number of bits in the first sub-block of bits, the first encoding, the K candidate values }.

31. The user equipment according to any of claims 28 to 30, wherein the second execution module is further configured to determine the number of bits in a third sub-block of bits; wherein the first bit block further comprises bits in the third bit sub-block, the bits in the third bit sub-block being frozen bits; the maximum of the K candidate values is related to the number of bits in the third sub-block of bits.

32. The user equipment according to any of claims 29 to 30, wherein the first coding is based on error-detecting code (error-detecting code); or the first encoding is based on an error-correction code (error-correction code).

33. The user equipment according to any of claims 28 to 30, wherein the average channel capacity of the sub-channels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block; or any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

34. The user equipment according to any of claims 28 to 30, wherein the second sub-block of bits comprises a first set of bits and a second set of bits; the bits in the first sub-block of bits and the bits in the first set of bits are used to generate the second set of bits.

35. The user equipment according to any of the claims 28 to 30, characterized in that the bits in the first bit packet are also used for determining the information format of the second bit sub-block.

36. The user equipment according to any of claims 28 to 30, wherein the first radio signal is transmitted on a physical layer control channel.