WO2018145306A1

WO2018145306A1 - Method and apparatus for channel codes in base station and user equipment

Info

Publication number: WO2018145306A1
Application number: PCT/CN2017/073289
Authority: WO
Inventors: 张晓博
Original assignee: 南通朗恒通信技术有限公司
Priority date: 2017-02-12
Filing date: 2017-02-12
Publication date: 2018-08-16
Also published as: CN109952709B; CN109952709A; CN116723542A

Abstract

Disclosed in the present invention are a method and an apparatus for channel codes in a base station and a user equipment. The base station sequentially executes first channel codes and sends a first wireless signal. A first bit block is used for the input of first channel codes. The first channel codes are based on polar codes. The output of the channel codes is used for generating the first wireless signal. The first bit block comprises bits in a first bit subblock and bits in a second bit subblock. Bits in a first bit packet are used for generating the first bit subblock. The first bit packet is related to the number of bits in the second bit subblock, or the first bit packet is related to the number of bits in the first bit block. The number of bits in the first bit subblock is greater than the number of bits in the first bit packet. The number of bits in the first bit subblock is greater than the number of bits in the first bit packet. By means of the present invention, the blind detection burden of a user equipment is reduced or a more flexible information transmission format is supported.

Description

Method and device for channel coding in base station and user equipment

Technical field

The present invention relates to a transmission scheme for wireless signals in a wireless communication system, and more particularly to a method and apparatus for transmission of channel coding.

Background technique

Polar Codes is a coding scheme first proposed by Professor Erdal Arikan of the University of Birken in Turkey in 2008. It can realize the Binary input Discrete Memoryless Channel (B-DMC). Code construction method for capacity. At the 3GPP (3rd Generation Partner Project) RAN1#87 conference, 3GPP determined a control channel coding scheme using a Polar code scheme as a 5G eMBB (Enhanced Mobile Broadband) scenario.

In the traditional LTE (Long Term Evolution) system, different DCI (Downlink Control Information) formats correspond to different numbers of coded bits, and all possible corresponding UEs (User Equipment) according to the current transmission mode. The DCI format performs blind detection on the PDCCH (Physical Downlink Control Channel) carrying DCI. The receiving method of the PDCCH causes the number of blind detections on the UE side to increase as the number of bits corresponding to the DCI increases.

Summary of the invention

The inventors have found through research that the length of the input bit block corresponding to the polarization code generator is 2 to the power of N, and the N is a positive integer. Therefore, for a certain number of information bits, the channel coding based on the polarization code The length of the input bit block corresponding to the device is fixed to the polarization code used, except that the number of frozen bits is different. This characteristic of the polarization code can be used to form a bit block composed of bits, DCI bits, and freeze bits corresponding to the indication information of the number of DCI bits into a block of input bits for generating a polarization code. The receiving end first decodes the indication information of the number of the DCI bits by using the characteristics of the polarization code serial decoder, and secondly determines the exact number of frozen bits in the input bit block by using the indication information, and then freezes the The exact number of bits is used for subsequent decoding to obtain DCI bits, thereby reducing the UE The number of blind checks and the processing burden. The indication information needs to be guaranteed high transmission reliability as the key information of the DCI bit decoding that is first decoded. Therefore, an error check code or an error correction code may be used to perform first coding on the indication information, the output of the first code being used as a corresponding bit of the indication information in the input bit block, thereby ensuring The transmission reliability of the indication information.

In response to the above problems, the present invention provides a solution. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments of the present application may be combined with each other arbitrarily. For example, features in embodiments and embodiments in the first node of the present application may be applied to a second node, and vice versa.

The invention discloses a method used in a base station for channel coding, which comprises the following steps:

- Step A. Performing a first channel coding;

- Step B. Send the first wireless signal.

Wherein the first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As an embodiment, the above method has the advantage that different numbers of information bits use the same channel coding, thereby reducing the number of blind detections and time-frequency occupied resources at the UE side. The bits in the first bit sub-block may be used to determine other information than the first bit packet or to ensure transmission reliability of the first bit packet.

As an embodiment, the first wireless signal is a multi-carrier symbol.

In one embodiment, the first wireless signal is an OFDM (Orthogonal Frequency Division Multiplexing) symbol.

As an embodiment, the first wireless signal is DFT-S-OFDM (Discrete Fourier) Transform Spread OFDM, Discrete Fourier Transform Orthogonal Frequency Division Multiplexing (OFDM) symbol.

As an embodiment, the output of the first channel coding is modulated to generate the first wireless signal.

As an embodiment, the output of the first channel coding is multi-antenna pre-coded to generate the first wireless signal.

As an embodiment, the first block of bits serves as an input to the first channel coding.

As an embodiment, each segment of the first bit block segmentation is used as an input to the first channel coding.

As an embodiment, the first bit block corresponds to a partial bit of the first channel coding input.

As an embodiment, the first block of bits includes only all of the information bits in the first channel coded input.

In one embodiment, the first bit block includes only a partial information bit in the first channel coding input and a parity bit corresponding to the partial information bit.

As an embodiment, the first bit block corresponds to all bits of the first channel coding input.

As an embodiment, the first bit packet explicitly indicates the number of bits in the second bit sub-block.

As an embodiment, the first bit packet implicitly indicates the number of bits in the second bit sub-block.

As an embodiment, an index of the candidate values in the K candidate values is used to determine the first bit packet.

As an embodiment, the value of the first bit sub-block is independent of the bits in the second bit sub-block.

As an embodiment, the position of the bits in the first bit sub-block in the first bit block is determined by default.

As an embodiment, the default determination refers to that no downlink signaling configuration is required.

As an embodiment, the default determination refers to an explicit configuration that does not require downlink signaling.

As an embodiment, the default determination is fixed.

As an embodiment, the default determination means that the position of the first bit sub-block in the first bit block is fixed for the first bit sub-block of a given number of bits.

As an embodiment, the default determination means that the position of the first bit sub-block in the first bit block is fixed for the first bit block of a given number of bits.

As an embodiment, the default determination means that, for the first bit block of a given timing resource, the position of the first bit sub-block in the first bit block is fixed.

As an embodiment, the position of the bits in the first bit sub-block in the first bit block is discontinuous.

As an embodiment, the bits in the first bit sub-block are consecutive in the first bit block.

As an embodiment, the position of the bits in the second bit sub-block in the first bit block is discontinuous.

As an embodiment, the bits in the second bit sub-block are consecutive in the first bit block.

As an embodiment, the first bit sub-block is at the forefront of the first bit block. The first bit and the second bit are any two bits in the first bit block, the first bit before the second bit means: in the decoding order of the base station assuming the receiver, The first bit is decoded prior to the second bit.

As an embodiment, the number of bits in the first bit sub-block is a fixed constant.

As an embodiment, the number of bits in the first bit sub-block is configurable.

As an embodiment, the K candidate values respectively correspond to K types of DCI (Downlink Control Information) format.

As an embodiment, the base station assumes that the probability of the receiver erroneously coding the first bit sub-block based on the first hypothesis is not higher than a first threshold, the first hypothesis being the second bit The number of bits in the block is equal to the maximum of the K candidate values.

In one embodiment, the receiver of the first wireless signal calculates a first coding rate based on the receiver, and notifies the base station of the first coding rate, the base station is based on the first coding rate The first bit block performs the first channel coding. And the encoding rate corresponding to the first bit block is less than or equal to the first encoding rate is based on the first hypothesis, and the probability of erroneously coding the first bit sub-block is not higher than the first threshold. One of the conditions.

In one embodiment, the receiver of the first wireless signal calculates a first SNR (Signal-to-Noise Ratio) based on the receiver, and notifies the base station of the first SNR, The base station sets a transmit power of the first wireless signal based on the first SNR. Place Determining that the SNR corresponding to the first wireless signal is greater than or equal to the first SNR is one of the conditions that the probability of erroneously decoding the first bit sub-block is not higher than the first threshold based on the first hypothesis .

In one embodiment, the receiver of the first wireless signal calculates a first modulation mode based on the receiver, and notifies the base station of the first modulation mode, where the base station sets the location based on the first modulation mode. The modulation method of the first wireless signal is described. The modulation mode corresponding to the first wireless signal is more reliable than the first modulation mode, and the probability of erroneously decoding the first bit sub-block is not higher than the first on the premise of the first hypothesis. One of the conditions of the threshold.

As an embodiment, at least one of {the encoding rate corresponding to the first bit block, the modulation mode of the first wireless signal, and the transmission power of the first wireless signal} is a condition that satisfies the assumption.

As an embodiment, the first bit sub-block is a result of the encoding of the first bit packet.

As an embodiment, the first bit sub-block includes a bit in the first bit packet and a redundancy check bit corresponding to a bit in the first bit packet.

As an embodiment, the first bit sub-block includes bits in the first bit packet that are repeated X times, the X being greater than one.

As an embodiment, the bits in the first bit sub-block are used to determine other information than the first bit packet.

As a sub-embodiment of the foregoing embodiment, the second bit sub-block includes a {CIF domain, a resource allocation domain, an MCS (Modulation and Coding Status) domain, an NDI domain, a HARQ process number domain, and a TPC domain. At least one of a field indicating a parameter of the DMRS, a CRC bit}.

Specifically, according to an aspect of the present invention, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As an embodiment, the above method has the advantage of improving the transmission reliability of the first bit packet.

As an embodiment, the first encoding is used to improve the transmission reliability of the first bit packet.

As an embodiment, the first code is a CRC (Circular Redundancy Check) code.

As an embodiment, the first code is a linear block code.

As an embodiment, the first code is a convolutional code.

As an embodiment, the first code is a TBCC (Tail-biting Convolutional Code).

As an embodiment, the first bit sub-block is an output of the first code.

As an embodiment, a portion of the bits in the first bit sub-block is an output of the first code.

As an embodiment, the bits in the first bit sub-block are composed of bits in the first bit packet and the first encoded output.

As an embodiment, the output of the first code is a CRC bit corresponding to the first bit packet.

As an embodiment, the output of the first code is a PC bit corresponding to the first bit packet.

Specifically, according to an aspect of the present invention, the step A further includes the following steps:

- Step A0. Send the first message.

The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As an embodiment, the above method has the advantage of supporting more flexible configuration of information bit transmission, thereby improving transmission efficiency and reliability.

As an embodiment, the first information is semi-statically configured.

As an embodiment, the first information is UE specific.

As an embodiment, the first information includes one or more RRC (Radio Resource Control) IEs (Information Element).

As a sub-embodiment of the foregoing embodiment, a part of the RRC IEs of the multiple RRC IEs are common to a cell, and the rest of the plurality of RRC IEs are UE-specific.

As an embodiment, the first information explicitly indicates at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As an embodiment, the first information implicitly indicates at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

In an embodiment, the first information indicates a current transmission setting of the UE, and the transmission The input sets an implicit indication {at least one of the number of bits in the first bit sub-block, the first encoding, the K candidate values}.

As an embodiment, the transmission settings include multiple antenna related parameters.

As an embodiment, the transmission settings include carrier aggregation related parameters.

Step A1. Determine the number of bits in the third bit sub-block.

The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As an embodiment, the above method has the advantage that the reliability of the transmission of the first bit sub-block is further ensured.

As an embodiment, the position of the bits in the third bit sub-block in the first bit block is discontinuous.

As an embodiment, the bits in the third bit sub-block are consecutive in the first bit block.

As an embodiment, the number of bits in the third bit sub-block ensures that the probability of the receiver erroneously coding the first bit sub-block on the premise of the first hypothesis is not higher than the first threshold. The first assumption is that the number of bits in the second bit sub-block is equal to the maximum of the K candidate values.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2. The number of bits in the third bit sub-block is equal to L-L1-L2. The L, the L1, and the L2 are all positive integers, wherein the L is greater than L1+L2.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the maximum value among the K candidate values is K1, where the The number of bits in the three-bit sub-block is greater than L-L1-K1.

As an embodiment, the base station allocates P1 CCEs (Control Channel Elements) to the first bit block based on the first threshold, and bits in the codewords carried on the P1 CCEs. The quantity is the L.

As an embodiment, the number of bits in the third bit sub-block ensures that the receiver is at the base The probability of erroneously coding the first bit block is not higher than a second threshold on the premise of the second hypothesis, the second hypothesis that the first bit sub-block received according to the first hypothesis is correct Decoded and used to determine the number of bits in the second bit sub-block.

As an embodiment, the first threshold is less than the second threshold.

As an embodiment, the first threshold is equal to the second threshold.

In one embodiment, the received first bit sub-block is the same as the first bit sub-block sent by the base station (ie, the first bit sub-block is correctly decoded).

In an embodiment, the received first bit sub-block is different from the first bit sub-block sent by the base station (ie, the first bit sub-block is erroneously decoded).

As an embodiment, {UCI (Uplink Control Information) fed back by the receiver of the first wireless signal, a modulation mode of the first wireless signal, and a transmission power of the first wireless signal} At least one of is used to determine the number of bits in the third bit sub-block.

As an embodiment, the third bit sub-block includes a first frozen bit set and a second frozen bit set. The maximum of the K candidate values is used to determine the number of bits in the first set of frozen bits. The number of bits in the second bit sub-block is used to determine the number of bits in the second set of frozen bits.

As an embodiment, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2, The maximum of the K candidate values is K1. The number of bits in the first set of frozen bits is equal to L-L1-K1. The number of bits in the second set of frozen bits is equal to K1-L2. The L, the L1, the L2, and the K1 are all positive integers.

Specifically, according to an aspect of the present invention, the first encoding is based on an error-detecting code.

As an embodiment, the above method has the advantage that the error detection code can be used to detect the correctness of the indication information transmission, thereby improving the transmission reliability of the detection indication information.

As an embodiment, the error detection code is a CRC (Circular Redundancy Check) code.

As an embodiment, the error detection code is a PC (Parity Check) code.

Specifically, according to an aspect of the present invention, the first encoding is based on an error Error-correcting code.

As an embodiment, the above method has the advantage that the error correction code can correct the erroneous transmission of the indication information, thereby improving the transmission reliability of the detection indication information.

As an embodiment, the error correction code is a TBCC (Tail-biting Block Convolutional Code).

As an embodiment, the error correction code is a Turbo code.

As an embodiment, the first encoding comprises a first level encoding and a second level encoding, the output of the first level encoding being used for the input of the second level encoding. The first encoding uses an error detection code and the second level encoding uses an error correction code.

Specifically, according to an aspect of the present invention, an average channel capacity of a subchannel mapped by a bit in the first bit subblock is smaller than a subchannel mapped by a bit in the second bit subblock. Average channel capacity.

As an embodiment, the foregoing method is advantageous in that the second bit sub-block corresponds to a better sub-channel relative to the first bit sub-block, thereby improving transmission reliability of the second bit sub-block.

As an embodiment, a channel capacity of a sub-channel in which any bit in the second bit sub-block is mapped is greater than a channel capacity of a sub-channel in which any bit in the first bit sub-block is mapped.

As an embodiment, the channel capacity corresponding to the presence of at least one subchannel in the subchannel mapped by the bits in the second bit subblock is smaller than that in the subchannel mapped by the bit in the first bit subblock. a channel capacity corresponding to the at least one subchannel, an average value of channel capacities of the subchannels mapped by the bits in the second bit subblock is greater than a channel capacity of the subchannel mapped by the bits in the first bit subblock average value.

As an embodiment, the base station assumes that the decoding order of the receiver of the first wireless signal receiver is from a bit corresponding to a subchannel having a low channel capacity to a bit corresponding to a subchannel having a high channel capacity.

Specifically, according to an aspect of the present invention, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As an embodiment, the above method has the advantage that the first bit sub-block can be preempted in the decoding order, thereby improving coding efficiency.

As an embodiment, the third bit sub-block includes a first frozen bit set and a second frozen bit Node bit set. The maximum of the K candidate values is used to determine the number of bits in the first set of frozen bits. The number of bits in the second bit sub-block is used to determine the number of bits in the second set of frozen bits. The receiver performs serial channel decoding based on the first channel coding on the received first bit block: 1) using bits in the first frozen bit set as known bits, for the first The output of the subchannel in which the bit in the bit subblock is located performs serial decoding to obtain an estimated value of the first bit subblock; 2) the estimated value of the first bit subblock is used as the first encoding based The input of the decoder obtains the first bit packet; 3) the first bit packet is used to determine the number of bits in the second bit sub-block, thereby determining the second frozen bit set; The first bit packet is used to recover bits in the first bit sub-block, and bits in the second frozen bit set and bits in the first bit sub-block are used as known bits, The output of the subchannel in which the bits in the second bit sub-block are located performs serial decoding to obtain bits in the second bit sub-block (ie, recover the first bit block).

As an embodiment, the sequence of serial channel decoding based on the first channel coding is a bit corresponding to a subchannel having a low channel capacity to a bit corresponding to a subchannel having a high channel capacity, in the first bit subblock. The capacity of the subchannel corresponding to any bit is lower than the capacity of the subchannel corresponding to any bit in the second bit subblock.

As an embodiment, the capacity of the subchannel corresponding to any bit in the first frozen bit set is lower than the capacity of the subchannel corresponding to any bit in the first bit subblock, the first The capacity of the subchannel corresponding to any bit in the bit subblock is lower than the capacity of the subchannel corresponding to any bit in the second frozen bit set.

As an embodiment, the sequence of serial channel decoding based on the first channel coding is from a bit corresponding to a subchannel having a high channel capacity to a bit corresponding to a subchannel having a low channel capacity, in the first bit subblock. The capacity of the subchannel corresponding to any bit is higher than the capacity of the subchannel corresponding to any bit in the second bit subblock.

As an embodiment, the first bit block is multiplied by a polarization code based generation matrix in the first channel coding to obtain the output bit block. Any one of the first bit sub-blocks The row number of the generation matrix corresponding to the special bit is smaller than the row number of the generation matrix corresponding to any one of the bits in the second bit sub-block. The base station assumes that the decoding order of the received bit block by the receiver is in an ascending order of the row numbers of the generation matrix corresponding to the bits in the received bit block.

As an embodiment, the generator matrix is a Kronecker matrix.

As an embodiment, the generator matrix is a matrix obtained by bit flipping the row numbers of the Kronecker matrix.

Specifically, according to an aspect of the present invention, the second bit sub-block includes a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As an embodiment, the above method has the advantage that the second set of bits serves as a redundancy check for the first bit sub-block and the first bit set, thereby improving the reliability of transmission.

As an embodiment, the bits in the second bit set are CRC (Circular Redundancy Check) corresponding to the bit in the first bit sub-block and the bit in the second bit sub-block. ) bit.

As an embodiment, the bits in the second set of bits are PC (Parity Check) bits corresponding to the bits in the first bit sub-block and the bits in the second bit sub-block.

As an embodiment, the bits in the second set of bits correspond to a CRC generator polynomial, and the input of the CRC generator polynomial is a bit in the first bit sub-block and a bit in the second bit sub-block.

Specifically, according to an aspect of the present invention, the bit in the first bit packet is further used to determine a position of a bit in the second bit sub-block in the first bit block, At least one of an information format of the second bit sub-block, a polynomial corresponding to a redundancy check bit of the first bit block.

As an embodiment, the above method has the advantage that the second bit sub-block can be configured more flexibly, which saves additional signaling overhead.

As an embodiment, the bits in the first bit packet explicitly indicate the location of the bits in the second bit sub-block in the first bit block.

As an embodiment, the bits in the first bit packet implicitly indicate the location of the bits in the second bit sub-block in the first bit block.

As an embodiment, the bits in the first bit packet indicate the relative positions of the second bit sub-block and the first bit sub-block.

As an embodiment, the bits in the first bit packet explicitly indicate the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet implicitly indicate the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet indicate the number of bits in the second bit sub-block, the number of bits in the two-bit sub-block and the information in the second bit sub-block The format corresponds one by one.

As an embodiment, the bits in the first bit packet are used to partially determine the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet together with other configuration parameters determine the information format of the second bit sub-block.

As an embodiment, the bits in the first bit packet explicitly indicate a polynomial corresponding to a redundant check bit in the first bit block.

As an embodiment, the bits in the first bit packet implicitly indicate a polynomial corresponding to a redundant check bit in the first bit block.

As an embodiment, the bits in the first bit packet indicate the number of bits in the second bit sub-block, and the number of bits in the two-bit sub-block determines the first bit block The polynomial corresponding to the redundancy check bit.

Specifically, according to an aspect of the present invention, the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information. (DCI).

As an embodiment, the above method has the advantage of reducing the number of blind detections of the physical layer control channel by the UE side.

As an embodiment, the physical layer control channel is a physical layer channel that can only carry physical layer signaling.

As an embodiment, the DCI is UE specific.

As an embodiment, the physical layer control channel is a PDCCH.

As an embodiment, the physical layer control channel is an ePDCCH (enhanced PDCCH).

As an embodiment, the physical layer control channel is an sPDCCH (short PDCCH, short physical layer downlink control channel).

As an embodiment, the physical layer control channel is an NR-PDCCH (New Radio PDCCH, a new radio layer downlink control channel).

A method for use in a user equipment for channel coding, comprising the steps of:

- step A. receiving the first wireless signal;

- Step B. Perform first channel decoding.

The first channel coding corresponds to a first channel coding, the first channel coding is based on a polarization code, and a first bit block is used for the input of the first channel coding. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As an embodiment, the first channel coding is used to recover the first block of bits.

As an embodiment, the first channel coding is used to recover the second bit sub-block.

As an embodiment, the first channel coding is used to recover a portion of the bits in the second bit sub-block.

In one embodiment, the first wireless signal carries verification information corresponding to the first bit block, and the channel decoding determines whether the first bit block is correctly restored based on the verification information.

In one embodiment, the first bit block includes check information corresponding to information bits in the first bit block, and the channel decoding determines whether the first bit block is correctly restored based on the check information. .

Specifically, according to an aspect of the invention, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

- Step A0. Receive the first message.

Specifically, according to an aspect of the present invention, the step B further includes the following steps:

Step B0. Determine the number of bits in the third bit sub-block.

As an embodiment, the number of bits in the third bit sub-block ensures that the probability of the receiver erroneously coding the first bit sub-block based on the first hypothesis is not higher than the first A threshold.

As an embodiment, the number of bits in the first bit sub-block is L1. The number of bits in the second bit sub-block is L2. The number of bits in the third bit sub-block is equal to L-L1-L2. The L, the L1, and the L2 are all positive integers, wherein the L is greater than L1+L2.

Specifically, according to an aspect of the invention, the first encoding is based on an error-correcting code.

As an embodiment, the first channel decoding is serial channel decoding. The first bit sub-block is recovered earlier than the second bit sub-block.

As an embodiment, the first channel coding uses the first bit sub-block as a known bit in a subsequent decoding process after restoring the first bit sub-block.

As an embodiment, the first bit block is composed of bits in the first bit sub-block, bits in the second bit sub-block, and bits in the third bit sub-block. The third bit sub-block includes a first frozen bit set and a second frozen bit set. Of the K candidate values The maximum value is used to determine the number of bits in the first set of frozen bits. The number of bits in the second bit sub-block is used to determine the number of bits in the second set of frozen bits. The process of decoding the first channel is: 1) performing a serial translation on the output of the subchannel in which the bit in the first bit subblock is located, using the bits in the first frozen bit set as known bits a code, obtaining an estimated value of the first bit sub-block; 2) obtaining an estimated value of the first bit sub-block as an input of a decoder based on the first encoding to obtain the first bit packet; 3) Using the first bit packet for determining the number of bits in the second bit sub-block to determine the second frozen bit set; 4) using the first bit packet to recover the first bit a bit in the sub-block, the bit in the first bit sub-block and the bit in the second frozen bit set are used as known bits, and the output of the sub-channel in which the bit in the second bit sub-block is located Performing serial decoding results in bits in the second bit sub-block (ie, recovering the first bit block).

As an embodiment, the bits in the second set of bits are used to check bits in the first bit sub-block and bits in the first set to determine if the reception is correct.

As an embodiment, the check is a PC (Parity Check).

As an embodiment, the check is a CRC (Circular Redundancy Check).

Specifically, according to an aspect of the invention, the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI).

The invention discloses a base station device used for channel coding, which comprises the following modules:

a first execution module: for performing a first channel coding;

- a first transmitting module: for transmitting the first wireless signal.

Wherein the first block of bits is used for the input of the first channel coding. The first channel The code is based on a polarization code. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As an embodiment, the above base station device is characterized in that an output after the first bit packet is subjected to the first encoding is used to determine the first bit sub-block.

As an embodiment, the foregoing base station device is characterized in that the first execution module is further configured to send the first information. The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As an embodiment, the above base station device is characterized in that the first execution module is further used to determine the number of bits in the third bit sub-block. The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As an embodiment, the above base station device is characterized in that the first coding is based on an error-detecting code.

As an embodiment, the above base station device is characterized in that the first coding is based on an error-correcting code.

As an embodiment, the foregoing base station device is characterized in that an average channel capacity of a subchannel mapped by a bit in the first bit subblock is smaller than an average channel of a subchannel mapped by a bit in the second bit subblock. capacity.

As an embodiment, the above base station device is characterized in that any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As an embodiment, the foregoing base station device is characterized in that the second bit sub-block comprises a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As an embodiment, the foregoing base station device is characterized by: a ratio in the first bit packet Specially used to determine {the position of the bit in the second bit sub-block in the first bit block, the information format of the second bit sub-block, the redundancy check of the first bit block At least one of the polynomials} corresponding to the bit.

As an embodiment, the foregoing base station device is characterized in that the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI ).

The invention discloses a method used in a channel coding user equipment, which comprises the following steps:

- step A. receiving the first wireless signal;

- Step B. Perform first channel decoding.

As an embodiment, the user equipment is characterized in that the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As an embodiment, the foregoing user equipment is characterized in that the first receiving module is further configured to receive the first information. The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As an embodiment, the above user equipment is characterized in that the second execution module is further used to determine the number of bits in the third bit sub-block. The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As an embodiment, the user equipment is characterized in that the first coding is based on an error-detecting code.

As an embodiment, the above user equipment is characterized in that the first coding is based on an error-correcting code.

As an embodiment, the foregoing user equipment is characterized in that an average channel capacity of a subchannel mapped by a bit in the first bit subblock is smaller than an average channel of a subchannel mapped by a bit in the second bit subblock. capacity.

As an embodiment, the user equipment is characterized in that any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As an embodiment, the foregoing user equipment is characterized in that the second bit sub-block comprises a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As an embodiment, the user equipment is characterized in that the bits in the first bit packet are further used to determine {the position of a bit in the second bit sub-block in the first bit block, The information format of the second bit sub-block, at least one of the polynomials corresponding to the redundancy check bits of the first bit block.

As an embodiment, the foregoing user equipment is characterized in that the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI ).

As an embodiment, the present invention has the following advantages over the conventional solution:

-Using the characteristics of the serial decoding of the Polar code, the number of blind detections on the UE side is reduced by the internal indication of the code block;

- increasing the reliability of the transmission of the indication information by additional coding of the indication information;

- Support more flexible and diverse DCI formats;

- Guaranteed the reliability of DCI transmission.

DRAWINGS

Other features, objects, and advantages of the present invention will become apparent from the Detailed Description of Description

1 shows a flow chart of wireless transmission in accordance with one embodiment of the present invention;

2 shows a schematic diagram of constructing a first block of bits in accordance with one embodiment of the present invention;

FIG. 3 illustrates a first bit block and a first wireless signal according to an embodiment of the present invention. Schematic diagram of the relationship between;

Figure 4 shows a schematic diagram of a first encoding in accordance with one embodiment of the present invention;

FIG. 5 is a diagram showing a relationship between {a first bit sub-block, a first bit set in a second bit sub-block} and a second bit set in a second bit sub-block according to an embodiment of the present invention;

Figure 6 shows a schematic diagram of a first channel coding in accordance with one embodiment of the present invention;

Figure 7 shows a schematic diagram of first channel decoding in accordance with one embodiment of the present invention;

FIG. 8 is a schematic diagram showing a mapping relationship between a first bit subblock and a second bit subblock on a subchannel according to an embodiment of the present invention; FIG.

Figure 9 is a diagram showing the first bit sub-block and the second bit sub-block in decoding order, in accordance with one embodiment of the present invention;

Figure 10 is a block diagram showing the structure of a processing device for use in a base station according to an embodiment of the present invention;

Figure 11 shows a block diagram of a structure for a processing device in a user equipment in accordance with one embodiment of the present invention.

Example 1

Embodiment 1 illustrates a flow chart of wireless transmission, as shown in FIG. In Figure 1, base station N1 is a serving cell maintenance base station of UE U2. In Figure 1, the steps in block F1, block F2 and block F3 are optional, respectively.

For N1, the first information is transmitted in step S11; the number of bits in the third bit sub-block is determined in step S12; the first channel coding is performed in step S13; and the first wireless signal is transmitted in step S14.

For U2, the first information is received in step S21; the first wireless signal is received in step S22; the number of bits in the third bit sub-block is determined in step S23; the first channel decoding is performed in step S24.

In Embodiment 1, the first bit block is used by N1 for the input of the first channel coding. The first channel coding is based on a polarization code. The first channel decoding corresponds to the first channel coding. The output of the first channel code is used by N1 to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used by N1 to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block. The first bit packet, the first bit sub-block and the second bit sub-block Do not include positive integer bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As sub-embodiment 1 of embodiment 1, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As sub-embodiment 2 of embodiment 1, the steps in block F1 are selected, the first information being used to determine {the number of bits in the first bit sub-block, the first code, the K At least one of the candidate values}.

As sub-embodiment 3 of embodiment 1, block F2 is selected, the first bit block further comprising bits in a third bit sub-block, the bits in the third bit sub-block being freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As sub-embodiment 4 of the first embodiment, the first encoding is based on an error-detecting code.

As a sub-embodiment 5 of Embodiment 1, the first encoding is based on an error-correcting code.

As a sub-embodiment 6 of Embodiment 1, the average channel capacity of the subchannels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As a sub-embodiment 7 of Embodiment 1, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As a sub-embodiment 8 of Embodiment 1, the second bit sub-block includes a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 1, the bits in the first bit packet are further used to determine {the position of the bit in the second bit sub-block in the first bit block, the second At least one of an information format of the bit sub-block, a polynomial corresponding to the redundancy check bit of the first bit block.

As a sub-embodiment 10 of Embodiment 1, the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI).

As sub-embodiment 11 of embodiment 1, the steps in block F3 exist, the first bit The block also includes bits in the third bit sub-block, the bits in the third bit sub-block being freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As a sub-embodiment 12 of Embodiment 1, the first bit packet indicates a format of physical layer signaling corresponding to the first bit block.

As a sub-embodiment 13 of Embodiment 1, the first bit packet indicates the number of bits in the second bit sub-block from the K candidate values.

As sub-embodiment 14 of embodiment 1, each bit in the first bit packet appears X times in the first bit sub-block, and X is a positive integer greater than one.

As a sub-embodiment 15 of Embodiment 1, the number of bits in the first bit packet is equal to ceil(log2(K)), where ceil represents rounding up.

As a sub-invention 16 of Embodiment 1, a channel capacity of a sub-channel in which any bit in the second bit sub-block is mapped is larger than a sub-channel in which the bit in the first bit sub-block is mapped. The channel capacity of the channel.

As a sub-embodiment 17 of Embodiment 1, the subchannel index corresponding to any bit in the first bit subblock is smaller than the index of the subchannel corresponding to any bit in the second bit subblock.

The above sub-embodiments 1-11 can be arbitrarily combined without conflict.

Example 2

Embodiment 2 exemplifies a schematic diagram of constructing a first block of bits, as shown in FIG.

In Embodiment 2, the first bit block is used by the base station for input of the first channel coding, the bits in the first bit block are bits in the first bit sub-block, bits in the second bit sub-block, and The bits in the third bit sub-block are composed. The number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2. The base station calculates, according to the L, the L1, and the L2, that the number of bits in the third bit sub-block is L-L1-L2. The bits in the third bit sub-block are freeze bits. The frozen bit is a bit with a default default value. The base station constructs a Permutation Matrix P of L and the number of columns, and concatenates the first bit subblock, the second bit subblock, and the third bit subblock to obtain a length A bit sequence of L, which is multiplied by the switching matrix P to obtain the first bit block. The switching matrix means: any row or column of a matrix includes only one, and the rest is 0.

As a sub-embodiment 1 of Embodiment 2, bits in the first bit sub-block are consecutive in the first bit block.

As a sub-embodiment 2 of Embodiment 2, bits in the first bit sub-block are discontinuous in the first bit block.

As a sub-embodiment 3 of Embodiment 2, bits in the second bit sub-block are consecutive in the first bit block.

As a sub-embodiment 4 of embodiment 2, bits in the second bit sub-block are discontinuous in the first bit block.

As a sub-embodiment 5 of Embodiment 2, bits in the third bit sub-block are consecutive in the first bit block.

As a sub-embodiment 6 of Embodiment 2, bits in the third bit sub-block are discontinuous in the first bit block.

Example 3

Embodiment 3 illustrates a schematic diagram of the relationship between the first bit block and the first wireless signal, as shown in FIG.

In Embodiment 3, at the base station, the first bit block is used for input of the first channel coding module, and the output of the first channel coding module obtains the first wireless signal after passing through the post-processing module. At the UE side, the output of the first wireless signal after passing through the pre-processing module is used for input of a first channel decoding module, and the first bit block is an output of the first channel decoding module. The first channel coding module and the first channel coding module are respectively an encoding module and a decoding module based on a polarization code.

As a sub-embodiment 1 of Embodiment 3, the first wireless signal is an OFDM symbol carrying the first bit block, and the post-processing operation in the post-processing module includes a modulation mapping, a multi-antenna pre-coding, and a RE (Resource) Element, resource particle) mapping and operation of OFDM signal generation.

As a sub-embodiment 2 of Embodiment 3, the first wireless signal is an OFDM symbol carrying the first bit block, and pre-processing operations in the pre-processing module include OFDM signal demodulation, channel estimation, channel equalization, RE demapping, demodulation mapping operations.

As a sub-embodiment 3 of Embodiment 3, the output of the first channel coding is the first The result of multiplying a bit block by a Kronecker matrix.

As a sub-embodiment 4 of the third embodiment, the output of the first channel coding is a result of multiplying a bit sequence formed by bit-inversion of bit numbers in the first bit block by a Kronecker matrix.

As a sub-embodiment 5 of the third embodiment, the first channel decoding module is a SC (Successive Cancelation Decoding) decoder based on a polarization code.

As a sub-embodiment 6 of the third embodiment, the first channel decoding module is a SCL (Successive Cancellation List) decoder based on a polarization code.

As a sub-embodiment 7 of the third embodiment, the first channel decoding module is based on an SCS (Successive Cancellation Stack) decoder.

Example 4

Embodiment 4 illustrates a schematic diagram of the first encoding, as shown in FIG.

In Embodiment 4, the first encoding includes an error detection code generation module and an error correction code generation module. a first bit packet is used for input of the error detection code generating module, and an output of the error detection code generating module is used as an input of the error correction code generating module together with the first bit packet, a first bit sub-block Is the output of the error correction code generation module.

As a sub-embodiment 1 of Embodiment 4, the error detection code is a cyclic redundancy check code.

As sub-embodiment 2 of the embodiment 4, the error detection code is a parity code.

As a sub-embodiment 3 of the embodiment 4, the error correction code is a Forward Error Correction (FEC) code.

As sub-embodiment 4 of embodiment 4, the error correction code is a linear block code.

As a sub-embodiment 5 of Embodiment 4, the error correction code is a tail biting convolutional code.

As a sub-embodiment 6 of the embodiment 4, the error correction code is a turbo code.

Example 5

Embodiment 5 exemplifies a relationship between {a first bit subblock, a first bit set in a second bit subblock} and a second bit set in a second bit subblock, as shown in FIG.

In Embodiment 5, the first bit set in the first bit sub-block and the second bit sub-block is an input of a check bit generating module, and the second bit set in the second bit sub-block is the check The output of the bit generation module.

As a sub-embodiment 1 of Embodiment 5, the check bit generating module is a CRC code generator, and the second bit set is a CRC code of the first bit sub-block and the first bit set.

As a sub-embodiment 2 of Embodiment 5, the check bit generating module is a parity code generator, and the second bit set is a parity of the first bit sub-block and the first bit set code.

Example 6

Embodiment 6 illustrates a schematic diagram of the first channel coding, as shown in FIG.

In Embodiment 6, the first channel coding includes a first bit packet generation module, a first coding module, a first bit block generation module, and a polarization code generation module. The number of bits in the second bit sub-block is used for the input of the first bit packet generation module, and the output of the first bit packet generation module is the first bit packet. The first bit packet is used for input of the first encoding module, and the output of the first encoding module is a first bit sub-block. The second bit sub-block includes a first set of bits and a second set of bits. The first bit sub-block and the first bit set are used for input of the first bit block generating module, and an output of the first bit block generating module is a first bit block. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The first block of bits is used by the polarization code generating module. The output of the polarization code generating module is the output of the first channel code.

As a sub-embodiment 1 of Embodiment 6, the bits in the first bit packet are used to determine the number of bits in the second bit sub-block.

As a sub-embodiment 2 of Embodiment 6, the value of the first bit packet is equal to the number of bits in the second bit sub-block.

As a sub-embodiment 3 of Embodiment 6, the value of one bit sub-block in the first bit packet is equal to the number of bits in the second bit sub-block.

As a sub-embodiment 4 of Embodiment 6, the first encoding module is as shown in Embodiment 4.

As a sub-embodiment 5 of Embodiment 6, the first bit block generating module calculates the third bit sub-block according to the number of bits in the first bit sub-block and the number of bits in the second bit sub-block. The number of bits is then processed as shown in embodiment 2 to generate the first block of bits.

As a sub-embodiment 6 of Embodiment 6, the length of the first bit block is 2 to the power of N, The N is a positive integer.

As a sub-embodiment 7 of the embodiment 6, the check bit generating module in the fifth embodiment is included in the first bit block generating module.

Example 7

Embodiment 7 illustrates a schematic diagram of first channel decoding in accordance with one embodiment of the present invention, as shown in FIG.

In Embodiment 7, the first channel decoding includes a polarization code decoding I module, a first decoding module, a first encoding module, an information bit number determining module, a polarization code decoding II module, and a bit check module. .

In Embodiment 7, the polarization code decoding I module and the polarization code decoding II module both correspond to the polarization code generating module in Embodiment 6. The polarization code generation module is related to the length of the first bit block. The bit check module corresponds to the check bit generation module in Embodiment 5. The first bit block is composed of a bit in a first bit sub-block, a bit in a second bit sub-block, and a bit in a third bit sub-block. The bits in the third bit sub-block are freeze bits. The third bit sub-block includes a first frozen bit set and a second frozen bit set. The bits in the first bit sub-block are used to determine the number of bits in the second bit sub-block. The number of bits in the second bit sub-block is one of the K candidate values. The maximum of the K candidate values is used to determine the first frozen bit set. The number of bits in the second bit sub-block is used to determine the second set of frozen bits. The second bit sub-block includes a first set of bits and a second set of bits. The second set of bits is a check bit corresponding to a bit in the first bit sub-block and a bit in the first bit set.

In Embodiment 7, the first frozen bit set and the demodulated result of the first wireless signal are used for input of a polarization code decoding I module, and the estimated value of the first bit sub-block is the polarization The code decodes the output of the I module. An estimate of the first bit sub-block is used for an input of the first coding module, the first bit packet being an output of the first coding module. The first decoding module corresponds to the first encoding module. The first bit packet is used for input of the first encoding module, and the output of the first encoding module is the first bit sub-block. The first bit packet is also used for input of the information bit number determining module, and the output of the information bit number determining module is the number of bits in the second bit sub-block and the second frozen bit set. The first bit sub-block, the number of bits in the second bit sub-block, and the A second set of frozen bits is used for the input of the Polar Code Decoding II module, the output of which is the second bit sub-block. The first bit sub-block and the second bit sub-block are used for input of the bit check module, and the output of the bit check module is a first bit set in a second bit sub-block.

As a sub-embodiment 1 of Embodiment 7, the number of bits in the first bit block is L, the number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2, the maximum of the K candidate values is K1. The number of bits in the third bit sub-block is L-L1-L2, wherein the number of bits in the first frozen bit set is L-L1-K1, and the number of bits in the second frozen bit set It is K1-L2.

As a sub-embodiment 2 of Embodiment 7, the polarization code decoding I module and the polarization code decoding II module are based on the same polarization code generation matrix. The polarization code generation matrix is used for the polarization code generation module. The bits in the first set of frozen bits are used as known bits in the Polar Code Decoding I module. The polarization code decoding I module decodes only the output of the subchannel corresponding to the bit in the first bit subblock. The bits in the first bit sub-block are used as known bits in the Polar Code Decoding II module.

As a sub-embodiment 3 of Embodiment 7, the polarization code decoding I module and the polarization code decoding II module use an SC (Successive Cancellation) decoder.

As a sub-embodiment 4 of Embodiment 7, the first encoding module is as shown in Embodiment 4.

As a sub-embodiment 5 of Embodiment 7, the second bit set is a CRC check bit corresponding to a bit in the first bit sub-block and a bit in the first bit set.

Example 8

Embodiment 8 exemplifies a mapping relationship between a first bit sub-block and a second bit sub-block on a sub-channel, as shown in FIG.

The number of bits in the first bit sub-block is L1, and the number of bits in the second bit sub-block is L2. The bits in the first bit sub-block are in one-to-one correspondence with L1 sub-channels, and the bits in the second bit sub-block are in one-to-one correspondence with L2 sub-channels. The channel capacity corresponding to any one of the L1 subchannels is higher than the channel capacity corresponding to any one of the L2 subchannels.

Example 9

Embodiment 9 exemplifies a first bit sub-block and a second bit sub-block in a decoding order, as shown in FIG.

In Embodiment 9, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block

As a sub-embodiment 1 of Embodiment 9, an SC decoder is used for the decoding.

As a sub-embodiment 2 of Embodiment 9, an SCL decoder is used for the decoding.

As a sub-embodiment 3 of Embodiment 9, an SCS decoder is used for the decoding.

Example 10

Embodiment 10 exemplifies a structural block diagram of a processing device used in a base station, as shown in FIG. In FIG. 10, the base station apparatus 200 is mainly composed of a first execution module 201 and a first transmission module 202.

In the embodiment 10, the first execution module 201 is configured to perform first channel coding, and the first sending module 202 is configured to send the first wireless signal.

In Embodiment 10, a first bit block is used for the input of the first channel coding. The first channel coding is based on a polarization code. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The number of bits in the second bit sub-block is related to the first bit packet. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As sub-embodiment 1 of embodiment 10, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As a sub-embodiment 2 of the embodiment 10, the first execution module 201 is further configured to send the first information. The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As a sub-embodiment 3 of embodiment 10, the first execution module 201 is also used to determine the number of bits in the third bit sub-block. The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The K candidate values The maximum value in the middle is related to the number of bits in the third bit sub-block.

As sub-embodiment 4 of embodiment 10, the first encoding is based on an error-detecting code.

As a sub-embodiment 5 of embodiment 10, the first encoding is based on an error-correcting code.

As a sub-embodiment 6 of the embodiment 10, the average channel capacity of the subchannels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As a sub-embodiment 7 of embodiment 10, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As a sub-embodiment 8 of embodiment 10, the second bit sub-block includes a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 10, the bits in the first bit packet are further used to determine {the position of the bit in the second bit sub-block in the first bit block, the second At least one of an information format of the bit sub-block, a polynomial corresponding to the redundancy check bit of the first bit block.

As a sub-embodiment 10 of embodiment 10, the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI).

Example 11

Embodiment 11 exemplifies a structural block diagram of a processing device for use in a user equipment, as shown in FIG. In FIG. 10, the user device 300 is mainly composed of a first receiving module 301 and a second executing module 302.

In Embodiment 11, the first receiving module 301 is configured to receive the first wireless signal; and the second executing module 302 is configured to perform the first channel decoding.

In Embodiment 11, the first channel coding corresponds to a first channel coding, the first channel coding is based on a polarization code, and a first bit block is used for the input of the first channel coding. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used Generating the first bit sub-block. The number of bits in the second bit sub-block is related to the first bit packet. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.

As sub-embodiment 1 of embodiment 11, the output of the first bit packet after the first encoding is used to determine the first bit sub-block.

As a sub-embodiment 2 of the embodiment 11, the first receiving module 301 is further configured to receive the first information. The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.

As a sub-embodiment 3 of embodiment 11, the second execution module 302 is also used to determine the number of bits in the third bit sub-block. The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.

As sub-embodiment 4 of embodiment 11, the first encoding is based on an error-detecting code.

As sub-embodiment 5 of embodiment 11, the first encoding is based on an error-correcting code.

As a sub-embodiment 6 of Embodiment 11, the average channel capacity of the subchannels mapped by the bits in the first bit sub-block is smaller than the average channel capacity of the sub-channels mapped by the bits in the second bit sub-block.

As a sub-embodiment 7 of embodiment 11, any bit in the first bit sub-block is decoded before any bit in the second bit sub-block.

As a sub-embodiment 8 of embodiment 11, the second bit sub-block includes a first bit set and a second bit set. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.

As sub-embodiment 9 of embodiment 11, the bits in the first bit packet are further used to determine {the position of the bit in the second bit sub-block in the first bit block, the second At least one of an information format of the bit sub-block, a polynomial corresponding to the redundancy check bit of the first bit block.

As a sub-embodiment 10 of Embodiment 11, the first wireless signal is in a physical layer control channel. Up-transmitting, or the first bit sub-block and the second bit sub-block belong to the same downlink control information (DCI).

One of ordinary skill in the art can appreciate that all or part of the above steps can be completed by a program to instruct related hardware, and the program can be stored in a computer readable storage medium such as a read only memory, a hard disk or an optical disk. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module unit in the above embodiment may be implemented in hardware form or in the form of a software function module. The application is not limited to any specific combination of software and hardware. The UE or the terminal in the present invention includes, but is not limited to, a wireless communication device such as a mobile phone, a tablet computer, a notebook, a network card, an NB-IOT terminal, and an eMTC terminal. The base station or system equipment in the present invention includes, but is not limited to, a macro communication base station, a micro cell base station, a home base station, a relay base station, and the like.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A method for use in a base station for channel coding, comprising the steps of:

- Step A. Performing a first channel coding;

- Step B. Send the first wireless signal.

Wherein the first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.
The method of claim 1 wherein the output of the first bit packet after the first encoding is used to determine the first bit sub-block.
The method according to claim 1, wherein the step A further comprises the following steps:

- Step A0. Send the first message.

The first information is used to determine at least one of {the number of bits in the first bit sub-block, the first code, the K candidate values}.
The method according to any one of claims 1-3, wherein the step A further comprises the following steps:

Step A1. Determine the number of bits in the third bit sub-block.

The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.
The method of claim 2-4, wherein the first encoding is based on an error-detecting code; or the first encoding is based on an error-correcting code.
The method according to claim 1-5, wherein an average channel capacity of the subchannels mapped by the bits in the first bit subblock is smaller than a bit in the second bit subblock The average channel capacity of the mapped subchannels; or any bits in the first bit subblock are decoded before any of the second bit subblocks.
The method of claims 1-6, wherein the second bit sub-block comprises a first set of bits and a second set of bits. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.
The method according to any of claims 1-7, wherein the bits in the first bit packet are further used to determine {the position of the bit in the second bit sub-block in the first bit block And an information format of the second bit sub-block, at least one of a polynomial corresponding to a redundancy check bit of the first bit block.
The method according to any one of claims 1-8, wherein the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to a same downlink control Information (DCI).
A method for use in a channel coding user equipment, comprising the steps of:

- step A. receiving the first wireless signal;

- Step B. Perform first channel decoding.

The first channel coding corresponds to a first channel coding, the first channel coding is based on a polarization code, and a first bit block is used for the input of the first channel coding. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.
The method of claim 10 wherein the output of the first bit packet after the first encoding is used to determine the first bit sub-block.
The method according to claim 10, wherein the step A further comprises the following steps:

- Step A0. Receive the first message.

Wherein the first information is used to determine {the number of bits in the first bit sub-block, At least one of the first code, the K candidate values}.
The method according to any one of claims 10-12, wherein the step B further comprises the following steps:

Step B0. Determine the number of bits in the third bit sub-block.

The first bit block further includes bits in the third bit sub-block, and the bits in the third bit sub-block are freeze bits. The maximum of the K candidate values is related to the number of bits in the third bit sub-block.
The method according to claims 11-13, characterized in that the first encoding is based on an error-detecting code; or the first encoding is based on an error-correcting code.
The method according to any of claims 10-14, wherein the average channel capacity of the subchannels mapped by the bits in the first bit sub-block is smaller than the sub-channel mapped by the bits in the second bit sub-block Average channel capacity; or any bit in the first bit sub-block is decoded before any of the second bit sub-blocks.
The method of claims 10-15, wherein the second bit sub-block comprises a first set of bits and a second set of bits. The bits in the first bit sub-block and the bits in the first bit set are used to generate the second set of bits.
The method according to claims 10-16, characterized in that the bits in the first bit packet are further used to determine {the position of the bit in the second bit sub-block in the first bit block And an information format of the second bit sub-block, at least one of a polynomial corresponding to a redundancy check bit of the first bit block.
The method according to any one of claims 10-17, wherein the first wireless signal is transmitted on a physical layer control channel, or the first bit sub-block and the second bit sub-block belong to the same downlink control Information (DCI).
A base station device used for channel coding, which includes the following modules:

a first execution module: for performing a first channel coding;

- a first transmitting module: for transmitting the first wireless signal.

Wherein the first block of bits is used for the input of the first channel coding. The first channel coding is based on a polarization code. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet and the The number of bits in the second bit sub-block is related, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.
A user equipment used for channel coding, which includes the following modules:

a first receiving module: configured to receive the first wireless signal;

a second execution module: for performing first channel decoding;

The first channel coding corresponds to a first channel coding, the first channel coding is based on a polarization code, and a first bit block is used for the input of the first channel coding. The first channel encoded output is used to generate the first wireless signal. The first bit block includes bits in the first bit sub-block and bits in the second bit sub-block. The bits in the first bit packet are used to generate the first bit sub-block. The first bit packet is related to the number of bits in the second bit sub-block, or the first bit packet is related to the number of bits in the first bit block. The first bit packet, the first bit sub-block and the second bit sub-block respectively comprise a positive integer number of bits. The number of bits in the second bit sub-block is one of the K candidate values. The candidate value is a positive integer and the K is a positive integer greater than one. The number of bits in the first bit sub-block is greater than the number of bits in the first bit packet.