CN109950252B - Manufacturing method of array substrate, display screen and display equipment - Google Patents
Manufacturing method of array substrate, display screen and display equipment Download PDFInfo
- Publication number
- CN109950252B CN109950252B CN201910138428.5A CN201910138428A CN109950252B CN 109950252 B CN109950252 B CN 109950252B CN 201910138428 A CN201910138428 A CN 201910138428A CN 109950252 B CN109950252 B CN 109950252B
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating material
- preparing
- array substrate
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a manufacturing method of an array substrate, the array substrate, a display screen and display equipment, wherein the method comprises the following steps: preparing an active material on a substrate, and imaging the active material through a first mask plate to form an active layer; preparing a first insulating material on the active layer, and performing weak exposure on the first insulating material by multiplexing a first mask plate to form a gate insulating layer; preparing a first conductive material on the grid insulating layer, and imaging the first conductive material through a second mask plate to form a grid layer; and preparing a second insulating material on the grid layer, and performing weak exposure on the second insulating material by multiplexing a second mask plate to form an interlayer insulating layer. The method comprises the steps of forming a gate insulation layer covering the upper surface and the side wall of an active layer by multiplexing a first mask plate; forming an interlayer insulating layer covering the upper surface and the side wall of the gate layer by multiplexing a second mask plate; the grid insulating layer and the interlayer insulating layer only cover necessary areas, so that the inorganic film layer is removed to the maximum extent, and the integral bending property of the array substrate is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate, the array substrate, a display screen and display equipment.
Background
The flexible AMOLED display adopts an LTPS (low temperature polysilicon process) technology to prepare the array substrate, and the conventional process is a 9mask process as follows: active layer (PSI) -gate routing layer (M1) -capacitor plate layer (M2) -via layer (ILD) -source drain routing layer (M3) -Planarization Layer (PLA) -Anode layer (Anode) -Pixel Definition Layer (PDL) -support post layer (SPC).
The folded display is one of the applications of the flexible AMOLED display, and this technique requires the display area (AA area) to be bent outward (inward). However, the inventors have found that the bending performance of the flexible AMOLED display is poor.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor bending performance of the flexible AMOLED display in the prior art.
Therefore, the invention provides the following technical scheme:
the invention provides a manufacturing method of an array substrate, which comprises the following steps: preparing an active material on a substrate, and patterning the active material through a first mask plate to form an active layer; preparing a first insulating material on the active layer, and performing weak exposure on the first insulating material by multiplexing the first mask plate to form a gate insulating layer; preparing a first conductive material on the grid insulating layer, and patterning the first conductive material through a second mask plate to form a grid layer; and preparing a second insulating material on the grid layer, and performing weak exposure on the second insulating material by multiplexing a second mask plate to form an interlayer insulating layer. The method comprises the steps of forming a gate insulation layer covering the upper surface and the side wall of an active layer by multiplexing a first mask plate; forming an interlayer insulating layer covering the upper surface and the side wall of the gate layer by multiplexing a second mask plate; the grid insulating layer and the interlayer insulating layer only cover necessary areas, so that the inorganic film layer is removed to the maximum extent, and the integral bending property of the array substrate is improved.
In one embodiment, before the step of preparing the active material on the substrate, the method further includes: a third insulating material is prepared on the substrate.
In one embodiment, the step of preparing a first insulating material on the active layer and performing weak exposure on the first insulating material by multiplexing the first mask to form a gate insulating layer includes: and preparing a first insulating material on the active layer, and performing weak exposure on the first insulating material and the third insulating material by multiplexing the first mask plate to form a gate insulating layer and a buffer layer. According to the manufacturing method, the first insulating material and the third insulating material on the unnecessary area are removed simultaneously by multiplexing the first mask plate, so that the inorganic film layers are removed as much as possible, and the flexibility of the array substrate is improved.
In one embodiment, after the step of preparing the third insulating material on the substrate, the method further includes: a fourth insulating material is prepared on the third insulating material.
In one embodiment, the step of preparing a first insulating material on the active layer and performing weak exposure on the first insulating material by multiplexing the first mask to form a gate insulating layer includes: preparing a first insulating material on the active layer, and performing weak exposure on the first insulating material, the fourth insulating material and the third insulating material by multiplexing the first mask plate to form a gate insulating layer, a shielding layer and a buffer layer. According to the manufacturing method, the first insulating material, the fourth insulating material and the third insulating material on the unnecessary area are removed simultaneously by multiplexing the first mask plate, so that the inorganic film layers are removed as much as possible, and the bending property of the array substrate is improved.
In one embodiment, the method further comprises the following steps: preparing a second conductive material on the substrate, and imaging the second conductive material through a third mask plate to form a first capacitor plate; preparing a fifth insulating material on the first capacitor plate, and performing weak exposure on the fifth insulating material by multiplexing the third mask plate to form a capacitor insulating layer; and forming a second capacitor plate on the capacitor insulating layer. According to the manufacturing method, the fifth insulating material on the non-necessary area is removed by multiplexing the third mask plate, so that the capacitor insulating layer is positioned on the upper surface and the side wall of the first capacitor plate, the capacitor insulating layer is not covered on other areas, the inorganic film layer is removed as much as possible, and the flexibility of the array substrate is improved.
In one embodiment, the second conductive material is the same as the first conductive material, the third mask is the same as the second mask, and the first capacitor plate and the gate layer are formed in the same process step. Therefore, mask plates can be saved, the process flow can be reduced, and the production cost can be reduced.
In a second aspect of the present invention, an array substrate is provided, which is prepared by the preparation method according to any one of the first aspect of the present invention.
In a third aspect of the invention, a display screen is provided, which includes the array substrate according to the second aspect of the invention.
In a fourth aspect of the invention, there is provided a display device comprising a display screen according to the third aspect of the invention.
The technical scheme of the invention has the following advantages:
the manufacturing method of the array substrate provided by the invention comprises the following steps: preparing an active material on a substrate, and patterning the active material through a first mask plate to form an active layer; preparing a first insulating material on the active layer, and performing weak exposure on the first insulating material by multiplexing the first mask plate to form a gate insulating layer; preparing a first conductive material on the grid insulating layer, and patterning the first conductive material through a second mask plate to form a grid layer; and preparing a second insulating material on the grid layer, and performing weak exposure on the second insulating material by multiplexing a second mask plate to form an interlayer insulating layer. According to the manufacturing method of the array substrate, the first insulating material is patterned by multiplexing the first mask plate for forming the active layer, and the grid insulating layer covering the upper surface and the side wall of the active layer is formed; patterning a second insulating material by multiplexing a second mask plate for forming a gate layer to form an interlayer insulating layer covering the upper surface and the side wall of the gate layer; the grid insulating layer and the interlayer insulating layer only cover necessary areas, the inorganic film layer on the substrate is removed to the maximum extent, the inorganic film layer is reduced as much as possible on the basis of not increasing the preparation cost, and the integral bending property of the array substrate is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart illustrating a specific example of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating another specific example of a method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 3 is a flow chart of another embodiment of a method for fabricating an array substrate according to an embodiment of the present invention;
FIG. 4 is a flow chart of another specific example of a method for fabricating an array substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an exemplary embodiment of an array substrate according to the present invention;
fig. 6 is a schematic view showing another specific example of the array substrate in the embodiment of the present invention;
fig. 7 is a schematic view of another specific example of the array substrate in the embodiment of the present invention.
Reference numerals:
1. a substrate; 2. a buffer layer; 3. a shielding layer; 4. an active layer; 5. a gate insulating layer; 6. a gate layer; 7. a first capacitor plate; 8. a capacitor insulating layer; 9. a second capacitor plate; 10. an interlayer insulating layer; 11. and a source drain layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As described in the background art, the flexible AMOLED display in the prior art has poor bending performance, and the inventors have studied and found that the main reason for the problem is that the array substrate of the AMOLED display is stressed during bending and is prone to crack, and especially, the inorganic film layer (such as SiNx, SiOx) and the like makes the bending performance of the substrate poor, thereby causing display failure.
The present embodiment provides a method for manufacturing an array substrate, as shown in fig. 1, including the following steps S1-S4.
Step S1: an active material is prepared on a substrate 1, and an active layer 4 is formed by patterning the active material through a first mask. Specifically, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process may be employed to prepare the active material, which covers the entire substrate 1; of course, in other embodiments, the active material may be formed by other methods in the prior art, which is not limited in this embodiment. After the active material is formed, the active material is patterned through a first mask plate to form an active layer, and the first mask plate can be specifically a PSI (PSI mask).
In an embodiment, the substrate 1 may be a flexible substrate or a rigid substrate, and may be arranged as needed. Specifically, the flexible substrate may be a Polyester Imide (PI) substrate, and the flexible substrate made of the polyester imide material is the Polyester Imide (PI) substrate; of course, in other embodiments, other flexible materials known in the art, such as a PET substrate made of plastic, may be used, as appropriate.
In one embodiment, the substrate 1 may be a single layer substrate; it may be a laminated substrate composed of two or more layers. When the substrate 1 is formed by multiple layers, an insulating material may be filled between two adjacent layers, and the insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride, and in other alternative embodiments, the insulating material may also be another inorganic insulating material in the prior art, which is not limited in this embodiment.
In an embodiment, the active material may be polysilicon, amorphous silicon, or monocrystalline silicon, and may be reasonably set according to actual needs, which is not limited in this embodiment.
Step S2: a first insulating material is prepared on the active layer 4, and the gate insulating layer 5 is formed by weakly exposing the first insulating material by multiplexing a first mask.
In an embodiment, the first insulating material may be formed by a chemical vapor deposition method, but the first insulating material may also be formed by other methods in the prior art, which is not limited in this embodiment. Specifically, the first insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride; in other alternative embodiments, the first insulating material may be made of other inorganic insulating materials in the prior art, which is not limited in this embodiment.
Specifically, after the first insulating material is prepared, the first insulating material covers the whole substrate, and the first insulating material is subjected to weak exposure by multiplexing the first mask plate, namely the PSI mask used in the process of preparing the active layer (PSI) is adopted, so that a new mask plate is not needed to be added, and the production cost is reduced. For example, a PSI mask prepared by a positive photoresist is taken as an example to explain, a light shielding pattern of the PSI mask is determined according to an actually required active layer, the first insulating material on other regions except for a covering region of the active layer can be removed by using the PSI mask to perform weak exposure in the process of removing the first insulating material, the weak exposure is to reduce the exposure, so that the first insulating material covering the sidewall of the active layer is not removed, the first insulating material on the sidewall of the active layer is remained, and the patterned first insulating material can well cover the upper surface and all the sidewalls of the active layer, so that the first insulating material can be removed to the maximum extent, only the first insulating material on a necessary region is remained, so that the covering area of the first insulating material is reduced, thereby reducing the covering area of an inorganic layer and improving the flexibility of the array substrate.
Step S3: a first conductive material is prepared on the gate insulating layer 5, and the gate electrode layer 6 is formed by patterning the first conductive material through a second mask. Specifically, a first conductive material covering the entire substrate may be prepared on the gate insulating layer 5 by sputtering, and the first conductive material may be patterned by using a second mask to form a gate layer, where the second mask may be an M1 mask. Of course, other methods in the prior art may be used to form the gate layer, which is not limited in this embodiment.
In one embodiment, the first conductive material may be a metal material; of course, in other embodiments, other conductive materials in the prior art can be used, and the conductive materials can be reasonably arranged according to needs.
Step S4: a second insulating material is prepared on the gate electrode layer 6, and the second insulating material is exposed weakly by multiplexing a second mask plate to form an interlayer insulating layer 10. Specifically, the second insulating material covering the entire substrate 1 is formed on the gate layer 6, and the entire surface of the second insulating material may be formed by chemical vapor deposition, or other methods in the prior art may be used, which is not limited in this embodiment. The second insulating material can be inorganic insulating materials such as silicon oxide or silicon nitride; of course, in other alternative embodiments, the second insulating material may be made of other inorganic insulating materials in the prior art, and this embodiment is not limited thereto.
Specifically, after the second insulating material is prepared, the second insulating material covers the whole substrate 1, and the second insulating material is subjected to weak exposure by multiplexing a second mask, that is, the M1mask used in the process of preparing the gate layer (M1) is adopted, so that a new mask is not required to be added, and the production cost is reduced. For example, an M1mask prepared by a positive photoresist is taken as an example to explain, a light shielding pattern of the M1mask is determined according to an actually required gate layer, the M1mask is used for weak exposure in the process of removing the second insulating material, so that the second insulating material on other regions except for a gate layer covering region can be removed, the weak exposure is to reduce the exposure, so that the second insulating material covering the side wall of the gate layer is not removed, the second insulating material on the side wall of the gate layer is reserved, and the patterned second insulating material can well cover the upper surface and all the side walls of the gate layer, so that the second insulating material can be removed to the maximum extent, only the second insulating material on a necessary region is reserved, the covering area of the second insulating material is reduced, the covering area of an inorganic layer is reduced, and the flexibility of the array substrate is improved.
According to the manufacturing method of the array substrate, the first insulating material is patterned by multiplexing the first mask plate for forming the active layer, and the grid insulating layer covering the upper surface and the side wall of the active layer is formed; patterning a second insulating material by multiplexing a second mask plate for forming a gate layer to form an interlayer insulating layer covering the upper surface and the side wall of the gate layer; the grid insulating layer and the interlayer insulating layer only cover necessary areas, the inorganic film layer on the substrate is removed to the maximum extent, the inorganic film layer is reduced as much as possible on the basis of not increasing the preparation cost, and the integral bending property of the array substrate is improved.
In an embodiment, as shown in fig. 2, before the step of preparing the active material on the substrate 1 in step S1, a step S5 is further included.
Step S5: a third insulating material is prepared on the substrate 1. Specifically, for simplification of the manufacturing process, the third insulating material covering the entire substrate is usually prepared on the substrate 1, for example, the third insulating material covering the entire substrate is prepared by using a chemical vapor deposition method, and of course, the third insulating material covering the substrate may also be formed by using other methods in the prior art, which is not limited in this embodiment.
In one embodiment, the third insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride. Of course, in other alternative embodiments, the third insulating material may be made of other inorganic insulating materials in the prior art, and this embodiment is not limited thereto.
After preparing the third insulating material on the substrate 1, the step S2 of preparing the first insulating material on the active layer 4 and performing the weak exposure on the first insulating material by multiplexing the first mask to form the gate insulating layer 5 includes: and preparing a first insulating material on the active layer 4, and weakly exposing the first insulating material and the third insulating material by multiplexing a first mask plate to form a gate insulating layer 5 and a buffer layer 2.
Specifically, the first insulating material and the third insulating material are simultaneously subjected to weak exposure by multiplexing the first mask plate, and a gate insulating layer 5 covering the upper surface and the side wall of the active layer and a buffer layer 2 located in the orthographic projection area of the gate insulating layer 5 on the substrate 1 are formed. The buffer layer 2 prevents impurities in the substrate 1 from diffusing into the active layer, and also plays a role in isolating water and oxygen.
According to the manufacturing method of the array substrate, the first insulating material and the third insulating material on the unnecessary area are removed simultaneously by multiplexing the first mask plate, so that the inorganic film layers are removed as much as possible, and the flexibility of the array substrate is improved.
In an embodiment, as shown in fig. 3, after the step of preparing the third insulating material on the substrate 1 in step S3, a step S6 is further included.
Step S6: a fourth insulating material is prepared on the third insulating material. Specifically, the fourth insulating material covering the entire substrate is prepared on the third insulating material, for example, the fourth insulating material covering the entire substrate is prepared by using a chemical vapor deposition method, and of course, the fourth insulating material covering the substrate may also be formed by using other methods in the prior art, which is not limited in this embodiment.
In one embodiment, the fourth insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride. Of course, in other alternative embodiments, the fourth insulating material may also be made of other inorganic insulating materials in the prior art, and this embodiment is not limited thereto.
After preparing the fourth insulating material on the third insulating material, the step S2 of preparing the first insulating material on the active layer 4, and performing weak exposure on the first insulating material by multiplexing the first mask to form the gate insulating layer 5 includes the steps of: preparing a first insulating material on the active layer 4, and performing weak exposure on the first insulating material, the fourth insulating material and the third insulating material by multiplexing a first mask plate to form a gate insulating layer 5, a shielding layer 3 and a buffer layer 2.
Specifically, the first insulating material, the fourth insulating material and the third insulating material are simultaneously subjected to weak exposure by multiplexing a first mask plate, so that a gate insulating layer 5 covering the upper surface and the side wall of the active layer, and a shielding layer 3 and a buffer layer 2 which are located in the orthographic projection area of the gate insulating layer 5 on the substrate 1 are formed. The shielding layer arranged between the buffer layer and the active layer can isolate oxygen and water, and the display effect of the array substrate is improved.
According to the manufacturing method of the array substrate, the first insulating material, the fourth insulating material and the third insulating material on the unnecessary area are removed simultaneously by multiplexing the first mask plate, so that the inorganic film layers are removed as much as possible, and the flexibility of the array substrate is improved.
In addition to the method for manufacturing the array substrate, as shown in FIG. 4, the method further includes steps S7-S9.
Step S7: and preparing a second conductive material on the substrate 1, and patterning the second conductive material through a third mask plate to form a first capacitor plate 7.
In one embodiment, the second conductive material covering the entire substrate may be prepared on the substrate by sputtering, and the first capacitor plate may be formed by patterning the second conductive material with a third mask. Of course, other methods in the prior art may be used to form the first capacitor plate, which is not limited in this embodiment.
In one embodiment, the second conductive material may be a metal material; of course, in other embodiments, other conductive materials in the prior art can be used, and the conductive materials can be reasonably arranged according to needs.
Step S8: and preparing a fifth insulating material on the first capacitor plate 7, and weakly exposing the fifth insulating material by multiplexing a third mask plate to form a capacitor insulating layer 8.
Specifically, the fifth insulating material covering the entire substrate 1 is formed on the first capacitor plate 7, and the entire surface of the fifth insulating material may be formed by a chemical vapor deposition method, or of course, the fifth insulating material may be formed by other methods in the prior art, which is not limited in this embodiment. The fifth insulating material can be inorganic insulating materials such as silicon oxide or silicon nitride; of course, in other alternative embodiments, the fifth insulating material may also be made of other inorganic insulating materials in the prior art, and this embodiment is not limited thereto.
Specifically, after the fifth insulating material is prepared, the fifth insulating material covers the whole substrate 1, and the fifth insulating material is subjected to weak exposure by multiplexing the third mask plate, namely the mask plate used in the process of preparing the first capacitor plate is adopted, so that a new mask plate is not needed to be added, and the production cost is reduced. For example, the shading pattern of the third mask plate is determined according to the actually required first capacitor plate, the fifth insulating material on other areas except the coverage area of the first capacitor plate can be removed by performing weak exposure on the third mask plate in the process of removing the fifth insulating material, the weak exposure is to reduce the exposure amount, so that the fifth insulating material covered on the side wall of the first capacitor plate is not removed, the fifth insulating material on the side wall of the first capacitor plate is reserved, the patterned fifth insulating material can well cover the upper surface and each side wall of the first capacitor plate, the fifth insulating material can be removed to the maximum extent, only the fifth insulating material on a necessary area is reserved, the coverage area of the fifth insulating material is reduced, the coverage area of an inorganic layer is reduced, and the bending property of the array substrate is improved.
Step S9: a second capacitor plate 9 is formed on the capacitor insulating layer 8. Specifically, a third conductive material is formed on the capacitor insulating layer 8 covering the entire substrate 1, and the third conductive material is patterned to form a second capacitor plate.
According to the manufacturing method of the array substrate, the fifth insulating material on the non-necessary area is removed by multiplexing the third mask plate, so that the capacitor insulating layer is positioned on the upper surface and the side wall of the first capacitor plate, the capacitor insulating layer is not covered on other areas, the inorganic film layer is removed as much as possible, and the bending property of the array substrate is improved.
In one embodiment, the second conductive material is the same as the first conductive material, the third mask is the same as the second mask, and the first capacitor plate 7 and the gate layer 6 are formed in the same process step.
When the capacitor needs to be manufactured on the array substrate, in order to save the process flow, the first capacitor plate of the capacitor can change the pattern of the M1mask according to the required capacitor while manufacturing the transistor grid, and the grid layer and the first capacitor plate of the capacitor are obtained after exposure. Therefore, mask plates can be saved, the process flow can be reduced, and the production cost can be reduced.
Specifically, a first conductive material covering the entire substrate 1 is formed on the substrate 1, and the first capacitor plate 7 and the gate electrode layer 6 are simultaneously formed by patterning the first conductive material through a second mask.
On the basis of the method for manufacturing the array substrate, the method further includes step S10.
Step S10: source-drain layers 11 are formed on the substrate 1. The source and drain layers may be fabricated by any method in the prior art, which is not limited in this embodiment.
When the light emitting device is required to be prepared on the flexible display substrate, after the step S10, the step S11 is further included.
Step S11: a planarization layer, an anode layer, a pixel defining layer, and a support post layer are formed on the source-drain layer 11. The above layers can be prepared by any method known in the art, and this example is not intended to limit the scope of the present invention.
According to the manufacturing method of the array substrate, the existence of the inorganic film layer in the array substrate is reduced to the greatest extent in a mode of multiplexing the mask plate, so that the bending performance of the array substrate is improved.
The embodiment of the invention also provides an array substrate which is prepared by adopting the preparation method in any one of the embodiments of the invention. The coverage area of the inorganic film layer in the array substrate prepared by the method is greatly reduced, and the bending property of the array substrate is improved.
Fig. 5 is a schematic diagram of a specific example of an array substrate in an embodiment of the present invention, and as shown in fig. 5, the array substrate includes, from bottom to top, a substrate 1, a buffer layer 2, an active layer 4, a gate insulating layer 5, a gate layer 6, an interlayer insulating layer 10, and a source/drain layer 11 that are sequentially stacked; the gate insulating layer 5 covers only the active layer 4; the buffer layer 2 is located only below the active layer 4; the interlayer insulating layer 10 covers only the gate layer 6.
The buffer layer in the array substrate is only positioned below the active layer, the gate insulating layer only covers the active layer, and the interlayer insulating layer only covers the gate layer, so that the buffer layer, the gate insulating layer and the interlayer insulating layer can reduce the existence of the redundant inorganic film layers (the buffer layer, the gate insulating layer and the interlayer insulating layer) in the array substrate to the greatest extent from the aspects of substrate design and process under the condition that the overall function is not influenced, and the bending performance of the flexible display substrate is improved.
Fig. 6 is a schematic diagram of another specific example of the array substrate in the embodiment of the present invention, and as shown in fig. 6, the array substrate includes a capacitor, and the capacitor includes a first capacitor plate 7, a capacitor insulating layer 8, and a second capacitor plate 9. The array substrate is covered with the inorganic film layer as little as possible, so that the buffer layer and the shielding layer are not covered outside the position of the substrate for manufacturing the TFT, and when the capacitor is arranged outside the TFT, the capacitor is directly arranged on the substrate. Of course, in other embodiments, the capacitor may also be disposed on the TFT tube, as shown in fig. 7.
The embodiment of the invention also provides a display screen which comprises the array substrate in the embodiment.
The embodiment of the invention also provides display equipment which comprises the display screen in the embodiment. The display device can be any device with a display function, such as a mobile phone, a tablet, a palm computer, an ipod, a digital camera, a navigator and the like.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
preparing an active material on a substrate (1), and patterning the active material through a first mask plate to form an active layer (4);
preparing a first insulating material on the active layer (4), and weakly exposing the first insulating material by multiplexing the first mask plate to form a gate insulating layer (5) only covering the upper surface and the side wall of the active layer (4);
preparing a first conductive material on the grid insulating layer (5), and patterning the first conductive material through a second mask plate to form a grid layer (6);
and preparing a second insulating material on the gate electrode layer (6), and weakly exposing the second insulating material by multiplexing a second mask plate to form an interlayer insulating layer (10) only covering the upper surface and the side wall of the gate electrode layer (6).
2. The method for manufacturing the array substrate according to claim 1, wherein the step of preparing the active material on the substrate (1) is preceded by the steps of:
-preparing a third insulating material on said substrate (1).
3. The method for manufacturing the array substrate according to claim 2, wherein the step of preparing a first insulating material on the active layer (4) and weakly exposing the first insulating material by multiplexing the first mask to form a gate insulating layer (5) comprises:
and preparing a first insulating material on the active layer (4), and weakly exposing the first insulating material and the third insulating material by multiplexing the first mask plate to form a gate insulating layer (5) and a buffer layer (2).
4. The method for manufacturing the array substrate according to claim 2, wherein after the step of preparing the third insulating material on the substrate (1), the method further comprises:
a fourth insulating material is prepared on the third insulating material.
5. The method for manufacturing the array substrate according to claim 4, wherein the step of preparing a first insulating material on the active layer (4) and weakly exposing the first insulating material by multiplexing the first mask to form a gate insulating layer (5) comprises:
preparing a first insulating material on the active layer (4), and weakly exposing the first insulating material, the fourth insulating material and the third insulating material by multiplexing the first mask plate to form a gate insulating layer (5), a shielding layer (3) and a buffer layer (2).
6. The method for manufacturing the array substrate according to any one of claims 1 to 5, further comprising:
preparing a second conductive material on the substrate (1), and patterning the second conductive material through a third mask plate to form a first capacitor plate (7);
preparing a fifth insulating material on the first capacitor plate (7), and weakly exposing the fifth insulating material by multiplexing the third mask plate to form a capacitor insulating layer (8);
and forming a second capacitor plate (9) on the capacitor insulating layer (8).
7. The method for manufacturing the array substrate according to claim 6, wherein the second conductive material is the same as the first conductive material, the third mask is the same as the second mask, and the first capacitor plate (7) and the gate layer (6) are formed in the same process step.
8. An array substrate prepared by the method of any one of claims 1 to 7.
9. A display screen comprising the array substrate of claim 8.
10. A display device characterized by comprising a display screen as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910138428.5A CN109950252B (en) | 2019-02-25 | 2019-02-25 | Manufacturing method of array substrate, display screen and display equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910138428.5A CN109950252B (en) | 2019-02-25 | 2019-02-25 | Manufacturing method of array substrate, display screen and display equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109950252A CN109950252A (en) | 2019-06-28 |
| CN109950252B true CN109950252B (en) | 2021-02-12 |
Family
ID=67006960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910138428.5A Active CN109950252B (en) | 2019-02-25 | 2019-02-25 | Manufacturing method of array substrate, display screen and display equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950252B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110993624A (en) * | 2019-12-16 | 2020-04-10 | 云谷（固安）科技有限公司 | Flexible display panel, preparation method thereof and flexible display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425044B (en) * | 2017-08-04 | 2021-03-23 | 京东方科技集团股份有限公司 | Flexible display panel, manufacturing method thereof and display device |
| CN108054192B (en) * | 2018-01-19 | 2019-12-24 | 武汉华星光电半导体显示技术有限公司 | Flexible AMOLED substrate and manufacturing method thereof |
| CN108898955A (en) * | 2018-07-31 | 2018-11-27 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| CN109148381B (en) * | 2018-08-24 | 2020-11-20 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
-
2019
- 2019-02-25 CN CN201910138428.5A patent/CN109950252B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109950252A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110649177A (en) | Preparation method of display panel, display panel and display device | |
| CN107221501B (en) | Vertical thin film transistor and preparation method thereof | |
| WO2016023294A1 (en) | Array substrate, manufacturing method and display device | |
| TWI418903B (en) | Array structure and manufacturing method thereof | |
| CN104600079A (en) | Liquid crystal display device, thin film transistor array substrate and manufacturing method thereof | |
| CN108962948B (en) | Array substrate and manufacturing method thereof | |
| US8901565B2 (en) | Thin film transistor comprising pixel electrode | |
| EP3089214B1 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN114122296B (en) | Display backboard, manufacturing method thereof and display device | |
| TW200931669A (en) | Active matrix array structure and manufacturing method thereof | |
| WO2017202188A1 (en) | Display substrate manufacturing method, display substrate and display device. | |
| US20210408472A1 (en) | Display substrate, display apparatus, and method of fabricating display substrate | |
| WO2018205886A1 (en) | Thin film transistor and manufacturing method therefor, array substrate and display apparatus | |
| JP2008139619A (en) | Liquid crystal display and manufacturing method therefor | |
| CN108231846B (en) | Display substrate, preparation method thereof and display device | |
| CN109950252B (en) | Manufacturing method of array substrate, display screen and display equipment | |
| CN102436104B (en) | Pixel structure and manufacturing method thereof | |
| US20100244039A1 (en) | Pixel structure | |
| CN107910351B (en) | Manufacturing method of TFT substrate | |
| CN109427785B (en) | Device including capacitor and method of forming the same | |
| CN107068612B (en) | Manufacturing method of via hole, manufacturing method of display substrate and display substrate | |
| CN109390413A (en) | A kind of thin film transistor and its manufacturing method, array substrate, display device | |
| CN100483233C (en) | Pixel structure of panel display device and method for fabricating same | |
| CN108333845A (en) | The production method of array substrate, display panel and array substrate | |
| WO2021056261A1 (en) | Display substrate, display apparatus, and method of fabricating display substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |